derek.holloway
7502bf64a4
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251 lines
11 KiB
C++
251 lines
11 KiB
C++
//===---- RISCVTargetParserTest.cpp - RISCVTargetParser unit tests --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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namespace {
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TEST(RISCVVType, CheckSameRatioLMUL) {
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// Smaller LMUL.
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EXPECT_EQ(RISCVVType::LMUL_1,
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RISCVVType::getSameRatioLMUL(
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RISCVVType::getSEWLMULRatio(16, RISCVVType::LMUL_2), 8));
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EXPECT_EQ(RISCVVType::LMUL_F2,
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RISCVVType::getSameRatioLMUL(
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RISCVVType::getSEWLMULRatio(16, RISCVVType::LMUL_1), 8));
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// Smaller fractional LMUL.
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EXPECT_EQ(RISCVVType::LMUL_F8,
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RISCVVType::getSameRatioLMUL(
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RISCVVType::getSEWLMULRatio(16, RISCVVType::LMUL_F4), 8));
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// Bigger LMUL.
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EXPECT_EQ(RISCVVType::LMUL_2,
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RISCVVType::getSameRatioLMUL(
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RISCVVType::getSEWLMULRatio(8, RISCVVType::LMUL_1), 16));
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EXPECT_EQ(RISCVVType::LMUL_1,
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RISCVVType::getSameRatioLMUL(
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RISCVVType::getSEWLMULRatio(8, RISCVVType::LMUL_F2), 16));
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// Bigger fractional LMUL.
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EXPECT_EQ(RISCVVType::LMUL_F2,
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RISCVVType::getSameRatioLMUL(
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RISCVVType::getSEWLMULRatio(8, RISCVVType::LMUL_F4), 16));
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}
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TEST(RISCVVType, IMEVTypeFields) {
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EXPECT_TRUE(RISCVVType::IME::isValidLambda(0));
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EXPECT_TRUE(RISCVVType::IME::isValidLambda(1));
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EXPECT_TRUE(RISCVVType::IME::isValidLambda(64));
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EXPECT_FALSE(RISCVVType::IME::isValidLambda(3));
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EXPECT_FALSE(RISCVVType::IME::isValidLambda(128));
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EXPECT_EQ(0U, RISCVVType::IME::encodeLambda(0));
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EXPECT_EQ(1U, RISCVVType::IME::encodeLambda(1));
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EXPECT_EQ(3U, RISCVVType::IME::encodeLambda(4));
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EXPECT_EQ(7U, RISCVVType::IME::encodeLambda(64));
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EXPECT_FALSE(RISCVVType::IME::decodeLambda(0));
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EXPECT_EQ(1U, *RISCVVType::IME::decodeLambda(1));
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EXPECT_EQ(4U, *RISCVVType::IME::decodeLambda(3));
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EXPECT_EQ(64U, *RISCVVType::IME::decodeLambda(7));
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unsigned BaseVType =
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RISCVVType::encodeVTYPE(RISCVVType::LMUL_1, 32, /*TailAgnostic=*/true,
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/*MaskAgnostic=*/true);
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uint64_t RV32VType = RISCVVType::IME::addVTypeFields(
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BaseVType, /*XLen=*/32, /*Lambda=*/4, /*AltFmtA=*/true,
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/*AltFmtB=*/false, /*BlockSize16=*/true);
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EXPECT_EQ(0x3c0000d0ULL, RV32VType);
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EXPECT_EQ(0x7e000000ULL, RISCVVType::IME::getVTypeFieldsMask(32));
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EXPECT_EQ(3U, RISCVVType::IME::getLambdaEncoding(RV32VType, 32));
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EXPECT_EQ(4U, *RISCVVType::IME::getLambda(RV32VType, 32));
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EXPECT_TRUE(RISCVVType::IME::isAltFmtA(RV32VType, 32));
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EXPECT_FALSE(RISCVVType::IME::isAltFmtB(RV32VType, 32));
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EXPECT_TRUE(RISCVVType::IME::isBlockSize16(RV32VType, 32));
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uint64_t RV64VType = RISCVVType::IME::addVTypeFields(
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BaseVType, /*XLen=*/64, /*Lambda=*/64, /*AltFmtA=*/true,
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/*AltFmtB=*/true, /*BlockSize16=*/true);
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EXPECT_EQ(0x7e000000000000d0ULL, RV64VType);
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EXPECT_EQ(0x7e00000000000000ULL, RISCVVType::IME::getVTypeFieldsMask(64));
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EXPECT_EQ(7U, RISCVVType::IME::getLambdaEncoding(RV64VType, 64));
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EXPECT_EQ(64U, *RISCVVType::IME::getLambda(RV64VType, 64));
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EXPECT_TRUE(RISCVVType::IME::isAltFmtA(RV64VType, 64));
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EXPECT_TRUE(RISCVVType::IME::isAltFmtB(RV64VType, 64));
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EXPECT_TRUE(RISCVVType::IME::isBlockSize16(RV64VType, 64));
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uint64_t RV64AltFmtAOnly = RISCVVType::IME::addVTypeFields(
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BaseVType, /*XLen=*/64, /*Lambda=*/0, /*AltFmtA=*/true,
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/*AltFmtB=*/false, /*BlockSize16=*/false);
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EXPECT_EQ(0x04000000000000d0ULL, RV64AltFmtAOnly);
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EXPECT_TRUE(RISCVVType::IME::isAltFmtA(RV64AltFmtAOnly, 64));
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EXPECT_FALSE(RISCVVType::IME::isAltFmtB(RV64AltFmtAOnly, 64));
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EXPECT_FALSE(RISCVVType::IME::isBlockSize16(RV64AltFmtAOnly, 64));
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uint64_t RV64BlockSizeOnly = RISCVVType::IME::addVTypeFields(
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BaseVType, /*XLen=*/64, /*Lambda=*/0, /*AltFmtA=*/false,
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/*AltFmtB=*/false, /*BlockSize16=*/true);
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EXPECT_EQ(0x08000000000000d0ULL, RV64BlockSizeOnly);
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EXPECT_FALSE(RISCVVType::IME::isAltFmtA(RV64BlockSizeOnly, 64));
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EXPECT_FALSE(RISCVVType::IME::isAltFmtB(RV64BlockSizeOnly, 64));
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EXPECT_TRUE(RISCVVType::IME::isBlockSize16(RV64BlockSizeOnly, 64));
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uint64_t DynamicLambda = RISCVVType::IME::addVTypeFields(
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BaseVType, /*XLen=*/64, /*Lambda=*/0, /*AltFmtA=*/false,
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/*AltFmtB=*/false, /*BlockSize16=*/false);
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EXPECT_FALSE(RISCVVType::IME::getLambda(DynamicLambda, 64));
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EXPECT_EQ(BaseVType, DynamicLambda);
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}
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TEST(RISCVTuneFeature, AllTuneFeatures) {
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SmallVector<StringRef> AllTuneFeatures;
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RISCV::getAllTuneFeatures(AllTuneFeatures);
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// Only allowed subtarget features that are explicitly marked by
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// special TableGen class.
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EXPECT_EQ(AllTuneFeatures.size(), 20U);
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for (auto F : {"conditional-cmv-fusion",
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"disable-latency-sched-heuristic",
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"disable-misched-load-clustering",
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"disable-misched-store-clustering",
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"disable-postmisched-load-clustering",
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"disable-postmisched-store-clustering",
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"single-element-vec-fp64",
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"no-default-unroll",
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"no-sink-splat-operands",
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"use-postra-scheduler",
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"predictable-select-expensive",
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"prefer-ascending-load-store",
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"prefer-vsetvli-over-read-vlenb",
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"prefer-w-inst",
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"short-forward-branch-ialu",
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"short-forward-branch-iminmax",
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"short-forward-branch-imul",
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"short-forward-branch-iload",
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"vl-dependent-latency",
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"vxrm-pipeline-flush"})
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EXPECT_TRUE(is_contained(AllTuneFeatures, F));
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}
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TEST(RISCVTuneFeature, LegalTuneFeatureStrings) {
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SmallVector<std::string> Result;
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EXPECT_FALSE(errorToBool(RISCV::parseTuneFeatureString(
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/*ProcName=*/"",
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"prefer-w-inst,no-short-forward-branch-ialu,vl-dependent-latency",
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Result)));
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EXPECT_TRUE(is_contained(Result, "+prefer-w-inst"));
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EXPECT_TRUE(is_contained(Result, "+vl-dependent-latency"));
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EXPECT_TRUE(is_contained(Result, "-short-forward-branch-ialu"));
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EXPECT_TRUE(is_contained(Result, "-short-forward-branch-iminmax"));
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EXPECT_TRUE(is_contained(Result, "-short-forward-branch-imul"));
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EXPECT_TRUE(is_contained(Result, "-short-forward-branch-iload"));
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Result.clear();
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// Test inverse implied features.
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EXPECT_FALSE(errorToBool(RISCV::parseTuneFeatureString(
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/*ProcName=*/"",
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"no-short-forward-branch-imul,short-forward-branch-iminmax", Result)));
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EXPECT_TRUE(is_contained(Result, "+short-forward-branch-iminmax"));
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EXPECT_TRUE(is_contained(Result, "+short-forward-branch-ialu"));
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EXPECT_TRUE(is_contained(Result, "-short-forward-branch-imul"));
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Result.clear();
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// Test custom directive names.
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EXPECT_FALSE(errorToBool(
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RISCV::parseTuneFeatureString(/*ProcName=*/"",
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"enable-default-unroll,no-sink-splat-"
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"operands,enable-latency-sched-heuristic",
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Result)));
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EXPECT_TRUE(is_contained(Result, "+no-sink-splat-operands"));
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EXPECT_TRUE(is_contained(Result, "-no-default-unroll"));
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EXPECT_TRUE(is_contained(Result, "-disable-latency-sched-heuristic"));
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}
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TEST(RISCVTuneFeature, IgnoreUnrecognizedTuneFeature) {
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SmallVector<std::string> Result;
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auto Err = RISCV::parseTuneFeatureString(/*ProcName=*/"",
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"32bit,prefer-w-inst", Result);
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// This should be an warning.
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EXPECT_TRUE(Err.isA<RISCV::ParserWarning>());
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EXPECT_EQ(toString(std::move(Err)),
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"unrecognized tune feature directive '32bit'");
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EXPECT_TRUE(is_contained(Result, "+prefer-w-inst"));
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}
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TEST(RISCVTuneFeature, DuplicatedFeatures) {
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SmallVector<std::string> Result;
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EXPECT_EQ(toString(RISCV::parseTuneFeatureString(
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/*ProcName=*/"", "prefer-w-inst,prefer-w-inst", Result)),
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"cannot specify more than one instance of 'prefer-w-inst'");
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EXPECT_EQ(toString(RISCV::parseTuneFeatureString(
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/*ProcName=*/"",
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"prefer-w-inst,no-prefer-w-inst,short-forward-branch-imul,no-"
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"short-forward-branch-imul",
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Result)),
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"Feature(s) 'prefer-w-inst', 'short-forward-branch-imul' cannot "
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"appear in both positive and negative directives");
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// The error message should show the feature name for those using custom
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// directives.
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EXPECT_EQ(
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toString(RISCV::parseTuneFeatureString(
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/*ProcName=*/"",
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"disable-latency-sched-heuristic,enable-latency-sched-heuristic",
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Result)),
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"Feature(s) 'disable-latency-sched-heuristic' cannot appear in both "
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"positive and negative directives");
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EXPECT_EQ(
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toString(RISCV::parseTuneFeatureString(
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/*ProcName=*/"",
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"short-forward-branch-imul,no-short-forward-branch-ialu", Result)),
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"Feature(s) 'short-forward-branch-imul', 'short-forward-branch-ialu' "
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"were implied by both positive and negative directives");
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}
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TEST(RISCVTuneFeature, ProcConfigurableFeatures) {
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SmallVector<std::string> Result;
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EXPECT_FALSE(errorToBool(RISCV::parseTuneFeatureString(
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"sifive-x280", "single-element-vec-fp64", Result)));
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EXPECT_TRUE(is_contained(Result, "+single-element-vec-fp64"));
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Result.clear();
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EXPECT_EQ(
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toString(RISCV::parseTuneFeatureString(
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"sifive-x280", "single-element-vec-fp64,prefer-w-inst", Result)),
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"Directive 'prefer-w-inst' is not allowed to be used with processor "
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"'sifive-x280'");
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}
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TEST(RISCVTuneFeature, AllProcConfigurableFeatures) {
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SmallVector<StringRef> Result;
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RISCV::getCPUConfigurableTuneFeatures("sifive-x280", Result);
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EXPECT_TRUE(is_contained(Result, "single-element-vec-fp64"));
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EXPECT_TRUE(is_contained(Result, "full-vec-fp64"));
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EXPECT_EQ(Result.size(), 2U);
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Result.clear();
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RISCV::getCPUConfigurableTuneFeatures("sifive-x390", Result);
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EXPECT_TRUE(is_contained(Result, "single-element-vec-fp64"));
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EXPECT_TRUE(is_contained(Result, "full-vec-fp64"));
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EXPECT_EQ(Result.size(), 2U);
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Result.clear();
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RISCV::getCPUConfigurableTuneFeatures("sifive-x180", Result);
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EXPECT_TRUE(is_contained(Result, "single-element-vec-fp64"));
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EXPECT_TRUE(is_contained(Result, "full-vec-fp64"));
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EXPECT_EQ(Result.size(), 2U);
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Result.clear();
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RISCV::getCPUConfigurableTuneFeatures("rocket", Result);
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EXPECT_TRUE(Result.empty());
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}
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} // namespace
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