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TheRock/debug-tools/rocgdb/source/sim/testsuite/sh/div.s
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Flatten subprojects into a single base monorepo
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# sh testcase for divs and divu
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
divs_1: ! divide by one
set_grs_a5a5
mov #1, r0
divs r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_2: ! divide by two
set_grs_a5a5
mov #2, r0
divs r0, r1
assertreg0 2
assertreg 0xd2d2d2d3, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_3: ! divide by three
set_grs_a5a5
mov #3, r0
divs r0, r1
assertreg0 3
assertreg 0xe1e1e1e2, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_0: ! divide by zero
set_grs_a5a5
mov #0, r0
divs r0, r1
assertreg0 0
assertreg 0x7fffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divs_o: ! divide signed overflow
set_grs_a5a5
mov #16, r0
movi20 #0x8000, r1
shad r0, r1 ! r1 == 0x80000000
mov #-1, r0
divs r0, r1
assertreg0 -1
assertreg 0x7fffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_1: ! divide by one, unsigned
set_grs_a5a5
mov #1, r0
divu r0, r1
assertreg0 1
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_2: ! divide by two, unsigned
set_grs_a5a5
mov #2, r0
divu r0, r1
assertreg0 2
assertreg 0x52d2d2d2, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_3: ! divide by three, unsigned
set_grs_a5a5
mov #3, r0
divu r0, r1
assertreg0 3
assertreg 0x37373737, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
divu_0: ! divide by zero, unsigned
set_grs_a5a5
mov #0, r0
divu r0, r1
assertreg0 0
assertreg 0xffffffff, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
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