derek.holloway
7502bf64a4
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133 lines
3.7 KiB
LLVM
133 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=RV32
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; RUN: llc -mtriple=riscv64-none-elf -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=RV64
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define i32 @mask_pair(i32 %x, i32 %y) {
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; RV32-LABEL: mask_pair:
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; RV32: # %bb.0:
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; RV32-NEXT: srl a0, a0, a1
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; RV32-NEXT: sll a0, a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: mask_pair:
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; RV64: # %bb.0:
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; RV64-NEXT: srlw a0, a0, a1
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; RV64-NEXT: sllw a0, a0, a1
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; RV64-NEXT: ret
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%shl = shl nsw i32 -1, %y
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%and = and i32 %shl, %x
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ret i32 %and
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}
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define i64 @mask_pair_64(i64 %x, i64 %y) {
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; RV32-LABEL: mask_pair_64:
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; RV32: # %bb.0:
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; RV32-NEXT: li a3, -1
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; RV32-NEXT: addi a4, a2, -32
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; RV32-NEXT: sll a3, a3, a2
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; RV32-NEXT: bltz a4, .LBB1_2
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; RV32-NEXT: # %bb.1:
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; RV32-NEXT: mv a2, a3
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; RV32-NEXT: j .LBB1_3
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; RV32-NEXT: .LBB1_2:
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; RV32-NEXT: not a2, a2
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; RV32-NEXT: lui a5, 524288
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; RV32-NEXT: addi a5, a5, -1
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; RV32-NEXT: srl a2, a5, a2
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; RV32-NEXT: or a2, a3, a2
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; RV32-NEXT: .LBB1_3:
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; RV32-NEXT: srai a4, a4, 31
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; RV32-NEXT: and a3, a4, a3
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; RV32-NEXT: and a1, a2, a1
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; RV32-NEXT: and a0, a3, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: mask_pair_64:
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; RV64: # %bb.0:
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; RV64-NEXT: srl a0, a0, a1
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; RV64-NEXT: sll a0, a0, a1
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; RV64-NEXT: ret
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%shl = shl nsw i64 -1, %y
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%and = and i64 %shl, %x
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ret i64 %and
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}
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define i128 @mask_pair_128(i128 %x, i128 %y) {
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; RV32-LABEL: mask_pair_128:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -32
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; RV32-NEXT: .cfi_def_cfa_offset 32
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; RV32-NEXT: lw a5, 0(a1)
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; RV32-NEXT: lw a4, 4(a1)
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; RV32-NEXT: lw a3, 8(a1)
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; RV32-NEXT: lw a1, 12(a1)
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; RV32-NEXT: lw a2, 0(a2)
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; RV32-NEXT: li a6, -1
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; RV32-NEXT: sw zero, 0(sp)
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; RV32-NEXT: sw zero, 4(sp)
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; RV32-NEXT: sw zero, 8(sp)
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; RV32-NEXT: sw zero, 12(sp)
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; RV32-NEXT: addi a7, sp, 16
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; RV32-NEXT: sw a6, 16(sp)
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; RV32-NEXT: sw a6, 20(sp)
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; RV32-NEXT: sw a6, 24(sp)
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; RV32-NEXT: sw a6, 28(sp)
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; RV32-NEXT: srli a6, a2, 3
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; RV32-NEXT: andi a6, a6, 12
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; RV32-NEXT: sub a6, a7, a6
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; RV32-NEXT: lw a7, 4(a6)
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; RV32-NEXT: lw t0, 8(a6)
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; RV32-NEXT: lw t1, 12(a6)
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; RV32-NEXT: lw a6, 0(a6)
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; RV32-NEXT: andi t2, a2, 31
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; RV32-NEXT: xori t2, t2, 31
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; RV32-NEXT: sll t1, t1, a2
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; RV32-NEXT: srli t3, t0, 1
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; RV32-NEXT: sll t0, t0, a2
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; RV32-NEXT: srli t4, a7, 1
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; RV32-NEXT: sll a7, a7, a2
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; RV32-NEXT: sll a2, a6, a2
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; RV32-NEXT: srli a6, a6, 1
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; RV32-NEXT: srl t3, t3, t2
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; RV32-NEXT: srl t4, t4, t2
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; RV32-NEXT: srl a6, a6, t2
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; RV32-NEXT: and a2, a2, a5
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; RV32-NEXT: or a5, t1, t3
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; RV32-NEXT: or t0, t0, t4
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; RV32-NEXT: or a6, a7, a6
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; RV32-NEXT: and a4, a6, a4
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; RV32-NEXT: and a3, t0, a3
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; RV32-NEXT: and a1, a5, a1
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; RV32-NEXT: sw a2, 0(a0)
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; RV32-NEXT: sw a4, 4(a0)
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; RV32-NEXT: sw a3, 8(a0)
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; RV32-NEXT: sw a1, 12(a0)
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; RV32-NEXT: addi sp, sp, 32
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; RV32-NEXT: .cfi_def_cfa_offset 0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: mask_pair_128:
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; RV64: # %bb.0:
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; RV64-NEXT: li a5, -1
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; RV64-NEXT: addi a4, a2, -64
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; RV64-NEXT: sll a3, a5, a2
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; RV64-NEXT: bltz a4, .LBB2_2
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; RV64-NEXT: # %bb.1:
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; RV64-NEXT: mv a2, a3
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; RV64-NEXT: j .LBB2_3
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; RV64-NEXT: .LBB2_2:
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; RV64-NEXT: not a2, a2
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; RV64-NEXT: srli a5, a5, 1
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; RV64-NEXT: srl a2, a5, a2
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; RV64-NEXT: or a2, a3, a2
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; RV64-NEXT: .LBB2_3:
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; RV64-NEXT: srai a4, a4, 63
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; RV64-NEXT: and a3, a4, a3
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; RV64-NEXT: and a1, a2, a1
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; RV64-NEXT: and a0, a3, a0
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; RV64-NEXT: ret
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%shl = shl nsw i128 -1, %y
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%and = and i128 %shl, %x
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ret i128 %and
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}
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