derek.holloway
7502bf64a4
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124 lines
2.4 KiB
Plaintext
124 lines
2.4 KiB
Plaintext
ChangeLog
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See the ChangeLog file looking for lines taged with the word FIXME.
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COREFILE.C:
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The implementation of corefile.c (defined by corefile.h) isn't the
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best. It is intended to be functionaly correct rather than fast. One
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option being considered is to add a data cache to reduce the overhead
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of the most common case of data read/writes.
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VEA:
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Missing VEA system calls.
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powerpc.igen:
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Missing or commented out instructions.
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64bit:
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64bit target untested. 64bit host broken. For instance use of scanf
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"%x", &long long.
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hw_*.c:
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Better and more devices.
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PORTABILITY:
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(Notes taken from Michael Meissner): Heavy use of the ## operator -
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fix using the classic X/**/Y hack; Use of the signed keyword. In
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particular, signed char has no analogue in classic C (though most
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implementations of classic C use signed chars); Use of long long which
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restricts the target compiler to be GCC.
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TRACING:
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debug.c: Macro's should be extended to include:
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IS_*TRACE: True if tracing enabled
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*TRACE_PREFIX: Outputs just the prefix line
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hw_trace.c: Flush, replace with a psim_set_tracing or some
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such program.
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CIA/NIA:
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Replace with functions to return/increment the CIA?
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SMP & GDB:
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GDB doesn't understand SMP!
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OVERALL STRUCTURE:
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A new file pstruct.h is to be created that contains a single flat data
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structure containing:
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pstruct {
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events;
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core;
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processor[nr_cpus];
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monitor;
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devices;
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trace;
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}
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The CPU's structure, in turn would contain the VM sub structures.
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When SMP==0, everything would have PSTRUCT passed. In SMP mode,
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however, there are two choices: PSTRUCT + CPU_NR or PROCESSOR. I
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suspect the latter is better.
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It is believed that this would significantly improve performance (at
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the price of reduced control over object scope).
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IGEN:
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Igen at present can't do the following:
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o duplication is an all or nothing affair.
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It should be configurable according to
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the instruction or the sub-table.
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o Due to the naming, only a single generated
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simulator can be included in a program.
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IGEN should be able to generate multiple
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engines that can all be included in a program
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o handle alternate architectures.
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o Igen should support the generation of a
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disasembler and posibly an assembler.
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I suggest that the table be extended to
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include, for each instruction, additional
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lines describing the extual format of the
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instruction.
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One possible format is:
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"mtlr %RS":SPR.something
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"mtspr %SPR, %RS"
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