derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
95063 lines
4.3 MiB
Plaintext
95063 lines
4.3 MiB
Plaintext
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
|
|
|
; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
|
|
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
|
|
|
|
define <16 x float> @bitcast_v16i32_to_v16f32(<16 x i32> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v16f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB0_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: .LBB0_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v16f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB0_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: .LBB0_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v16f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB0_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
|
|
; GFX9-NEXT: .LBB0_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v16f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB0_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
|
|
; GFX11-NEXT: .LBB0_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define inreg <16 x float> @bitcast_v16i32_to_v16f32_scalar(<16 x i32> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v16f32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB1_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB1_3
|
|
; SI-NEXT: .LBB1_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s6, s6, 3
|
|
; SI-NEXT: s_add_i32 s7, s7, 3
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: .LBB1_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s7
|
|
; SI-NEXT: v_mov_b32_e32 v15, s6
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB1_4:
|
|
; SI-NEXT: s_branch .LBB1_2
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v16f32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB1_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB1_3
|
|
; VI-NEXT: .LBB1_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_add_i32 s7, s7, 3
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: s_add_i32 s23, s23, 3
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: s_add_i32 s21, s21, 3
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: s_add_i32 s19, s19, 3
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: s_add_i32 s17, s17, 3
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: .LBB1_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB1_4:
|
|
; VI-NEXT: s_branch .LBB1_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v16f32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB1_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB1_3
|
|
; GFX9-NEXT: .LBB1_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX9-NEXT: s_add_i32 s29, s29, 3
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: .LBB1_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB1_4:
|
|
; GFX9-NEXT: s_branch .LBB1_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v16f32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB1_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB1_3
|
|
; GFX11-NEXT: .LBB1_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX11-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX11-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX11-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX11-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX11-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX11-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-NEXT: s_add_i32 s3, s3, 3
|
|
; GFX11-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-NEXT: s_add_i32 s1, s1, 3
|
|
; GFX11-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-NEXT: .LBB1_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB1_4:
|
|
; GFX11-NEXT: s_branch .LBB1_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define <16 x i32> @bitcast_v16f32_to_v16i32(<16 x float> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v16i32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB2_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: .LBB2_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v16i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB2_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: .LBB2_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v16i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB2_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX9-NEXT: .LBB2_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v16i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB2_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
|
|
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
|
|
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
|
|
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
|
|
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
|
|
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
|
|
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
|
|
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
|
|
; GFX11-NEXT: .LBB2_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define inreg <16 x i32> @bitcast_v16f32_to_v16i32_scalar(<16 x float> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v16i32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB3_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB3_4
|
|
; SI-NEXT: .LBB3_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; SI-NEXT: s_branch .LBB3_5
|
|
; SI-NEXT: .LBB3_3:
|
|
; SI-NEXT: s_branch .LBB3_2
|
|
; SI-NEXT: .LBB3_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s30
|
|
; SI-NEXT: v_mov_b32_e32 v15, s31
|
|
; SI-NEXT: .LBB3_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; SI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v16i32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB3_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB3_4
|
|
; VI-NEXT: .LBB3_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; VI-NEXT: s_branch .LBB3_5
|
|
; VI-NEXT: .LBB3_3:
|
|
; VI-NEXT: s_branch .LBB3_2
|
|
; VI-NEXT: .LBB3_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB3_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v16i32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB3_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB3_4
|
|
; GFX9-NEXT: .LBB3_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; GFX9-NEXT: s_branch .LBB3_5
|
|
; GFX9-NEXT: .LBB3_3:
|
|
; GFX9-NEXT: s_branch .LBB3_2
|
|
; GFX9-NEXT: .LBB3_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB3_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v16i32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB3_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB3_4
|
|
; GFX11-NEXT: .LBB3_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f32_e64 v15, s27, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v14, s26, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB3_3:
|
|
; GFX11-NEXT: s_branch .LBB3_2
|
|
; GFX11-NEXT: .LBB3_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define <8 x i64> @bitcast_v16i32_to_v8i64(<16 x i32> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v8i64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB4_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: .LBB4_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v8i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB4_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: .LBB4_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v8i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB4_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
|
|
; GFX9-NEXT: .LBB4_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v8i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB4_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
|
|
; GFX11-NEXT: .LBB4_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define inreg <8 x i64> @bitcast_v16i32_to_v8i64_scalar(<16 x i32> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v8i64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB5_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB5_3
|
|
; SI-NEXT: .LBB5_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s6, s6, 3
|
|
; SI-NEXT: s_add_i32 s7, s7, 3
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: .LBB5_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s7
|
|
; SI-NEXT: v_mov_b32_e32 v15, s6
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB5_4:
|
|
; SI-NEXT: s_branch .LBB5_2
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v8i64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB5_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB5_3
|
|
; VI-NEXT: .LBB5_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_add_i32 s7, s7, 3
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: s_add_i32 s23, s23, 3
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: s_add_i32 s21, s21, 3
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: s_add_i32 s19, s19, 3
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: s_add_i32 s17, s17, 3
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: .LBB5_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB5_4:
|
|
; VI-NEXT: s_branch .LBB5_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v8i64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB5_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB5_3
|
|
; GFX9-NEXT: .LBB5_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX9-NEXT: s_add_i32 s29, s29, 3
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: .LBB5_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB5_4:
|
|
; GFX9-NEXT: s_branch .LBB5_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v8i64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB5_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB5_3
|
|
; GFX11-NEXT: .LBB5_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX11-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX11-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX11-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX11-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX11-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX11-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-NEXT: s_add_i32 s3, s3, 3
|
|
; GFX11-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-NEXT: s_add_i32 s1, s1, 3
|
|
; GFX11-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-NEXT: .LBB5_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB5_4:
|
|
; GFX11-NEXT: s_branch .LBB5_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define <16 x i32> @bitcast_v8i64_to_v16i32(<8 x i64> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v16i32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB6_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; SI-NEXT: .LBB6_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v16i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB6_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: .LBB6_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v16i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB6_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: .LBB6_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v16i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB6_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
|
|
; GFX11-NEXT: .LBB6_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define inreg <16 x i32> @bitcast_v8i64_to_v16i32_scalar(<8 x i64> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v16i32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB7_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB7_3
|
|
; SI-NEXT: .LBB7_2: ; %cmp.true
|
|
; SI-NEXT: s_add_u32 s7, s7, 3
|
|
; SI-NEXT: s_addc_u32 s6, s6, 0
|
|
; SI-NEXT: s_add_u32 s28, s28, 3
|
|
; SI-NEXT: s_addc_u32 s29, s29, 0
|
|
; SI-NEXT: s_add_u32 s26, s26, 3
|
|
; SI-NEXT: s_addc_u32 s27, s27, 0
|
|
; SI-NEXT: s_add_u32 s24, s24, 3
|
|
; SI-NEXT: s_addc_u32 s25, s25, 0
|
|
; SI-NEXT: s_add_u32 s22, s22, 3
|
|
; SI-NEXT: s_addc_u32 s23, s23, 0
|
|
; SI-NEXT: s_add_u32 s20, s20, 3
|
|
; SI-NEXT: s_addc_u32 s21, s21, 0
|
|
; SI-NEXT: s_add_u32 s18, s18, 3
|
|
; SI-NEXT: s_addc_u32 s19, s19, 0
|
|
; SI-NEXT: s_add_u32 s16, s16, 3
|
|
; SI-NEXT: s_addc_u32 s17, s17, 0
|
|
; SI-NEXT: .LBB7_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s7
|
|
; SI-NEXT: v_mov_b32_e32 v15, s6
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB7_4:
|
|
; SI-NEXT: s_branch .LBB7_2
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v16i32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB7_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB7_3
|
|
; VI-NEXT: .LBB7_2: ; %cmp.true
|
|
; VI-NEXT: s_add_u32 s7, s7, 3
|
|
; VI-NEXT: s_addc_u32 s6, s6, 0
|
|
; VI-NEXT: s_add_u32 s28, s28, 3
|
|
; VI-NEXT: s_addc_u32 s29, s29, 0
|
|
; VI-NEXT: s_add_u32 s26, s26, 3
|
|
; VI-NEXT: s_addc_u32 s27, s27, 0
|
|
; VI-NEXT: s_add_u32 s24, s24, 3
|
|
; VI-NEXT: s_addc_u32 s25, s25, 0
|
|
; VI-NEXT: s_add_u32 s22, s22, 3
|
|
; VI-NEXT: s_addc_u32 s23, s23, 0
|
|
; VI-NEXT: s_add_u32 s20, s20, 3
|
|
; VI-NEXT: s_addc_u32 s21, s21, 0
|
|
; VI-NEXT: s_add_u32 s18, s18, 3
|
|
; VI-NEXT: s_addc_u32 s19, s19, 0
|
|
; VI-NEXT: s_add_u32 s16, s16, 3
|
|
; VI-NEXT: s_addc_u32 s17, s17, 0
|
|
; VI-NEXT: .LBB7_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB7_4:
|
|
; VI-NEXT: s_branch .LBB7_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v16i32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB7_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB7_3
|
|
; GFX9-NEXT: .LBB7_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_u32 s7, s7, 3
|
|
; GFX9-NEXT: s_addc_u32 s6, s6, 0
|
|
; GFX9-NEXT: s_add_u32 s28, s28, 3
|
|
; GFX9-NEXT: s_addc_u32 s29, s29, 0
|
|
; GFX9-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX9-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX9-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX9-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX9-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX9-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX9-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX9-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX9-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX9-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX9-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX9-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX9-NEXT: .LBB7_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB7_4:
|
|
; GFX9-NEXT: s_branch .LBB7_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v16i32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB7_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB7_3
|
|
; GFX11-NEXT: .LBB7_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX11-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX11-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX11-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX11-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX11-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX11-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX11-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX11-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX11-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX11-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX11-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX11-NEXT: s_add_u32 s2, s2, 3
|
|
; GFX11-NEXT: s_addc_u32 s3, s3, 0
|
|
; GFX11-NEXT: s_add_u32 s0, s0, 3
|
|
; GFX11-NEXT: s_addc_u32 s1, s1, 0
|
|
; GFX11-NEXT: .LBB7_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB7_4:
|
|
; GFX11-NEXT: s_branch .LBB7_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define <8 x double> @bitcast_v16i32_to_v8f64(<16 x i32> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v8f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB8_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: .LBB8_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v8f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB8_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: .LBB8_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v8f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB8_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
|
|
; GFX9-NEXT: .LBB8_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v8f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB8_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
|
|
; GFX11-NEXT: .LBB8_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define inreg <8 x double> @bitcast_v16i32_to_v8f64_scalar(<16 x i32> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v8f64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB9_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB9_3
|
|
; SI-NEXT: .LBB9_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s6, s6, 3
|
|
; SI-NEXT: s_add_i32 s7, s7, 3
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: .LBB9_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s7
|
|
; SI-NEXT: v_mov_b32_e32 v15, s6
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB9_4:
|
|
; SI-NEXT: s_branch .LBB9_2
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v8f64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB9_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB9_3
|
|
; VI-NEXT: .LBB9_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_add_i32 s7, s7, 3
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: s_add_i32 s23, s23, 3
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: s_add_i32 s21, s21, 3
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: s_add_i32 s19, s19, 3
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: s_add_i32 s17, s17, 3
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: .LBB9_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB9_4:
|
|
; VI-NEXT: s_branch .LBB9_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v8f64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB9_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB9_3
|
|
; GFX9-NEXT: .LBB9_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX9-NEXT: s_add_i32 s29, s29, 3
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: .LBB9_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB9_4:
|
|
; GFX9-NEXT: s_branch .LBB9_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v8f64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB9_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB9_3
|
|
; GFX11-NEXT: .LBB9_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX11-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX11-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX11-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX11-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX11-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX11-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-NEXT: s_add_i32 s3, s3, 3
|
|
; GFX11-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-NEXT: s_add_i32 s1, s1, 3
|
|
; GFX11-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-NEXT: .LBB9_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB9_4:
|
|
; GFX11-NEXT: s_branch .LBB9_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define <16 x i32> @bitcast_v8f64_to_v16i32(<8 x double> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v16i32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB10_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: .LBB10_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v16i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB10_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: .LBB10_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v16i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB10_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX9-NEXT: .LBB10_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v16i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB10_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: .LBB10_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define inreg <16 x i32> @bitcast_v8f64_to_v16i32_scalar(<8 x double> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v16i32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB11_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB11_4
|
|
; SI-NEXT: .LBB11_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; SI-NEXT: s_branch .LBB11_5
|
|
; SI-NEXT: .LBB11_3:
|
|
; SI-NEXT: s_branch .LBB11_2
|
|
; SI-NEXT: .LBB11_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s30
|
|
; SI-NEXT: v_mov_b32_e32 v15, s31
|
|
; SI-NEXT: .LBB11_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; SI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v16i32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB11_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB11_4
|
|
; VI-NEXT: .LBB11_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; VI-NEXT: s_branch .LBB11_5
|
|
; VI-NEXT: .LBB11_3:
|
|
; VI-NEXT: s_branch .LBB11_2
|
|
; VI-NEXT: .LBB11_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB11_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v16i32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB11_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB11_4
|
|
; GFX9-NEXT: .LBB11_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; GFX9-NEXT: s_branch .LBB11_5
|
|
; GFX9-NEXT: .LBB11_3:
|
|
; GFX9-NEXT: s_branch .LBB11_2
|
|
; GFX9-NEXT: .LBB11_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB11_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v16i32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB11_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB11_4
|
|
; GFX11-NEXT: .LBB11_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], s[26:27], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB11_3:
|
|
; GFX11-NEXT: s_branch .LBB11_2
|
|
; GFX11-NEXT: .LBB11_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define <32 x i16> @bitcast_v16i32_to_v32i16(<16 x i32> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v32i16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB12_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB12_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB12_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB12_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v24
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v27
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v24
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v32i16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB12_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: .LBB12_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v32i16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB12_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
|
|
; GFX9-NEXT: .LBB12_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v32i16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB12_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
|
|
; GFX11-NEXT: .LBB12_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define inreg <32 x i16> @bitcast_v16i32_to_v32i16_scalar(<16 x i32> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v32i16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB13_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s56, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB13_3
|
|
; SI-NEXT: .LBB13_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s5, s5, 3
|
|
; SI-NEXT: s_add_i32 s4, s4, 3
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b32 s56, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s17, 16
|
|
; SI-NEXT: .LBB13_3: ; %end
|
|
; SI-NEXT: s_and_b32 s7, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s44, 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s11, s63, 16
|
|
; SI-NEXT: s_or_b32 s9, s9, s11
|
|
; SI-NEXT: s_and_b32 s11, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s13, s42, 16
|
|
; SI-NEXT: s_or_b32 s11, s11, s13
|
|
; SI-NEXT: s_and_b32 s13, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s15, s62, 16
|
|
; SI-NEXT: s_or_b32 s13, s13, s15
|
|
; SI-NEXT: s_and_b32 s15, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s40, 16
|
|
; SI-NEXT: s_or_b32 s15, s15, s16
|
|
; SI-NEXT: s_and_b32 s16, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s17, s61, 16
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_or_b32 s14, s17, s14
|
|
; SI-NEXT: s_and_b32 s17, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s18, s60, 16
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_and_b32 s18, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_or_b32 s12, s18, s12
|
|
; SI-NEXT: s_and_b32 s18, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s19, s59, 16
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_and_b32 s19, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_or_b32 s10, s19, s10
|
|
; SI-NEXT: s_and_b32 s19, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s58, 16
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_and_b32 s20, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_or_b32 s8, s20, s8
|
|
; SI-NEXT: s_and_b32 s20, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s21, s57, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s56, 16
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_or_b32 s5, s5, s6
|
|
; SI-NEXT: v_mov_b32_e32 v0, s7
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
|
; SI-NEXT: v_mov_b32_e32 v2, s11
|
|
; SI-NEXT: v_mov_b32_e32 v3, s13
|
|
; SI-NEXT: v_mov_b32_e32 v4, s15
|
|
; SI-NEXT: v_mov_b32_e32 v5, s16
|
|
; SI-NEXT: v_mov_b32_e32 v6, s14
|
|
; SI-NEXT: v_mov_b32_e32 v7, s17
|
|
; SI-NEXT: v_mov_b32_e32 v8, s12
|
|
; SI-NEXT: v_mov_b32_e32 v9, s18
|
|
; SI-NEXT: v_mov_b32_e32 v10, s10
|
|
; SI-NEXT: v_mov_b32_e32 v11, s19
|
|
; SI-NEXT: v_mov_b32_e32 v12, s8
|
|
; SI-NEXT: v_mov_b32_e32 v13, s20
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB13_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: s_branch .LBB13_2
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v32i16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB13_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB13_3
|
|
; VI-NEXT: .LBB13_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_add_i32 s7, s7, 3
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: s_add_i32 s23, s23, 3
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: s_add_i32 s21, s21, 3
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: s_add_i32 s19, s19, 3
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: s_add_i32 s17, s17, 3
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: .LBB13_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB13_4:
|
|
; VI-NEXT: s_branch .LBB13_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v32i16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB13_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB13_3
|
|
; GFX9-NEXT: .LBB13_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX9-NEXT: s_add_i32 s29, s29, 3
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: .LBB13_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB13_4:
|
|
; GFX9-NEXT: s_branch .LBB13_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v32i16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB13_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB13_3
|
|
; GFX11-NEXT: .LBB13_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX11-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX11-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX11-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX11-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX11-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX11-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-NEXT: s_add_i32 s3, s3, 3
|
|
; GFX11-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-NEXT: s_add_i32 s1, s1, 3
|
|
; GFX11-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-NEXT: .LBB13_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB13_4:
|
|
; GFX11-NEXT: s_branch .LBB13_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define <16 x i32> @bitcast_v32i16_to_v16i32(<32 x i16> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v16i32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v32, v15
|
|
; SI-NEXT: v_mov_b32_e32 v17, v14
|
|
; SI-NEXT: v_mov_b32_e32 v18, v13
|
|
; SI-NEXT: v_mov_b32_e32 v19, v12
|
|
; SI-NEXT: v_mov_b32_e32 v20, v11
|
|
; SI-NEXT: v_mov_b32_e32 v21, v10
|
|
; SI-NEXT: v_mov_b32_e32 v22, v9
|
|
; SI-NEXT: v_mov_b32_e32 v23, v8
|
|
; SI-NEXT: v_mov_b32_e32 v24, v7
|
|
; SI-NEXT: v_mov_b32_e32 v25, v6
|
|
; SI-NEXT: v_mov_b32_e32 v26, v5
|
|
; SI-NEXT: v_mov_b32_e32 v27, v4
|
|
; SI-NEXT: v_mov_b32_e32 v28, v3
|
|
; SI-NEXT: v_mov_b32_e32 v29, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB14_3
|
|
; SI-NEXT: ; %bb.1: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB14_4
|
|
; SI-NEXT: .LBB14_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB14_3: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v55
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v54
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v53
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v51
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v50
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v49
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v39
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v38
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v36
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v35
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v34
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v33
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB14_2
|
|
; SI-NEXT: .LBB14_4: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_or_b32_e32 v0, v55, v0
|
|
; SI-NEXT: s_mov_b32 s6, 0x30000
|
|
; SI-NEXT: v_or_b32_e32 v1, v54, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v53, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v52, v3
|
|
; SI-NEXT: v_or_b32_e32 v4, v51, v4
|
|
; SI-NEXT: v_or_b32_e32 v5, v50, v5
|
|
; SI-NEXT: v_or_b32_e32 v6, v49, v6
|
|
; SI-NEXT: v_or_b32_e32 v7, v48, v7
|
|
; SI-NEXT: v_or_b32_e32 v8, v39, v8
|
|
; SI-NEXT: v_or_b32_e32 v9, v38, v9
|
|
; SI-NEXT: v_or_b32_e32 v10, v37, v10
|
|
; SI-NEXT: v_or_b32_e32 v11, v36, v11
|
|
; SI-NEXT: v_or_b32_e32 v12, v35, v12
|
|
; SI-NEXT: v_or_b32_e32 v13, v34, v13
|
|
; SI-NEXT: v_or_b32_e32 v14, v33, v14
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v16i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB14_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v17, 3
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v15
|
|
; VI-NEXT: v_add_u16_sdwa v15, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v14
|
|
; VI-NEXT: v_add_u16_sdwa v14, v14, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v16, v14
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v13
|
|
; VI-NEXT: v_add_u16_sdwa v13, v13, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v16, v13
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v12
|
|
; VI-NEXT: v_add_u16_sdwa v12, v12, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v11
|
|
; VI-NEXT: v_add_u16_sdwa v11, v11, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v16, v11
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v10
|
|
; VI-NEXT: v_add_u16_sdwa v10, v10, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v16, v10
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v9
|
|
; VI-NEXT: v_add_u16_sdwa v9, v9, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v16, v9
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v8
|
|
; VI-NEXT: v_add_u16_sdwa v8, v8, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v16, v8
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v7
|
|
; VI-NEXT: v_add_u16_sdwa v7, v7, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v16, v7
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v6
|
|
; VI-NEXT: v_add_u16_sdwa v6, v6, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v16, v6
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v5
|
|
; VI-NEXT: v_add_u16_sdwa v5, v5, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v16, v5
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v4
|
|
; VI-NEXT: v_add_u16_sdwa v4, v4, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v3
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v3, v16, v3
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v2
|
|
; VI-NEXT: v_add_u16_sdwa v2, v2, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v16, v2
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v1
|
|
; VI-NEXT: v_add_u16_sdwa v1, v1, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v16, v0
|
|
; VI-NEXT: .LBB14_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v16i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB14_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB14_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v16i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB14_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: .LBB14_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define inreg <16 x i32> @bitcast_v32i16_to_v16i32_scalar(<32 x i16> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v16i32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s36, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s37, 1
|
|
; SI-NEXT: v_writelane_b32 v16, s38, 2
|
|
; SI-NEXT: v_writelane_b32 v16, s39, 3
|
|
; SI-NEXT: v_writelane_b32 v16, s48, 4
|
|
; SI-NEXT: v_writelane_b32 v16, s49, 5
|
|
; SI-NEXT: v_writelane_b32 v16, s50, 6
|
|
; SI-NEXT: v_writelane_b32 v16, s51, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v0
|
|
; SI-NEXT: s_lshr_b32 s6, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s8, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s9, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s12, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB15_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s36, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s37, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s38, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s39, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s44, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s45, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s46, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s47, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 16
|
|
; SI-NEXT: s_or_b32 s48, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 16
|
|
; SI-NEXT: s_or_b32 s49, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s50, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s51, s4, s5
|
|
; SI-NEXT: s_cbranch_execnz .LBB15_3
|
|
; SI-NEXT: .LBB15_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s36, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s37, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s38, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s39, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s40, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s41, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s42, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s43, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s44, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s45, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s46, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s47, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s48, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_add_i32 s49, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s9, s9, 3
|
|
; SI-NEXT: s_add_i32 s50, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s51, s4, 0x30000
|
|
; SI-NEXT: .LBB15_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s39
|
|
; SI-NEXT: v_mov_b32_e32 v4, s40
|
|
; SI-NEXT: v_mov_b32_e32 v5, s41
|
|
; SI-NEXT: v_mov_b32_e32 v6, s42
|
|
; SI-NEXT: v_mov_b32_e32 v7, s43
|
|
; SI-NEXT: v_mov_b32_e32 v8, s44
|
|
; SI-NEXT: v_mov_b32_e32 v9, s45
|
|
; SI-NEXT: v_mov_b32_e32 v10, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s47
|
|
; SI-NEXT: v_mov_b32_e32 v12, s48
|
|
; SI-NEXT: v_mov_b32_e32 v13, s49
|
|
; SI-NEXT: v_mov_b32_e32 v14, s50
|
|
; SI-NEXT: v_mov_b32_e32 v15, s51
|
|
; SI-NEXT: v_readlane_b32 s51, v16, 7
|
|
; SI-NEXT: v_readlane_b32 s50, v16, 6
|
|
; SI-NEXT: v_readlane_b32 s49, v16, 5
|
|
; SI-NEXT: v_readlane_b32 s48, v16, 4
|
|
; SI-NEXT: v_readlane_b32 s39, v16, 3
|
|
; SI-NEXT: v_readlane_b32 s38, v16, 2
|
|
; SI-NEXT: v_readlane_b32 s37, v16, 1
|
|
; SI-NEXT: v_readlane_b32 s36, v16, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB15_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
|
|
; SI-NEXT: s_branch .LBB15_2
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v16i32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB15_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB15_3
|
|
; VI-NEXT: .LBB15_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s5, s6, 3
|
|
; VI-NEXT: s_and_b32 s4, s6, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s7, 3
|
|
; VI-NEXT: s_add_i32 s6, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s7, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s29, 3
|
|
; VI-NEXT: s_add_i32 s7, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s28, 3
|
|
; VI-NEXT: s_add_i32 s29, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s27, 3
|
|
; VI-NEXT: s_add_i32 s28, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s26, 3
|
|
; VI-NEXT: s_add_i32 s27, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s25, 3
|
|
; VI-NEXT: s_add_i32 s26, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s24, 3
|
|
; VI-NEXT: s_add_i32 s25, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s23, 3
|
|
; VI-NEXT: s_add_i32 s24, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s22, 3
|
|
; VI-NEXT: s_add_i32 s23, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s21, 3
|
|
; VI-NEXT: s_add_i32 s22, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s20, 3
|
|
; VI-NEXT: s_add_i32 s21, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s19, 3
|
|
; VI-NEXT: s_add_i32 s20, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s18, 3
|
|
; VI-NEXT: s_add_i32 s19, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s17, 3
|
|
; VI-NEXT: s_add_i32 s18, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s16, 3
|
|
; VI-NEXT: s_add_i32 s17, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s16, s4, 0x30000
|
|
; VI-NEXT: .LBB15_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB15_4:
|
|
; VI-NEXT: s_branch .LBB15_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v16i32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB15_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB15_4
|
|
; GFX9-NEXT: .LBB15_2: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, s31, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, s30, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB15_5
|
|
; GFX9-NEXT: .LBB15_3:
|
|
; GFX9-NEXT: s_branch .LBB15_2
|
|
; GFX9-NEXT: .LBB15_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB15_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v16i32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB15_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB15_4
|
|
; GFX11-NEXT: .LBB15_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB15_3:
|
|
; GFX11-NEXT: s_branch .LBB15_2
|
|
; GFX11-NEXT: .LBB15_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define <32 x half> @bitcast_v16i32_to_v32f16(<16 x i32> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v32f16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB16_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB16_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB16_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB16_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v24
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v27
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v24
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v32f16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB16_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: .LBB16_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v32f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB16_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
|
|
; GFX9-NEXT: .LBB16_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v32f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB16_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
|
|
; GFX11-NEXT: .LBB16_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define inreg <32 x half> @bitcast_v16i32_to_v32f16_scalar(<16 x i32> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v32f16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB17_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s56, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB17_3
|
|
; SI-NEXT: .LBB17_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s5, s5, 3
|
|
; SI-NEXT: s_add_i32 s4, s4, 3
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b32 s56, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s17, 16
|
|
; SI-NEXT: .LBB17_3: ; %end
|
|
; SI-NEXT: s_and_b32 s7, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s44, 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s11, s63, 16
|
|
; SI-NEXT: s_or_b32 s9, s9, s11
|
|
; SI-NEXT: s_and_b32 s11, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s13, s42, 16
|
|
; SI-NEXT: s_or_b32 s11, s11, s13
|
|
; SI-NEXT: s_and_b32 s13, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s15, s62, 16
|
|
; SI-NEXT: s_or_b32 s13, s13, s15
|
|
; SI-NEXT: s_and_b32 s15, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s40, 16
|
|
; SI-NEXT: s_or_b32 s15, s15, s16
|
|
; SI-NEXT: s_and_b32 s16, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s17, s61, 16
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_or_b32 s14, s17, s14
|
|
; SI-NEXT: s_and_b32 s17, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s18, s60, 16
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_and_b32 s18, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_or_b32 s12, s18, s12
|
|
; SI-NEXT: s_and_b32 s18, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s19, s59, 16
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_and_b32 s19, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_or_b32 s10, s19, s10
|
|
; SI-NEXT: s_and_b32 s19, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s58, 16
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_and_b32 s20, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_or_b32 s8, s20, s8
|
|
; SI-NEXT: s_and_b32 s20, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s21, s57, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s56, 16
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_or_b32 s5, s5, s6
|
|
; SI-NEXT: v_mov_b32_e32 v0, s7
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
|
; SI-NEXT: v_mov_b32_e32 v2, s11
|
|
; SI-NEXT: v_mov_b32_e32 v3, s13
|
|
; SI-NEXT: v_mov_b32_e32 v4, s15
|
|
; SI-NEXT: v_mov_b32_e32 v5, s16
|
|
; SI-NEXT: v_mov_b32_e32 v6, s14
|
|
; SI-NEXT: v_mov_b32_e32 v7, s17
|
|
; SI-NEXT: v_mov_b32_e32 v8, s12
|
|
; SI-NEXT: v_mov_b32_e32 v9, s18
|
|
; SI-NEXT: v_mov_b32_e32 v10, s10
|
|
; SI-NEXT: v_mov_b32_e32 v11, s19
|
|
; SI-NEXT: v_mov_b32_e32 v12, s8
|
|
; SI-NEXT: v_mov_b32_e32 v13, s20
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB17_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: s_branch .LBB17_2
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v32f16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB17_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB17_3
|
|
; VI-NEXT: .LBB17_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_add_i32 s7, s7, 3
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: s_add_i32 s23, s23, 3
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: s_add_i32 s21, s21, 3
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: s_add_i32 s19, s19, 3
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: s_add_i32 s17, s17, 3
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: .LBB17_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB17_4:
|
|
; VI-NEXT: s_branch .LBB17_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v32f16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB17_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB17_3
|
|
; GFX9-NEXT: .LBB17_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX9-NEXT: s_add_i32 s29, s29, 3
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: .LBB17_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB17_4:
|
|
; GFX9-NEXT: s_branch .LBB17_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v32f16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB17_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB17_3
|
|
; GFX11-NEXT: .LBB17_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX11-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX11-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX11-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX11-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX11-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX11-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-NEXT: s_add_i32 s3, s3, 3
|
|
; GFX11-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-NEXT: s_add_i32 s1, s1, 3
|
|
; GFX11-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-NEXT: .LBB17_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB17_4:
|
|
; GFX11-NEXT: s_branch .LBB17_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define <16 x i32> @bitcast_v32f16_to_v16i32(<32 x half> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v16i32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v32, v15
|
|
; SI-NEXT: v_mov_b32_e32 v17, v14
|
|
; SI-NEXT: v_mov_b32_e32 v18, v13
|
|
; SI-NEXT: v_mov_b32_e32 v19, v12
|
|
; SI-NEXT: v_mov_b32_e32 v20, v11
|
|
; SI-NEXT: v_mov_b32_e32 v21, v10
|
|
; SI-NEXT: v_mov_b32_e32 v22, v9
|
|
; SI-NEXT: v_mov_b32_e32 v23, v8
|
|
; SI-NEXT: v_mov_b32_e32 v24, v7
|
|
; SI-NEXT: v_mov_b32_e32 v25, v6
|
|
; SI-NEXT: v_mov_b32_e32 v26, v5
|
|
; SI-NEXT: v_mov_b32_e32 v27, v4
|
|
; SI-NEXT: v_mov_b32_e32 v28, v3
|
|
; SI-NEXT: v_mov_b32_e32 v29, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v31
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB18_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: .LBB18_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB18_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v40
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v55
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v31
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v30
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v54
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v29
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v53
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v28
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v27
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v52
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v26
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v50
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v49
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v24
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v48
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v23
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v39
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v22
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v38
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v21
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_or_b32_e32 v9, v11, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v37
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v20
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v36
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v35
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v18
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_or_b32_e32 v12, v14, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v33
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v32
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; SI-NEXT: .LBB18_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v16i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB18_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x200
|
|
; VI-NEXT: v_add_f16_sdwa v17, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v13, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v12, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v11, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v10, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v9, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v8, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v7, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v6, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v5, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v4, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v3, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v1, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
|
|
; VI-NEXT: v_add_f16_sdwa v16, v0, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v17
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: .LBB18_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v16i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB18_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB18_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v16i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB18_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: .LBB18_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define inreg <16 x i32> @bitcast_v32f16_to_v16i32_scalar(<32 x half> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v16i32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v18, s36, 0
|
|
; SI-NEXT: v_writelane_b32 v18, s37, 1
|
|
; SI-NEXT: v_writelane_b32 v18, s38, 2
|
|
; SI-NEXT: v_writelane_b32 v18, s39, 3
|
|
; SI-NEXT: v_writelane_b32 v18, s48, 4
|
|
; SI-NEXT: v_writelane_b32 v18, s49, 5
|
|
; SI-NEXT: v_writelane_b32 v18, s50, 6
|
|
; SI-NEXT: v_writelane_b32 v18, s51, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v0
|
|
; SI-NEXT: s_lshr_b32 s9, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s12, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s6, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s8, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB19_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s36, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s37, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s38, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s39, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s44, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s45, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s46, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s12, 16
|
|
; SI-NEXT: s_or_b32 s47, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s48, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s9, 16
|
|
; SI-NEXT: s_or_b32 s49, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s8, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s50, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s51, s4, s5
|
|
; SI-NEXT: s_cbranch_execnz .LBB19_4
|
|
; SI-NEXT: .LBB19_2: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s63
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s62
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s17
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s61
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s18
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s60
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s19
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s59
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s21
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s57
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s22
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s56
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s23
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s24
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s14
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s25
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s26
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_or_b32_e32 v9, v11, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s27
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s11
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s28
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_or_b32_e32 v12, v14, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, s7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, s6
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; SI-NEXT: s_branch .LBB19_5
|
|
; SI-NEXT: .LBB19_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
|
|
; SI-NEXT: s_branch .LBB19_2
|
|
; SI-NEXT: .LBB19_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s39
|
|
; SI-NEXT: v_mov_b32_e32 v4, s40
|
|
; SI-NEXT: v_mov_b32_e32 v5, s41
|
|
; SI-NEXT: v_mov_b32_e32 v6, s42
|
|
; SI-NEXT: v_mov_b32_e32 v7, s43
|
|
; SI-NEXT: v_mov_b32_e32 v8, s44
|
|
; SI-NEXT: v_mov_b32_e32 v9, s45
|
|
; SI-NEXT: v_mov_b32_e32 v10, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s47
|
|
; SI-NEXT: v_mov_b32_e32 v12, s48
|
|
; SI-NEXT: v_mov_b32_e32 v13, s49
|
|
; SI-NEXT: v_mov_b32_e32 v14, s50
|
|
; SI-NEXT: v_mov_b32_e32 v15, s51
|
|
; SI-NEXT: .LBB19_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s51, v18, 7
|
|
; SI-NEXT: v_readlane_b32 s50, v18, 6
|
|
; SI-NEXT: v_readlane_b32 s49, v18, 5
|
|
; SI-NEXT: v_readlane_b32 s48, v18, 4
|
|
; SI-NEXT: v_readlane_b32 s39, v18, 3
|
|
; SI-NEXT: v_readlane_b32 s38, v18, 2
|
|
; SI-NEXT: v_readlane_b32 s37, v18, 1
|
|
; SI-NEXT: v_readlane_b32 s36, v18, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v16i32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v17, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v17, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB19_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB19_4
|
|
; VI-NEXT: .LBB19_2: ; %cmp.true
|
|
; VI-NEXT: s_lshr_b32 s4, s31, 16
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s31, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s30, 16
|
|
; VI-NEXT: v_or_b32_e32 v15, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s30, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s29, 16
|
|
; VI-NEXT: v_or_b32_e32 v14, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s29, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s28, 16
|
|
; VI-NEXT: v_or_b32_e32 v13, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s28, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s27, 16
|
|
; VI-NEXT: v_or_b32_e32 v12, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s27, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s26, 16
|
|
; VI-NEXT: v_or_b32_e32 v11, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s26, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s25, 16
|
|
; VI-NEXT: v_or_b32_e32 v10, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s25, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s24, 16
|
|
; VI-NEXT: v_or_b32_e32 v9, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s24, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s23, 16
|
|
; VI-NEXT: v_or_b32_e32 v8, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s23, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s22, 16
|
|
; VI-NEXT: v_or_b32_e32 v7, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s22, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s21, 16
|
|
; VI-NEXT: v_or_b32_e32 v6, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s21, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s20, 16
|
|
; VI-NEXT: v_or_b32_e32 v5, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s20, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s19, 16
|
|
; VI-NEXT: v_or_b32_e32 v4, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s19, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s18, 16
|
|
; VI-NEXT: v_or_b32_e32 v3, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s18, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s17, 16
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v16, s17, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s16, 16
|
|
; VI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; VI-NEXT: v_mov_b32_e32 v16, s4
|
|
; VI-NEXT: v_add_f16_sdwa v16, v16, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v0, s16, v0
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: s_branch .LBB19_5
|
|
; VI-NEXT: .LBB19_3:
|
|
; VI-NEXT: s_branch .LBB19_2
|
|
; VI-NEXT: .LBB19_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB19_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v17, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v17, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v16i32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB19_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB19_4
|
|
; GFX9-NEXT: .LBB19_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, s31, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, s30, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB19_5
|
|
; GFX9-NEXT: .LBB19_3:
|
|
; GFX9-NEXT: s_branch .LBB19_2
|
|
; GFX9-NEXT: .LBB19_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB19_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v16i32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB19_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB19_4
|
|
; GFX11-NEXT: .LBB19_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB19_3:
|
|
; GFX11-NEXT: s_branch .LBB19_2
|
|
; GFX11-NEXT: .LBB19_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define <32 x bfloat> @bitcast_v16i32_to_v32bf16(<16 x i32> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v32bf16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB20_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: .LBB20_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB20_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: .LBB20_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v36
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v35
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v28
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v24
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v22
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v18
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v32bf16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB20_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: .LBB20_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v32bf16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB20_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
|
|
; GFX9-NEXT: .LBB20_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v32bf16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB20_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v15, 3, v15
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v14, 3, v14
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v13, 3, v13
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v12, 3, v12
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v11, 3, v11
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v10, 3, v10
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v9, 3, v9
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0
|
|
; GFX11-NEXT: .LBB20_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define inreg <32 x bfloat> @bitcast_v16i32_to_v32bf16_scalar(<16 x i32> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v32bf16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s78, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s79, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB21_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s7, s78, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s6, s78, 16
|
|
; SI-NEXT: s_and_b32 s9, s79, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s8, s79, 16
|
|
; SI-NEXT: s_and_b32 s11, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s10, s29, 16
|
|
; SI-NEXT: s_and_b32 s13, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s12, s28, 16
|
|
; SI-NEXT: s_and_b32 s15, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s14, s27, 16
|
|
; SI-NEXT: s_and_b32 s41, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s40, s26, 16
|
|
; SI-NEXT: s_and_b32 s43, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s25, 16
|
|
; SI-NEXT: s_and_b32 s45, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s24, 16
|
|
; SI-NEXT: s_and_b32 s47, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s46, s23, 16
|
|
; SI-NEXT: s_and_b32 s57, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s56, s22, 16
|
|
; SI-NEXT: s_and_b32 s59, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s58, s21, 16
|
|
; SI-NEXT: s_and_b32 s61, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s60, s20, 16
|
|
; SI-NEXT: s_and_b32 s63, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s62, s19, 16
|
|
; SI-NEXT: s_and_b32 s73, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s72, s18, 16
|
|
; SI-NEXT: s_and_b32 s75, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s74, s17, 16
|
|
; SI-NEXT: s_and_b32 s77, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s76, s16, 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB21_3
|
|
; SI-NEXT: .LBB21_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s79, s79, 3
|
|
; SI-NEXT: s_add_i32 s78, s78, 3
|
|
; SI-NEXT: s_and_b32 s7, s78, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s6, s78, 16
|
|
; SI-NEXT: s_and_b32 s9, s79, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s8, s79, 16
|
|
; SI-NEXT: s_and_b32 s11, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s10, s29, 16
|
|
; SI-NEXT: s_and_b32 s13, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s12, s28, 16
|
|
; SI-NEXT: s_and_b32 s15, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s14, s27, 16
|
|
; SI-NEXT: s_and_b32 s41, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s40, s26, 16
|
|
; SI-NEXT: s_and_b32 s43, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s25, 16
|
|
; SI-NEXT: s_and_b32 s45, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s24, 16
|
|
; SI-NEXT: s_and_b32 s47, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s46, s23, 16
|
|
; SI-NEXT: s_and_b32 s57, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s56, s22, 16
|
|
; SI-NEXT: s_and_b32 s59, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s58, s21, 16
|
|
; SI-NEXT: s_and_b32 s61, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s60, s20, 16
|
|
; SI-NEXT: s_and_b32 s63, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s62, s19, 16
|
|
; SI-NEXT: s_and_b32 s73, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s72, s18, 16
|
|
; SI-NEXT: s_and_b32 s75, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s74, s17, 16
|
|
; SI-NEXT: s_and_b32 s77, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s76, s16, 16
|
|
; SI-NEXT: .LBB21_3: ; %end
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s77
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s76
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s73
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s72
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s63
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s62
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s61
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s60
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s59
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s58
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s56
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s47
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s46
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s45
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s44
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s43
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s42
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s40
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s14
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s12
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s10
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s8
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s6
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB21_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr43
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr41
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr15
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr13
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr11
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr9
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr7
|
|
; SI-NEXT: s_branch .LBB21_2
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v32bf16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB21_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB21_3
|
|
; VI-NEXT: .LBB21_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_add_i32 s7, s7, 3
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: s_add_i32 s23, s23, 3
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: s_add_i32 s21, s21, 3
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: s_add_i32 s19, s19, 3
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: s_add_i32 s17, s17, 3
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: .LBB21_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB21_4:
|
|
; VI-NEXT: s_branch .LBB21_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v32bf16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB21_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB21_3
|
|
; GFX9-NEXT: .LBB21_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX9-NEXT: s_add_i32 s29, s29, 3
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: .LBB21_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB21_4:
|
|
; GFX9-NEXT: s_branch .LBB21_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v32bf16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB21_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB21_3
|
|
; GFX11-NEXT: .LBB21_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX11-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX11-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX11-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX11-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX11-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX11-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-NEXT: s_add_i32 s3, s3, 3
|
|
; GFX11-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-NEXT: s_add_i32 s1, s1, 3
|
|
; GFX11-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-NEXT: .LBB21_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB21_4:
|
|
; GFX11-NEXT: s_branch .LBB21_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define <16 x i32> @bitcast_v32bf16_to_v16i32(<32 x bfloat> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v16i32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_mul_f32_e32 v54, 1.0, v32
|
|
; SI-NEXT: v_mul_f32_e32 v55, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v52, 1.0, v31
|
|
; SI-NEXT: v_mul_f32_e32 v53, 1.0, v1
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v51, 1.0, v2
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v49, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v39, 1.0, v4
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
|
|
; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v35, 1.0, v6
|
|
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v8
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v23
|
|
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v10
|
|
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v23, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v19
|
|
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
|
|
; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB22_3
|
|
; SI-NEXT: ; %bb.1: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB22_4
|
|
; SI-NEXT: .LBB22_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB22_3: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v38
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v55, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v53, 16
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v51, 16
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v49, 16
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v39, 16
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v37, 16
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v35, 16
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v17, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB22_2
|
|
; SI-NEXT: .LBB22_4: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v50
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
|
|
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v38
|
|
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v36
|
|
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v34
|
|
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
|
|
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
|
|
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
|
|
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
|
|
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
|
|
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
|
|
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
|
|
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
|
|
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v16i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB22_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
|
|
; VI-NEXT: s_movk_i32 s6, 0x7fff
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v14
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v14
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_alignbit_b32 v14, v14, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_alignbit_b32 v13, v13, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v12
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v12, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v12
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v12
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_alignbit_b32 v12, v12, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_alignbit_b32 v11, v11, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v10
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v10, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v10
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v10
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_alignbit_b32 v10, v10, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v9
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_alignbit_b32 v9, v9, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v8
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v8
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_alignbit_b32 v8, v8, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v7
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_alignbit_b32 v7, v7, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v6
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v6
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v6
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_alignbit_b32 v6, v6, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v5
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_alignbit_b32 v5, v5, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v4, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v4
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_alignbit_b32 v4, v4, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v3
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_alignbit_b32 v3, v3, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v2
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_alignbit_b32 v2, v2, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v1
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_alignbit_b32 v1, v1, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
|
|
; VI-NEXT: .LBB22_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v16i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB22_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v15, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v15, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v15
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
|
|
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v14, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v14, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v13, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v12, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v12, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v12
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v11, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v10, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v10, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v10
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v10, v10, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v9, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v9
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v8, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v8, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v8
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v7, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v7
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v6, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v6
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v6, v6, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v5, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v4, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v4, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v4, v4, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v3, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v3, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v2, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v1, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v0, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v0, v0, v16, s7
|
|
; GFX9-NEXT: .LBB22_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v16i32:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v30, v14
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
|
|
; GFX11-TRUE16-NEXT: .LBB22_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB22_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v4, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.h
|
|
; GFX11-TRUE16-NEXT: .LBB22_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v16i32:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB22_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v23, v14, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v16, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v22, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v2, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v2, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v1, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v21, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
|
|
; GFX11-FAKE16-NEXT: .LBB22_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define inreg <16 x i32> @bitcast_v32bf16_to_v16i32_scalar(<32 x bfloat> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v16i32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v0
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s5, s29, 16
|
|
; SI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s28, 16
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s9, s27, 16
|
|
; SI-NEXT: s_and_b32 s10, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s26, 16
|
|
; SI-NEXT: s_and_b32 s12, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s25, 16
|
|
; SI-NEXT: s_and_b32 s14, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s24, 16
|
|
; SI-NEXT: s_and_b32 s24, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_and_b32 s25, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: s_and_b32 s26, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s27, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s28, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: s_and_b32 s29, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s40, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s41, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s43, s42, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s42, 16
|
|
; SI-NEXT: s_and_b32 s45, s44, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s46, 0
|
|
; SI-NEXT: v_mul_f32_e64 v41, 1.0, s41
|
|
; SI-NEXT: v_mul_f32_e64 v52, 1.0, s16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v63, 1.0, s40
|
|
; SI-NEXT: v_mul_f32_e64 v48, 1.0, s17
|
|
; SI-NEXT: v_mul_f32_e64 v62, 1.0, s29
|
|
; SI-NEXT: v_mul_f32_e64 v61, 1.0, s28
|
|
; SI-NEXT: v_mul_f32_e64 v60, 1.0, s27
|
|
; SI-NEXT: v_mul_f32_e64 v59, 1.0, s26
|
|
; SI-NEXT: v_mul_f32_e64 v58, 1.0, s25
|
|
; SI-NEXT: v_mul_f32_e64 v57, 1.0, s24
|
|
; SI-NEXT: v_mul_f32_e64 v56, 1.0, s14
|
|
; SI-NEXT: v_mul_f32_e64 v47, 1.0, s12
|
|
; SI-NEXT: v_mul_f32_e64 v46, 1.0, s10
|
|
; SI-NEXT: v_mul_f32_e64 v45, 1.0, s8
|
|
; SI-NEXT: v_mul_f32_e64 v44, 1.0, s6
|
|
; SI-NEXT: v_mul_f32_e64 v43, 1.0, s4
|
|
; SI-NEXT: v_mul_f32_e64 v42, 1.0, s45
|
|
; SI-NEXT: v_mul_f32_e64 v16, 1.0, s43
|
|
; SI-NEXT: v_mul_f32_e64 v39, 1.0, s18
|
|
; SI-NEXT: v_mul_f32_e64 v54, 1.0, s19
|
|
; SI-NEXT: v_mul_f32_e64 v50, 1.0, s20
|
|
; SI-NEXT: v_mul_f32_e64 v37, 1.0, s21
|
|
; SI-NEXT: v_mul_f32_e64 v35, 1.0, s22
|
|
; SI-NEXT: v_mul_f32_e64 v33, 1.0, s23
|
|
; SI-NEXT: v_mul_f32_e64 v31, 1.0, s15
|
|
; SI-NEXT: v_mul_f32_e64 v29, 1.0, s13
|
|
; SI-NEXT: v_mul_f32_e64 v27, 1.0, s11
|
|
; SI-NEXT: v_mul_f32_e64 v25, 1.0, s9
|
|
; SI-NEXT: v_mul_f32_e64 v23, 1.0, s7
|
|
; SI-NEXT: v_mul_f32_e64 v21, 1.0, s5
|
|
; SI-NEXT: v_mul_f32_e64 v19, 1.0, s44
|
|
; SI-NEXT: v_mul_f32_e64 v17, 1.0, s42
|
|
; SI-NEXT: s_cbranch_scc0 .LBB23_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v63
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[52:53], 16
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v62
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[39:40], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v61
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[54:55], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v60
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[50:51], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v59
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[37:38], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v58
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[35:36], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v57
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[33:34], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v56
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[31:32], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v47
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[29:30], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v46
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[27:28], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v45
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[25:26], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v44
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[23:24], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v43
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[21:22], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v42
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[19:20], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v16
|
|
; SI-NEXT: v_mov_b32_e32 v20, v16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[17:18], 16
|
|
; SI-NEXT: v_mov_b32_e32 v16, v20
|
|
; SI-NEXT: s_cbranch_execnz .LBB23_3
|
|
; SI-NEXT: .LBB23_2: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v52
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v63
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v48
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v62
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v61
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v54
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v60
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v50
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v59
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v58
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v57
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v56
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v47
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v46
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v45
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v44
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v43
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v42
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
|
|
; SI-NEXT: .LBB23_3: ; %end
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB23_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_branch .LBB23_2
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v16i32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v20, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v20, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB23_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB23_4
|
|
; VI-NEXT: .LBB23_2: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
|
|
; VI-NEXT: s_lshl_b32 s4, s30, 16
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
|
|
; VI-NEXT: v_add_f32_e32 v1, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s28, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; VI-NEXT: v_add_f32_e32 v2, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[0:1]
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: s_and_b32 s5, s26, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s26, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s24, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s24, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s22, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s20, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s20, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s18, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s18, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s16, 16
|
|
; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s17, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s19, 16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v1, v5, s[4:5]
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
|
|
; VI-NEXT: s_lshl_b32 s6, s21, 16
|
|
; VI-NEXT: v_mov_b32_e32 v1, v17
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v5, v7, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v16
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v5, v5
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
|
|
; VI-NEXT: v_bfe_u32 v11, v5, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v5
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: s_lshl_b32 s6, s23, 16
|
|
; VI-NEXT: v_mov_b32_e32 v3, v17
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v7, v9, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v11, v13, vcc
|
|
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v7, v7
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
|
|
; VI-NEXT: s_lshl_b32 s6, s25, 16
|
|
; VI-NEXT: v_mov_b32_e32 v5, v17
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v9, v11, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v16
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v9, v9
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
|
|
; VI-NEXT: v_bfe_u32 v15, v9, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v9
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v7, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v15, v17, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s27, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v11, v13, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v11, v11
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v16
|
|
; VI-NEXT: v_mov_b32_e32 v9, v17
|
|
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: s_and_b32 s7, s31, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v13, v15, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v13, s7, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: s_lshl_b32 s6, s31, 16
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v11, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: s_lshl_b32 s4, s29, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
|
|
; VI-NEXT: v_add_f32_e32 v15, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[17:18]
|
|
; VI-NEXT: v_mov_b32_e32 v13, v15
|
|
; VI-NEXT: v_mov_b32_e32 v15, v16
|
|
; VI-NEXT: s_branch .LBB23_5
|
|
; VI-NEXT: .LBB23_3:
|
|
; VI-NEXT: s_branch .LBB23_2
|
|
; VI-NEXT: .LBB23_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB23_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v20, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v20, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v16i32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB23_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB23_4
|
|
; GFX9-NEXT: .LBB23_2: ; %cmp.true
|
|
; GFX9-NEXT: s_and_b32 s4, s31, 0xffff0000
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s31, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v3, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: s_lshl_b32 s4, s30, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v4, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, 0xffff
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v1, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v3
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s29, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s28, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s27, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s26, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s25, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s24, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s23, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s22, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s21, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s20, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s19, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s18, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v17, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s17, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v17, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: s_lshl_b32 s4, s16, 16
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v0, s4, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v0, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v0
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_and_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v16
|
|
; GFX9-NEXT: s_branch .LBB23_5
|
|
; GFX9-NEXT: .LBB23_3:
|
|
; GFX9-NEXT: s_branch .LBB23_2
|
|
; GFX9-NEXT: .LBB23_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB23_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v20, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v16i32_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB23_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB23_4
|
|
; GFX11-TRUE16-NEXT: .LBB23_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s27, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s26, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v7, v7, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v2, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v17 :: v_dual_add_nc_u32 v3, v3, v4
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s15, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s12, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v17, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v16, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v18, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v16, v20, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v18
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v16, v19, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s12, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v19 :: v_dual_add_nc_u32 v19, v21, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, v22, v17
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v20, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v21, v22, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v23, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v24, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v17.l
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB23_3:
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB23_2
|
|
; GFX11-TRUE16-NEXT: .LBB23_4:
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v16i32_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB23_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB23_4
|
|
; GFX11-FAKE16-NEXT: .LBB23_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s26, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s25, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_nc_u32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v8, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v6, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s17, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v6, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v7, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v17, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v19, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v18, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v6, v16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s15, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v17, v18 :: v_dual_add_nc_u32 v17, v19, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s12, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v24
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v21, v24, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v18, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v16, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v20, 16, v17
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB23_3:
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB23_2
|
|
; GFX11-FAKE16-NEXT: .LBB23_4:
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v64i8:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; kill: killed $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB24_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v17, v16, v15, 24
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v15, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v16, v15, 8
|
|
; SI-NEXT: v_alignbit_b32 v20, v14, v13, 24
|
|
; SI-NEXT: v_alignbit_b32 v21, v14, v13, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v14, v13, 8
|
|
; SI-NEXT: v_alignbit_b32 v23, v12, v11, 24
|
|
; SI-NEXT: v_alignbit_b32 v24, v12, v11, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v12, v11, 8
|
|
; SI-NEXT: v_alignbit_b32 v29, v10, v9, 24
|
|
; SI-NEXT: v_alignbit_b32 v30, v10, v9, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v10, v9, 8
|
|
; SI-NEXT: v_alignbit_b32 v35, v8, v7, 24
|
|
; SI-NEXT: v_alignbit_b32 v36, v8, v7, 16
|
|
; SI-NEXT: v_alignbit_b32 v37, v8, v7, 8
|
|
; SI-NEXT: v_alignbit_b32 v49, v6, v5, 24
|
|
; SI-NEXT: v_alignbit_b32 v50, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v52, v6, v5, 8
|
|
; SI-NEXT: v_alignbit_b32 v55, v4, v3, 24
|
|
; SI-NEXT: v_alignbit_b32 v41, v4, v3, 16
|
|
; SI-NEXT: v_alignbit_b32 v43, v4, v3, 8
|
|
; SI-NEXT: v_alignbit_b32 v46, v2, v1, 24
|
|
; SI-NEXT: v_alignbit_b32 v56, v2, v1, 16
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_alignbit_b32 v58, v2, v1, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v57, 8, v6
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v4
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v4
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v2
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
|
|
; SI-NEXT: .LBB24_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB24_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_alignbit_b32 v17, v16, v15, 24
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v15, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v16, v15, 8
|
|
; SI-NEXT: v_alignbit_b32 v20, v14, v13, 24
|
|
; SI-NEXT: v_alignbit_b32 v21, v14, v13, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v14, v13, 8
|
|
; SI-NEXT: v_alignbit_b32 v23, v12, v11, 24
|
|
; SI-NEXT: v_alignbit_b32 v24, v12, v11, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v12, v11, 8
|
|
; SI-NEXT: v_alignbit_b32 v29, v10, v9, 24
|
|
; SI-NEXT: v_alignbit_b32 v30, v10, v9, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v10, v9, 8
|
|
; SI-NEXT: v_alignbit_b32 v35, v8, v7, 24
|
|
; SI-NEXT: v_alignbit_b32 v36, v8, v7, 16
|
|
; SI-NEXT: v_alignbit_b32 v37, v8, v7, 8
|
|
; SI-NEXT: v_alignbit_b32 v49, v6, v5, 24
|
|
; SI-NEXT: v_alignbit_b32 v50, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v52, v6, v5, 8
|
|
; SI-NEXT: v_alignbit_b32 v55, v4, v3, 24
|
|
; SI-NEXT: v_alignbit_b32 v41, v4, v3, 16
|
|
; SI-NEXT: v_alignbit_b32 v43, v4, v3, 8
|
|
; SI-NEXT: v_alignbit_b32 v46, v2, v1, 24
|
|
; SI-NEXT: v_alignbit_b32 v56, v2, v1, 16
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_alignbit_b32 v58, v2, v1, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v57, 8, v6
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v4
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v4
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v2
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
|
|
; SI-NEXT: .LBB24_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v58
|
|
; SI-NEXT: v_and_b32_e32 v56, 0xff, v56
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v56
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v46
|
|
; SI-NEXT: v_or_b32_e32 v46, v46, v56
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v46
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v17
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v63
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v62
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v17, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v41
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v55
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v61
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v60
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v59
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v52
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v49
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v57
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v47
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v45
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v37
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v44
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v40
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v31
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v29
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v54
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v53
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v51
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v25
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v48
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v38
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v22
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v20
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v32
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v19
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v28
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v26
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v64i8:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB24_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: v_mov_b32_e32 v27, v21
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: .LBB24_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB24_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 3, v16
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: .LBB24_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v21
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; VI-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
|
|
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
|
|
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
|
|
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v64i8:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB24_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v16
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, v22
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: .LBB24_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB24_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 3, v11
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 3, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 3, v9
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 3, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 3, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 3, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 3, v6
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 3, v5
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: .LBB24_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v22, v30, v24, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v22, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v21, v62, v21, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v61, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v21, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v43, v23, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v54, v20, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v27, v25, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v16i32_to_v64i8:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB24_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB24_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB24_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 3, v9
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 3, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 3, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 3, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB24_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
|
|
; GFX11-TRUE16-NEXT: s_clause 0x3
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v16i32_to_v64i8:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB24_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB24_2: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB24_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 3, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 3, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 3, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 3, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 3, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 3, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 3, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB24_4: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
|
|
; GFX11-FAKE16-NEXT: s_clause 0x3
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16i32_to_v64i8_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v4, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v4, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v4, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v4, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v4, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v4, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v4, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v4, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v4, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v4, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v4, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v4, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v4, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v4, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v4, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v4, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v4, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v4, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v4, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v4, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v4, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v4, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v4, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v4, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v4, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v4, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v4, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v4, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v4, s30, 28
|
|
; SI-NEXT: v_writelane_b32 v4, s31, 29
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; SI-NEXT: s_cbranch_scc0 .LBB25_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s38, s5, 24
|
|
; SI-NEXT: s_lshr_b32 s39, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s48, s5, 8
|
|
; SI-NEXT: s_lshr_b32 s49, s29, 24
|
|
; SI-NEXT: s_lshr_b32 s50, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s51, s29, 8
|
|
; SI-NEXT: s_lshr_b32 s52, s27, 24
|
|
; SI-NEXT: s_lshr_b32 s53, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s54, s27, 8
|
|
; SI-NEXT: s_lshr_b32 s55, s25, 24
|
|
; SI-NEXT: s_lshr_b32 s64, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s65, s25, 8
|
|
; SI-NEXT: s_lshr_b32 s66, s23, 24
|
|
; SI-NEXT: s_lshr_b32 s67, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s68, s23, 8
|
|
; SI-NEXT: s_lshr_b32 s69, s21, 24
|
|
; SI-NEXT: s_lshr_b32 s70, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s71, s21, 8
|
|
; SI-NEXT: s_lshr_b32 s80, s19, 24
|
|
; SI-NEXT: s_lshr_b32 s81, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s82, s19, 8
|
|
; SI-NEXT: s_lshr_b32 s83, s17, 24
|
|
; SI-NEXT: s_lshr_b32 s84, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s85, s17, 8
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 8
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[28:29], 24
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[28:29], 8
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[24:25], 24
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 8
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 24
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[22:23], 8
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 8
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[18:19], 24
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 8
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 8
|
|
; SI-NEXT: s_cbranch_execnz .LBB25_3
|
|
; SI-NEXT: .LBB25_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s5, s5, 3
|
|
; SI-NEXT: s_add_i32 s4, s4, 3
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 8
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[28:29], 24
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[28:29], 8
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[24:25], 24
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 8
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[22:23], 24
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b32 s38, s5, 24
|
|
; SI-NEXT: s_lshr_b32 s39, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s48, s5, 8
|
|
; SI-NEXT: s_lshr_b32 s49, s29, 24
|
|
; SI-NEXT: s_lshr_b32 s50, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s51, s29, 8
|
|
; SI-NEXT: s_lshr_b32 s52, s27, 24
|
|
; SI-NEXT: s_lshr_b32 s53, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s54, s27, 8
|
|
; SI-NEXT: s_lshr_b32 s55, s25, 24
|
|
; SI-NEXT: s_lshr_b32 s64, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s65, s25, 8
|
|
; SI-NEXT: s_lshr_b32 s66, s23, 24
|
|
; SI-NEXT: s_lshr_b32 s67, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s68, s23, 8
|
|
; SI-NEXT: s_lshr_b32 s69, s21, 24
|
|
; SI-NEXT: s_lshr_b32 s70, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s71, s21, 8
|
|
; SI-NEXT: s_lshr_b32 s80, s19, 24
|
|
; SI-NEXT: s_lshr_b32 s81, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s82, s19, 8
|
|
; SI-NEXT: s_lshr_b32 s83, s17, 24
|
|
; SI-NEXT: s_lshr_b32 s84, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s85, s17, 8
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[22:23], 8
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[20:21], 8
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[18:19], 24
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 8
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 8
|
|
; SI-NEXT: .LBB25_3: ; %end
|
|
; SI-NEXT: s_lshl_b32 s7, s36, 8
|
|
; SI-NEXT: s_and_b32 s9, s16, 0xff
|
|
; SI-NEXT: s_or_b32 s7, s9, s7
|
|
; SI-NEXT: s_and_b32 s9, s34, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s30, 24
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_mov_b32_e32 v1, s7
|
|
; SI-NEXT: s_and_b32 s7, s17, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s85, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s84, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s83, 24
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_lshl_b32 s7, s94, 8
|
|
; SI-NEXT: s_and_b32 s9, s18, 0xff
|
|
; SI-NEXT: s_or_b32 s7, s9, s7
|
|
; SI-NEXT: s_and_b32 s9, s92, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s90, 24
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_mov_b32_e32 v3, s7
|
|
; SI-NEXT: s_and_b32 s7, s19, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s82, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s81, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s80, 24
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s78, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s76, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s74, 24
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s21, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s71, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s70, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s69, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s22, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s88, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s62, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s23, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s68, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s67, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s66, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s60, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s56, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s25, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s65, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s64, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s55, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s46, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s44, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s42, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s27, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s54, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s53, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s52, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s40, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s12, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s29, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s51, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s50, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s49, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s10, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s7
|
|
; SI-NEXT: s_and_b32 s7, s8, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s4
|
|
; SI-NEXT: s_and_b32 s4, s5, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s48, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s39, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s38, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: v_mov_b32_e32 v1, s4
|
|
; SI-NEXT: v_readlane_b32 s30, v4, 28
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: v_readlane_b32 s31, v4, 29
|
|
; SI-NEXT: v_readlane_b32 s85, v4, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v4, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v4, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v4, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v4, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v4, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v4, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v4, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v4, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v4, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v4, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v4, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v4, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v4, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v4, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v4, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v4, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v4, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v4, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v4, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v4, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v4, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v4, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v4, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v4, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v4, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v4, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v4, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB25_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr36
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: ; implicit-def: $sgpr85
|
|
; SI-NEXT: ; implicit-def: $sgpr84
|
|
; SI-NEXT: ; implicit-def: $sgpr83
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr90
|
|
; SI-NEXT: ; implicit-def: $sgpr82
|
|
; SI-NEXT: ; implicit-def: $sgpr81
|
|
; SI-NEXT: ; implicit-def: $sgpr80
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr71
|
|
; SI-NEXT: ; implicit-def: $sgpr70
|
|
; SI-NEXT: ; implicit-def: $sgpr69
|
|
; SI-NEXT: ; implicit-def: $sgpr68
|
|
; SI-NEXT: ; implicit-def: $sgpr67
|
|
; SI-NEXT: ; implicit-def: $sgpr66
|
|
; SI-NEXT: ; implicit-def: $sgpr65
|
|
; SI-NEXT: ; implicit-def: $sgpr64
|
|
; SI-NEXT: ; implicit-def: $sgpr55
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr53
|
|
; SI-NEXT: ; implicit-def: $sgpr52
|
|
; SI-NEXT: ; implicit-def: $sgpr51
|
|
; SI-NEXT: ; implicit-def: $sgpr50
|
|
; SI-NEXT: ; implicit-def: $sgpr49
|
|
; SI-NEXT: ; implicit-def: $sgpr48
|
|
; SI-NEXT: ; implicit-def: $sgpr39
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: s_branch .LBB25_2
|
|
;
|
|
; VI-LABEL: bitcast_v16i32_to_v64i8_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v4, s34, 0
|
|
; VI-NEXT: v_writelane_b32 v4, s35, 1
|
|
; VI-NEXT: v_writelane_b32 v4, s36, 2
|
|
; VI-NEXT: v_writelane_b32 v4, s37, 3
|
|
; VI-NEXT: v_writelane_b32 v4, s38, 4
|
|
; VI-NEXT: v_writelane_b32 v4, s39, 5
|
|
; VI-NEXT: v_writelane_b32 v4, s48, 6
|
|
; VI-NEXT: v_writelane_b32 v4, s49, 7
|
|
; VI-NEXT: v_writelane_b32 v4, s50, 8
|
|
; VI-NEXT: v_writelane_b32 v4, s51, 9
|
|
; VI-NEXT: v_writelane_b32 v4, s52, 10
|
|
; VI-NEXT: v_writelane_b32 v4, s53, 11
|
|
; VI-NEXT: v_writelane_b32 v4, s54, 12
|
|
; VI-NEXT: v_writelane_b32 v4, s55, 13
|
|
; VI-NEXT: v_writelane_b32 v4, s64, 14
|
|
; VI-NEXT: v_writelane_b32 v4, s65, 15
|
|
; VI-NEXT: v_writelane_b32 v4, s66, 16
|
|
; VI-NEXT: v_writelane_b32 v4, s67, 17
|
|
; VI-NEXT: v_writelane_b32 v4, s30, 18
|
|
; VI-NEXT: v_writelane_b32 v4, s31, 19
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; VI-NEXT: s_cbranch_scc0 .LBB25_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_lshr_b32 s56, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s58, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s60, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s61, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s63, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s72, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s74, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s75, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s76, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s77, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s78, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s79, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s89, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s90, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s91, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s31, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s34, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s35, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s36, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s39, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s48, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s49, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s50, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s51, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s52, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s53, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s54, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s65, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s66, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 8
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; VI-NEXT: s_cbranch_execnz .LBB25_3
|
|
; VI-NEXT: .LBB25_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s17, s17, 3
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: s_add_i32 s19, s19, 3
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: s_add_i32 s21, s21, 3
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: s_add_i32 s23, s23, 3
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_add_i32 s5, s5, 3
|
|
; VI-NEXT: s_add_i32 s4, s4, 3
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; VI-NEXT: s_lshr_b32 s56, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s58, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s60, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s61, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s63, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s72, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s74, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s75, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s76, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s77, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s78, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s79, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s89, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s90, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s91, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s31, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s34, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s35, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s36, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s39, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s48, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s49, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s50, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s51, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s52, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s53, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s54, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s65, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s66, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 8
|
|
; VI-NEXT: .LBB25_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v3, s44
|
|
; VI-NEXT: v_mov_b32_e32 v1, s67
|
|
; VI-NEXT: v_perm_b32 v3, s66, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s55
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v1, s65
|
|
; VI-NEXT: v_perm_b32 v3, s64, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s42
|
|
; VI-NEXT: v_mov_b32_e32 v1, s54
|
|
; VI-NEXT: v_perm_b32 v3, s53, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s50
|
|
; VI-NEXT: v_mov_b32_e32 v1, s52
|
|
; VI-NEXT: v_perm_b32 v3, s51, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s40
|
|
; VI-NEXT: v_mov_b32_e32 v1, s49
|
|
; VI-NEXT: v_perm_b32 v3, s48, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s37
|
|
; VI-NEXT: v_mov_b32_e32 v1, s39
|
|
; VI-NEXT: v_perm_b32 v3, s38, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s14
|
|
; VI-NEXT: v_mov_b32_e32 v1, s36
|
|
; VI-NEXT: v_perm_b32 v3, s35, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s30
|
|
; VI-NEXT: v_mov_b32_e32 v1, s34
|
|
; VI-NEXT: v_perm_b32 v3, s31, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s12
|
|
; VI-NEXT: v_mov_b32_e32 v1, s91
|
|
; VI-NEXT: v_perm_b32 v3, s90, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s79
|
|
; VI-NEXT: v_mov_b32_e32 v1, s89
|
|
; VI-NEXT: v_perm_b32 v3, s88, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s10
|
|
; VI-NEXT: v_mov_b32_e32 v1, s78
|
|
; VI-NEXT: v_perm_b32 v3, s77, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s26, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s74
|
|
; VI-NEXT: v_mov_b32_e32 v1, s76
|
|
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s27, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s8
|
|
; VI-NEXT: v_mov_b32_e32 v1, s73
|
|
; VI-NEXT: v_perm_b32 v3, s72, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s28, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s61
|
|
; VI-NEXT: v_mov_b32_e32 v1, s63
|
|
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s29, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s6
|
|
; VI-NEXT: v_mov_b32_e32 v1, s60
|
|
; VI-NEXT: v_perm_b32 v3, s59, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s4, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v1, s58
|
|
; VI-NEXT: v_mov_b32_e32 v3, s56
|
|
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
|
|
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: v_readlane_b32 s30, v4, 18
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_readlane_b32 s31, v4, 19
|
|
; VI-NEXT: v_readlane_b32 s67, v4, 17
|
|
; VI-NEXT: v_readlane_b32 s66, v4, 16
|
|
; VI-NEXT: v_readlane_b32 s65, v4, 15
|
|
; VI-NEXT: v_readlane_b32 s64, v4, 14
|
|
; VI-NEXT: v_readlane_b32 s55, v4, 13
|
|
; VI-NEXT: v_readlane_b32 s54, v4, 12
|
|
; VI-NEXT: v_readlane_b32 s53, v4, 11
|
|
; VI-NEXT: v_readlane_b32 s52, v4, 10
|
|
; VI-NEXT: v_readlane_b32 s51, v4, 9
|
|
; VI-NEXT: v_readlane_b32 s50, v4, 8
|
|
; VI-NEXT: v_readlane_b32 s49, v4, 7
|
|
; VI-NEXT: v_readlane_b32 s48, v4, 6
|
|
; VI-NEXT: v_readlane_b32 s39, v4, 5
|
|
; VI-NEXT: v_readlane_b32 s38, v4, 4
|
|
; VI-NEXT: v_readlane_b32 s37, v4, 3
|
|
; VI-NEXT: v_readlane_b32 s36, v4, 2
|
|
; VI-NEXT: v_readlane_b32 s35, v4, 1
|
|
; VI-NEXT: v_readlane_b32 s34, v4, 0
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB25_4:
|
|
; VI-NEXT: ; implicit-def: $sgpr67
|
|
; VI-NEXT: ; implicit-def: $sgpr66
|
|
; VI-NEXT: ; implicit-def: $sgpr44
|
|
; VI-NEXT: ; implicit-def: $sgpr65
|
|
; VI-NEXT: ; implicit-def: $sgpr64
|
|
; VI-NEXT: ; implicit-def: $sgpr55
|
|
; VI-NEXT: ; implicit-def: $sgpr54
|
|
; VI-NEXT: ; implicit-def: $sgpr53
|
|
; VI-NEXT: ; implicit-def: $sgpr42
|
|
; VI-NEXT: ; implicit-def: $sgpr52
|
|
; VI-NEXT: ; implicit-def: $sgpr51
|
|
; VI-NEXT: ; implicit-def: $sgpr50
|
|
; VI-NEXT: ; implicit-def: $sgpr49
|
|
; VI-NEXT: ; implicit-def: $sgpr48
|
|
; VI-NEXT: ; implicit-def: $sgpr40
|
|
; VI-NEXT: ; implicit-def: $sgpr39
|
|
; VI-NEXT: ; implicit-def: $sgpr38
|
|
; VI-NEXT: ; implicit-def: $sgpr37
|
|
; VI-NEXT: ; implicit-def: $sgpr36
|
|
; VI-NEXT: ; implicit-def: $sgpr35
|
|
; VI-NEXT: ; implicit-def: $sgpr14
|
|
; VI-NEXT: ; implicit-def: $sgpr34
|
|
; VI-NEXT: ; implicit-def: $sgpr31
|
|
; VI-NEXT: ; implicit-def: $sgpr30
|
|
; VI-NEXT: ; implicit-def: $sgpr91
|
|
; VI-NEXT: ; implicit-def: $sgpr90
|
|
; VI-NEXT: ; implicit-def: $sgpr12
|
|
; VI-NEXT: ; implicit-def: $sgpr89
|
|
; VI-NEXT: ; implicit-def: $sgpr88
|
|
; VI-NEXT: ; implicit-def: $sgpr79
|
|
; VI-NEXT: ; implicit-def: $sgpr78
|
|
; VI-NEXT: ; implicit-def: $sgpr77
|
|
; VI-NEXT: ; implicit-def: $sgpr10
|
|
; VI-NEXT: ; implicit-def: $sgpr76
|
|
; VI-NEXT: ; implicit-def: $sgpr75
|
|
; VI-NEXT: ; implicit-def: $sgpr74
|
|
; VI-NEXT: ; implicit-def: $sgpr73
|
|
; VI-NEXT: ; implicit-def: $sgpr72
|
|
; VI-NEXT: ; implicit-def: $sgpr8
|
|
; VI-NEXT: ; implicit-def: $sgpr63
|
|
; VI-NEXT: ; implicit-def: $sgpr62
|
|
; VI-NEXT: ; implicit-def: $sgpr61
|
|
; VI-NEXT: ; implicit-def: $sgpr60
|
|
; VI-NEXT: ; implicit-def: $sgpr59
|
|
; VI-NEXT: ; implicit-def: $sgpr6
|
|
; VI-NEXT: ; implicit-def: $sgpr58
|
|
; VI-NEXT: ; implicit-def: $sgpr57
|
|
; VI-NEXT: ; implicit-def: $sgpr56
|
|
; VI-NEXT: s_branch .LBB25_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v16i32_to_v64i8_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v4, s34, 0
|
|
; GFX9-NEXT: v_writelane_b32 v4, s35, 1
|
|
; GFX9-NEXT: v_writelane_b32 v4, s36, 2
|
|
; GFX9-NEXT: v_writelane_b32 v4, s37, 3
|
|
; GFX9-NEXT: v_writelane_b32 v4, s38, 4
|
|
; GFX9-NEXT: v_writelane_b32 v4, s39, 5
|
|
; GFX9-NEXT: v_writelane_b32 v4, s48, 6
|
|
; GFX9-NEXT: v_writelane_b32 v4, s49, 7
|
|
; GFX9-NEXT: v_writelane_b32 v4, s50, 8
|
|
; GFX9-NEXT: v_writelane_b32 v4, s51, 9
|
|
; GFX9-NEXT: v_writelane_b32 v4, s52, 10
|
|
; GFX9-NEXT: v_writelane_b32 v4, s53, 11
|
|
; GFX9-NEXT: v_writelane_b32 v4, s54, 12
|
|
; GFX9-NEXT: v_writelane_b32 v4, s55, 13
|
|
; GFX9-NEXT: v_writelane_b32 v4, s30, 14
|
|
; GFX9-NEXT: v_writelane_b32 v4, s31, 15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB25_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s57, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s58, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s59, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s60, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s61, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s62, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s63, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s72, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s74, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s75, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s76, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s77, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s78, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s79, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s88, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s89, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s90, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s91, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s92, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s93, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s94, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s95, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s30, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s35, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s36, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s37, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s38, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s39, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s48, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s49, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s50, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s52, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s53, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB25_3
|
|
; GFX9-NEXT: .LBB25_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: s_add_i32 s29, s29, 3
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: s_add_i32 s5, s5, 3
|
|
; GFX9-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s57, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s58, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s59, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s60, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s61, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s62, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s63, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s72, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s74, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s75, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s76, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s77, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s78, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s79, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s88, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s89, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s90, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s91, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s92, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s93, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s94, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s95, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s30, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s35, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s36, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s37, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s38, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s39, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s48, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s49, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s50, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s52, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s53, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
|
|
; GFX9-NEXT: .LBB25_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s44
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s55
|
|
; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s51
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s53
|
|
; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s42
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s50
|
|
; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s38
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s48
|
|
; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s40
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s37
|
|
; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s31
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s35
|
|
; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s14
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s30
|
|
; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s92
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s94
|
|
; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s12
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s91
|
|
; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s79
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s89
|
|
; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s10
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s78
|
|
; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s74
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s76
|
|
; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s8
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s73
|
|
; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s61
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s63
|
|
; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s6
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s60
|
|
; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s58
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s56
|
|
; GFX9-NEXT: v_perm_b32 v1, s5, v1, v2
|
|
; GFX9-NEXT: v_perm_b32 v2, s57, v3, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: v_readlane_b32 s30, v4, 14
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: v_readlane_b32 s31, v4, 15
|
|
; GFX9-NEXT: v_readlane_b32 s55, v4, 13
|
|
; GFX9-NEXT: v_readlane_b32 s54, v4, 12
|
|
; GFX9-NEXT: v_readlane_b32 s53, v4, 11
|
|
; GFX9-NEXT: v_readlane_b32 s52, v4, 10
|
|
; GFX9-NEXT: v_readlane_b32 s51, v4, 9
|
|
; GFX9-NEXT: v_readlane_b32 s50, v4, 8
|
|
; GFX9-NEXT: v_readlane_b32 s49, v4, 7
|
|
; GFX9-NEXT: v_readlane_b32 s48, v4, 6
|
|
; GFX9-NEXT: v_readlane_b32 s39, v4, 5
|
|
; GFX9-NEXT: v_readlane_b32 s38, v4, 4
|
|
; GFX9-NEXT: v_readlane_b32 s37, v4, 3
|
|
; GFX9-NEXT: v_readlane_b32 s36, v4, 2
|
|
; GFX9-NEXT: v_readlane_b32 s35, v4, 1
|
|
; GFX9-NEXT: v_readlane_b32 s34, v4, 0
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB25_4:
|
|
; GFX9-NEXT: ; implicit-def: $sgpr55
|
|
; GFX9-NEXT: ; implicit-def: $sgpr54
|
|
; GFX9-NEXT: ; implicit-def: $sgpr44
|
|
; GFX9-NEXT: ; implicit-def: $sgpr53
|
|
; GFX9-NEXT: ; implicit-def: $sgpr52
|
|
; GFX9-NEXT: ; implicit-def: $sgpr51
|
|
; GFX9-NEXT: ; implicit-def: $sgpr50
|
|
; GFX9-NEXT: ; implicit-def: $sgpr49
|
|
; GFX9-NEXT: ; implicit-def: $sgpr42
|
|
; GFX9-NEXT: ; implicit-def: $sgpr48
|
|
; GFX9-NEXT: ; implicit-def: $sgpr39
|
|
; GFX9-NEXT: ; implicit-def: $sgpr38
|
|
; GFX9-NEXT: ; implicit-def: $sgpr37
|
|
; GFX9-NEXT: ; implicit-def: $sgpr36
|
|
; GFX9-NEXT: ; implicit-def: $sgpr40
|
|
; GFX9-NEXT: ; implicit-def: $sgpr35
|
|
; GFX9-NEXT: ; implicit-def: $sgpr34
|
|
; GFX9-NEXT: ; implicit-def: $sgpr31
|
|
; GFX9-NEXT: ; implicit-def: $sgpr30
|
|
; GFX9-NEXT: ; implicit-def: $sgpr95
|
|
; GFX9-NEXT: ; implicit-def: $sgpr14
|
|
; GFX9-NEXT: ; implicit-def: $sgpr94
|
|
; GFX9-NEXT: ; implicit-def: $sgpr93
|
|
; GFX9-NEXT: ; implicit-def: $sgpr92
|
|
; GFX9-NEXT: ; implicit-def: $sgpr91
|
|
; GFX9-NEXT: ; implicit-def: $sgpr90
|
|
; GFX9-NEXT: ; implicit-def: $sgpr12
|
|
; GFX9-NEXT: ; implicit-def: $sgpr89
|
|
; GFX9-NEXT: ; implicit-def: $sgpr88
|
|
; GFX9-NEXT: ; implicit-def: $sgpr79
|
|
; GFX9-NEXT: ; implicit-def: $sgpr78
|
|
; GFX9-NEXT: ; implicit-def: $sgpr77
|
|
; GFX9-NEXT: ; implicit-def: $sgpr10
|
|
; GFX9-NEXT: ; implicit-def: $sgpr76
|
|
; GFX9-NEXT: ; implicit-def: $sgpr75
|
|
; GFX9-NEXT: ; implicit-def: $sgpr74
|
|
; GFX9-NEXT: ; implicit-def: $sgpr73
|
|
; GFX9-NEXT: ; implicit-def: $sgpr72
|
|
; GFX9-NEXT: ; implicit-def: $sgpr8
|
|
; GFX9-NEXT: ; implicit-def: $sgpr63
|
|
; GFX9-NEXT: ; implicit-def: $sgpr62
|
|
; GFX9-NEXT: ; implicit-def: $sgpr61
|
|
; GFX9-NEXT: ; implicit-def: $sgpr60
|
|
; GFX9-NEXT: ; implicit-def: $sgpr59
|
|
; GFX9-NEXT: ; implicit-def: $sgpr6
|
|
; GFX9-NEXT: ; implicit-def: $sgpr58
|
|
; GFX9-NEXT: ; implicit-def: $sgpr57
|
|
; GFX9-NEXT: ; implicit-def: $sgpr56
|
|
; GFX9-NEXT: s_branch .LBB25_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v16i32_to_v64i8_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
|
|
; GFX11-NEXT: scratch_store_b32 off, v23, s32 ; 4-byte Folded Spill
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s4
|
|
; GFX11-NEXT: v_writelane_b32 v23, s34, 0
|
|
; GFX11-NEXT: v_writelane_b32 v23, s35, 1
|
|
; GFX11-NEXT: v_writelane_b32 v23, s36, 2
|
|
; GFX11-NEXT: v_writelane_b32 v23, s37, 3
|
|
; GFX11-NEXT: v_writelane_b32 v23, s38, 4
|
|
; GFX11-NEXT: v_writelane_b32 v23, s39, 5
|
|
; GFX11-NEXT: v_writelane_b32 v23, s48, 6
|
|
; GFX11-NEXT: v_writelane_b32 v23, s30, 7
|
|
; GFX11-NEXT: v_writelane_b32 v23, s31, 8
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 vcc_lo, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB25_4
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
|
|
; GFX11-NEXT: s_lshr_b32 s44, s27, 16
|
|
; GFX11-NEXT: s_lshr_b32 s43, s27, 8
|
|
; GFX11-NEXT: s_lshr_b32 s46, s26, 16
|
|
; GFX11-NEXT: s_lshr_b32 s45, s26, 8
|
|
; GFX11-NEXT: s_lshr_b32 s56, s25, 24
|
|
; GFX11-NEXT: s_lshr_b32 s57, s25, 16
|
|
; GFX11-NEXT: s_lshr_b32 s47, s25, 8
|
|
; GFX11-NEXT: s_lshr_b32 s59, s24, 16
|
|
; GFX11-NEXT: s_lshr_b32 s58, s24, 8
|
|
; GFX11-NEXT: s_lshr_b32 s61, s23, 24
|
|
; GFX11-NEXT: s_lshr_b32 s62, s23, 16
|
|
; GFX11-NEXT: s_lshr_b32 s60, s23, 8
|
|
; GFX11-NEXT: s_lshr_b32 s72, s22, 16
|
|
; GFX11-NEXT: s_lshr_b32 s63, s22, 8
|
|
; GFX11-NEXT: s_lshr_b32 s74, s21, 24
|
|
; GFX11-NEXT: s_lshr_b32 s75, s21, 16
|
|
; GFX11-NEXT: s_lshr_b32 s73, s21, 8
|
|
; GFX11-NEXT: s_lshr_b32 s77, s20, 16
|
|
; GFX11-NEXT: s_lshr_b32 s76, s20, 8
|
|
; GFX11-NEXT: s_lshr_b32 s78, s19, 24
|
|
; GFX11-NEXT: s_lshr_b32 s88, s19, 16
|
|
; GFX11-NEXT: s_lshr_b32 s79, s19, 8
|
|
; GFX11-NEXT: s_lshr_b32 s90, s18, 16
|
|
; GFX11-NEXT: s_lshr_b32 s89, s18, 8
|
|
; GFX11-NEXT: s_lshr_b32 s92, s17, 24
|
|
; GFX11-NEXT: s_lshr_b32 s93, s17, 16
|
|
; GFX11-NEXT: s_lshr_b32 s91, s17, 8
|
|
; GFX11-NEXT: s_lshr_b32 s95, s16, 16
|
|
; GFX11-NEXT: s_lshr_b32 s94, s16, 8
|
|
; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 24
|
|
; GFX11-NEXT: s_lshr_b32 s30, s3, 16
|
|
; GFX11-NEXT: s_lshr_b32 s31, s3, 8
|
|
; GFX11-NEXT: s_lshr_b32 s34, s2, 16
|
|
; GFX11-NEXT: s_lshr_b32 s35, s2, 8
|
|
; GFX11-NEXT: s_lshr_b32 s36, s1, 24
|
|
; GFX11-NEXT: s_lshr_b32 s37, s1, 16
|
|
; GFX11-NEXT: s_lshr_b32 s38, s1, 8
|
|
; GFX11-NEXT: s_lshr_b32 s39, s0, 16
|
|
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
|
|
; GFX11-NEXT: s_lshr_b64 s[4:5], s[26:27], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[6:7], s[24:25], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[8:9], s[22:23], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[12:13], s[18:19], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[14:15], s[16:17], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[28:29], s[2:3], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[40:41], s[0:1], 24
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB25_3
|
|
; GFX11-NEXT: .LBB25_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_i32 s1, s1, 3
|
|
; GFX11-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-NEXT: s_add_i32 s3, s3, 3
|
|
; GFX11-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-NEXT: s_add_i32 s17, s17, 3
|
|
; GFX11-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-NEXT: s_add_i32 s19, s19, 3
|
|
; GFX11-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-NEXT: s_add_i32 s21, s21, 3
|
|
; GFX11-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-NEXT: s_add_i32 s23, s23, 3
|
|
; GFX11-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-NEXT: s_add_i32 s25, s25, 3
|
|
; GFX11-NEXT: s_add_i32 s27, s27, 3
|
|
; GFX11-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-NEXT: s_lshr_b64 s[4:5], s[26:27], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[6:7], s[24:25], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[8:9], s[22:23], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[12:13], s[18:19], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[14:15], s[16:17], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[28:29], s[2:3], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[40:41], s[0:1], 24
|
|
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
|
|
; GFX11-NEXT: s_lshr_b32 s44, s27, 16
|
|
; GFX11-NEXT: s_lshr_b32 s43, s27, 8
|
|
; GFX11-NEXT: s_lshr_b32 s46, s26, 16
|
|
; GFX11-NEXT: s_lshr_b32 s45, s26, 8
|
|
; GFX11-NEXT: s_lshr_b32 s56, s25, 24
|
|
; GFX11-NEXT: s_lshr_b32 s57, s25, 16
|
|
; GFX11-NEXT: s_lshr_b32 s47, s25, 8
|
|
; GFX11-NEXT: s_lshr_b32 s59, s24, 16
|
|
; GFX11-NEXT: s_lshr_b32 s58, s24, 8
|
|
; GFX11-NEXT: s_lshr_b32 s61, s23, 24
|
|
; GFX11-NEXT: s_lshr_b32 s62, s23, 16
|
|
; GFX11-NEXT: s_lshr_b32 s60, s23, 8
|
|
; GFX11-NEXT: s_lshr_b32 s72, s22, 16
|
|
; GFX11-NEXT: s_lshr_b32 s63, s22, 8
|
|
; GFX11-NEXT: s_lshr_b32 s74, s21, 24
|
|
; GFX11-NEXT: s_lshr_b32 s75, s21, 16
|
|
; GFX11-NEXT: s_lshr_b32 s73, s21, 8
|
|
; GFX11-NEXT: s_lshr_b32 s77, s20, 16
|
|
; GFX11-NEXT: s_lshr_b32 s76, s20, 8
|
|
; GFX11-NEXT: s_lshr_b32 s78, s19, 24
|
|
; GFX11-NEXT: s_lshr_b32 s88, s19, 16
|
|
; GFX11-NEXT: s_lshr_b32 s79, s19, 8
|
|
; GFX11-NEXT: s_lshr_b32 s90, s18, 16
|
|
; GFX11-NEXT: s_lshr_b32 s89, s18, 8
|
|
; GFX11-NEXT: s_lshr_b32 s92, s17, 24
|
|
; GFX11-NEXT: s_lshr_b32 s93, s17, 16
|
|
; GFX11-NEXT: s_lshr_b32 s91, s17, 8
|
|
; GFX11-NEXT: s_lshr_b32 s95, s16, 16
|
|
; GFX11-NEXT: s_lshr_b32 s94, s16, 8
|
|
; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 24
|
|
; GFX11-NEXT: s_lshr_b32 s30, s3, 16
|
|
; GFX11-NEXT: s_lshr_b32 s31, s3, 8
|
|
; GFX11-NEXT: s_lshr_b32 s34, s2, 16
|
|
; GFX11-NEXT: s_lshr_b32 s35, s2, 8
|
|
; GFX11-NEXT: s_lshr_b32 s36, s1, 24
|
|
; GFX11-NEXT: s_lshr_b32 s37, s1, 16
|
|
; GFX11-NEXT: s_lshr_b32 s38, s1, 8
|
|
; GFX11-NEXT: s_lshr_b32 s39, s0, 16
|
|
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
|
|
; GFX11-NEXT: .LBB25_3: ; %end
|
|
; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
|
|
; GFX11-NEXT: v_readlane_b32 s34, v23, 0
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
|
|
; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
|
|
; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
|
|
; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
|
|
; GFX11-NEXT: v_perm_b32 v6, s2, s35, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
|
|
; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
|
|
; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
|
|
; GFX11-NEXT: v_or_b32_e32 v3, v6, v5
|
|
; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
|
|
; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
|
|
; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
|
|
; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
|
|
; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-NEXT: v_or_b32_e32 v5, v6, v9
|
|
; GFX11-NEXT: v_perm_b32 v9, s88, s78, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
|
|
; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
|
|
; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
|
|
; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
|
|
; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
|
|
; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-NEXT: v_perm_b32 v13, s20, s76, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-NEXT: v_perm_b32 v15, s21, s73, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-NEXT: v_perm_b32 v16, s22, s63, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX11-NEXT: v_or_b32_e32 v9, v13, v10
|
|
; GFX11-NEXT: v_perm_b32 v13, s62, s61, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v10, v15, v11
|
|
; GFX11-NEXT: v_or_b32_e32 v11, v16, v14
|
|
; GFX11-NEXT: v_perm_b32 v14, s59, s6, v12
|
|
; GFX11-NEXT: v_perm_b32 v17, s57, s56, v12
|
|
; GFX11-NEXT: v_perm_b32 v18, s46, s4, v12
|
|
; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
|
|
; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX11-NEXT: v_perm_b32 v21, s26, s45, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_perm_b32 v22, s27, s43, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-NEXT: v_or_b32_e32 v13, v16, v14
|
|
; GFX11-NEXT: v_or_b32_e32 v14, v19, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v15, v21, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v16, v22, v20
|
|
; GFX11-NEXT: v_readlane_b32 s30, v23, 7
|
|
; GFX11-NEXT: s_clause 0x3
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-NEXT: v_readlane_b32 s31, v23, 8
|
|
; GFX11-NEXT: v_readlane_b32 s48, v23, 6
|
|
; GFX11-NEXT: v_readlane_b32 s39, v23, 5
|
|
; GFX11-NEXT: v_readlane_b32 s38, v23, 4
|
|
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
|
|
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
|
|
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
|
|
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
|
|
; GFX11-NEXT: scratch_load_b32 v23, off, s32 ; 4-byte Folded Reload
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s0
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB25_4:
|
|
; GFX11-NEXT: ; implicit-def: $sgpr48
|
|
; GFX11-NEXT: ; implicit-def: $sgpr39
|
|
; GFX11-NEXT: ; implicit-def: $sgpr40
|
|
; GFX11-NEXT: ; implicit-def: $sgpr38
|
|
; GFX11-NEXT: ; implicit-def: $sgpr37
|
|
; GFX11-NEXT: ; implicit-def: $sgpr36
|
|
; GFX11-NEXT: ; implicit-def: $sgpr35
|
|
; GFX11-NEXT: ; implicit-def: $sgpr34
|
|
; GFX11-NEXT: ; implicit-def: $sgpr28
|
|
; GFX11-NEXT: ; implicit-def: $sgpr31
|
|
; GFX11-NEXT: ; implicit-def: $sgpr30
|
|
; GFX11-NEXT: ; implicit-def: $vcc_hi
|
|
; GFX11-NEXT: ; implicit-def: $sgpr94
|
|
; GFX11-NEXT: ; implicit-def: $sgpr95
|
|
; GFX11-NEXT: ; implicit-def: $sgpr14
|
|
; GFX11-NEXT: ; implicit-def: $sgpr91
|
|
; GFX11-NEXT: ; implicit-def: $sgpr93
|
|
; GFX11-NEXT: ; implicit-def: $sgpr92
|
|
; GFX11-NEXT: ; implicit-def: $sgpr89
|
|
; GFX11-NEXT: ; implicit-def: $sgpr90
|
|
; GFX11-NEXT: ; implicit-def: $sgpr12
|
|
; GFX11-NEXT: ; implicit-def: $sgpr79
|
|
; GFX11-NEXT: ; implicit-def: $sgpr88
|
|
; GFX11-NEXT: ; implicit-def: $sgpr78
|
|
; GFX11-NEXT: ; implicit-def: $sgpr76
|
|
; GFX11-NEXT: ; implicit-def: $sgpr77
|
|
; GFX11-NEXT: ; implicit-def: $sgpr10
|
|
; GFX11-NEXT: ; implicit-def: $sgpr73
|
|
; GFX11-NEXT: ; implicit-def: $sgpr75
|
|
; GFX11-NEXT: ; implicit-def: $sgpr74
|
|
; GFX11-NEXT: ; implicit-def: $sgpr63
|
|
; GFX11-NEXT: ; implicit-def: $sgpr72
|
|
; GFX11-NEXT: ; implicit-def: $sgpr8
|
|
; GFX11-NEXT: ; implicit-def: $sgpr60
|
|
; GFX11-NEXT: ; implicit-def: $sgpr62
|
|
; GFX11-NEXT: ; implicit-def: $sgpr61
|
|
; GFX11-NEXT: ; implicit-def: $sgpr58
|
|
; GFX11-NEXT: ; implicit-def: $sgpr59
|
|
; GFX11-NEXT: ; implicit-def: $sgpr6
|
|
; GFX11-NEXT: ; implicit-def: $sgpr47
|
|
; GFX11-NEXT: ; implicit-def: $sgpr57
|
|
; GFX11-NEXT: ; implicit-def: $sgpr56
|
|
; GFX11-NEXT: ; implicit-def: $sgpr45
|
|
; GFX11-NEXT: ; implicit-def: $sgpr46
|
|
; GFX11-NEXT: ; implicit-def: $sgpr4
|
|
; GFX11-NEXT: ; implicit-def: $sgpr43
|
|
; GFX11-NEXT: ; implicit-def: $sgpr44
|
|
; GFX11-NEXT: ; implicit-def: $sgpr42
|
|
; GFX11-NEXT: s_branch .LBB25_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <16 x i32> %a, splat (i32 3)
|
|
%a2 = bitcast <16 x i32> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x i32> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v16i32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v34, v6
|
|
; SI-NEXT: v_mov_b32_e32 v33, v4
|
|
; SI-NEXT: v_mov_b32_e32 v32, v2
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:80
|
|
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:88
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:96
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:104
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:112
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:120
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:128
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 8, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v17
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v8
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v10
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v12
|
|
; SI-NEXT: s_waitcnt vmcnt(10)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v50
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v51
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v52
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v53
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v55
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v40
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v42
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v44
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v58
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v47
|
|
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100
|
|
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB26_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v49
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v1, v48, v1
|
|
; SI-NEXT: v_or_b32_e32 v3, v35, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v57
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v62, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v56, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v52
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v43, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v54, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v44
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v21, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v53
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v27, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v37, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v20, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v24, v6
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v28, v7
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v38
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v17, v8
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v18
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v30
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v63
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v45
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v59
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v46
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v41
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v47
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v51
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v19
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v25
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v50, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: .LBB26_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB26_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
|
|
; SI-NEXT: v_or_b32_e32 v0, v49, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v48, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
|
|
; SI-NEXT: v_or_b32_e32 v1, v39, v1
|
|
; SI-NEXT: s_movk_i32 s6, 0x300
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v35, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v57
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v62, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v42
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v56, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v43, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v54, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v44
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v21, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v27, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: s_mov_b32 s7, 0x3000000
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v36, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v37, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v20, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v24, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v28, v7
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v38, v3
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v17, v8
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v18, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v22, v5
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v26, v6
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v30, v7
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v60
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v63, v8
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v59, v9
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v46, v10
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v41, v11
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v47
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v51, v12
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v19, v13
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v23
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v25, v14
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x300, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v50, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
|
|
; SI-NEXT: .LBB26_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v16i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v53, v1
|
|
; VI-NEXT: v_mov_b32_e32 v54, v0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:128
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:88
|
|
; VI-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; VI-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:80
|
|
; VI-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: v_mov_b32_e32 v31, v15
|
|
; VI-NEXT: v_mov_b32_e32 v32, v14
|
|
; VI-NEXT: v_mov_b32_e32 v33, v13
|
|
; VI-NEXT: v_mov_b32_e32 v34, v12
|
|
; VI-NEXT: v_mov_b32_e32 v35, v11
|
|
; VI-NEXT: v_mov_b32_e32 v36, v10
|
|
; VI-NEXT: v_mov_b32_e32 v37, v9
|
|
; VI-NEXT: v_mov_b32_e32 v38, v8
|
|
; VI-NEXT: v_mov_b32_e32 v39, v7
|
|
; VI-NEXT: v_mov_b32_e32 v48, v6
|
|
; VI-NEXT: v_mov_b32_e32 v49, v5
|
|
; VI-NEXT: v_mov_b32_e32 v50, v4
|
|
; VI-NEXT: v_mov_b32_e32 v51, v3
|
|
; VI-NEXT: v_mov_b32_e32 v52, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:124
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:120
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:116
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:112
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:108
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:104
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:100
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:96
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:92
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB26_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
|
|
; VI-NEXT: v_perm_b32 v3, v48, v39, s6
|
|
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
|
|
; VI-NEXT: v_perm_b32 v2, v50, v49, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
|
|
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v16, v25, v16, s6
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: .LBB26_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB26_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v54
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v53
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v52
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v51
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v50
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v49
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v48
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v39
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_mov_b32_e32 v15, 0x300
|
|
; VI-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; VI-NEXT: v_add_u16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v38
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v37
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v36
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v35
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v33
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v32
|
|
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v31
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; VI-NEXT: v_add_u16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v16
|
|
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v17
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v18
|
|
; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v19
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v4, 0x300, v4
|
|
; VI-NEXT: v_add_u16_sdwa v5, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v20
|
|
; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v21
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v22
|
|
; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v23
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v5, 0x300, v5
|
|
; VI-NEXT: v_add_u16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v30
|
|
; VI-NEXT: v_lshlrev_b16_e32 v10, 8, v27
|
|
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29
|
|
; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v42
|
|
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v63
|
|
; VI-NEXT: v_lshlrev_b16_e32 v14, 8, v59
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(5)
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v7
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v6, 0x300, v6
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; VI-NEXT: s_waitcnt vmcnt(3)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v18, 8, v18
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v7, 0x300, v7
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v57
|
|
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v56
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v26
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
|
|
; VI-NEXT: v_add_u16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v47
|
|
; VI-NEXT: v_lshlrev_b16_e32 v10, 8, v46
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v28
|
|
; VI-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v9, 0x300, v9
|
|
; VI-NEXT: v_add_u16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v45
|
|
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v44
|
|
; VI-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v43
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v10, 0x300, v10
|
|
; VI-NEXT: v_add_u16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v41
|
|
; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v40
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v55
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v11, 0x300, v11
|
|
; VI-NEXT: v_add_u16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v62
|
|
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v61
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v60
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v12, 0x300, v12
|
|
; VI-NEXT: v_add_u16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v58
|
|
; VI-NEXT: v_lshlrev_b16_e32 v14, 8, v24
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v13, 0x300, v13
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: v_or_b32_sdwa v14, v16, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v14, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; VI-NEXT: v_or_b32_sdwa v14, v16, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v16
|
|
; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v16, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v16
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v17, 3, v25
|
|
; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v16
|
|
; VI-NEXT: v_add_u16_sdwa v15, v17, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: .LBB26_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v16i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:128
|
|
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
|
|
; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:80
|
|
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, v15
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, v14
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, v13
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, v12
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, v11
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, v2
|
|
; GFX9-NEXT: s_waitcnt vmcnt(24)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(22)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:124
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:120
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:116
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:112
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:108
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:104
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:100
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:96
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:92
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB26_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v0, v54, v53, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v52, v51, s6
|
|
; GFX9-NEXT: v_perm_b32 v2, v50, v49, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v48, v39, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v2, v38, v37, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v36, v35, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v3, v34, v33, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v32, v31, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v9, v47, v46, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v45, v44, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v42, v30, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v55, v63, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v60, v59, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr22
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v43, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
|
|
; GFX9-NEXT: v_perm_b32 v8, v24, v25, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
|
|
; GFX9-NEXT: v_perm_b32 v9, v26, v27, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
|
|
; GFX9-NEXT: v_perm_b32 v10, v28, v29, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
|
|
; GFX9-NEXT: v_perm_b32 v11, v41, v40, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, v62, v61, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
|
|
; GFX9-NEXT: v_perm_b32 v13, v58, v57, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v16, v56, v16, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: .LBB26_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB26_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v54
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v53
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 3, v52
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v51
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v50
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v49
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v48
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v39
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x300
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v36
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 3, v32
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 3, v18
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 3, v22
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v46
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v44
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v30
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v63
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v59
|
|
; GFX9-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 3, v24
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v25
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
|
|
; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 3, v26
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v27
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 3, v45
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
|
|
; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 3, v28
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 3, v42
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
|
|
; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 3, v41
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v40
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 3, v55
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
|
|
; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 3, v62
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v61
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 3, v60
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
|
|
; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 3, v58
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v57
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v16, 3, v56
|
|
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
|
|
; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX9-NEXT: .LBB26_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v16i32:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1f
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:128
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:124
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:116
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:112
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:108
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:104
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:100
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:96
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:92
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:88
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:84
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:80
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:76
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:72
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:68
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v128, off, s32 offset:132
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v14.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v13.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v12.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v11.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v9.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v7.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v6.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v5.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v4.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v0.l
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v128
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB26_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB26_4
|
|
; GFX11-TRUE16-NEXT: .LBB26_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB26_3: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v119, v118, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v117, v116, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v114, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v113, v112, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v101, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v102, v100, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v99, v98, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v16, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v96, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v30, v87, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v86, v85, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v84, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v81, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v71, v69, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v68, v67, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v65, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v54, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB26_2
|
|
; GFX11-TRUE16-NEXT: .LBB26_4: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v117.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v118.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v116.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v115.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v113.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v114.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v112.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v103.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v102.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v100.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v99.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v101.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v17.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v4.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v97.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v96.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v20.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v4.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v22.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v26.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v27.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v3.h, v4.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v5.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v19.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v21.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v28.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v30.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v23.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v24.l, 3
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v86.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v82.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v81.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v6.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v6.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v25.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v80.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v71.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v68.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v8.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v29.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v87.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v65.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v55.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v54.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v9.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v85.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v84.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v12.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v13.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v52.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v9.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v83.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v51.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v50.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v49.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v70.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v69.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v12.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v13.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v10.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, v37.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v67.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v66.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v35.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v33.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v36.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v64.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v15.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v34.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v32.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v11.h, v11.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v53.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v31.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v17.l, v15.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v17.h, v15.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v12.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v48.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v12.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v13.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v13.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, v38.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v14.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v14.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v39.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v13.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v3.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v4.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v14.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v4.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v18.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v5.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v5.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v6.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v6.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v7.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v8.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v8.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v10.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v10.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v11.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v14.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v14.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v15.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v15.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v16.l
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v16i32:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1f
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:128
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:124
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:120
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:116
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:112
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:108
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:104
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:96
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:92
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:88
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:84
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:80
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:76
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:72
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:68
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:64
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v14
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v34, v12
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB26_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB26_4
|
|
; GFX11-FAKE16-NEXT: .LBB26_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB26_3: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v36, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v119, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v118, v117, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v115, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v112, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v113, v103, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v102, v100, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v101, v99, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v96, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v97, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v83, v81, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v70, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v71, v68, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v65, v55, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB26_2
|
|
; GFX11-FAKE16-NEXT: .LBB26_4: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v36, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v37
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v34, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v35
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v31
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v16, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v22, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v24, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v119
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v118, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v98, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v83, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v84
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v82
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v81
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v80, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v71, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v69, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v67, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v65, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v18, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v70
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v68
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v66
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v64
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v55
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v23, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v25, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v16i32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v28
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s11, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v24
|
|
; SI-NEXT: v_readfirstlane_b32 s13, v23
|
|
; SI-NEXT: v_readfirstlane_b32 s14, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s15, v21
|
|
; SI-NEXT: v_readfirstlane_b32 s40, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s41, v19
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s43, v17
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s45, v15
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s47, v13
|
|
; SI-NEXT: v_readfirstlane_b32 s56, v12
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v30
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s59, v9
|
|
; SI-NEXT: v_readfirstlane_b32 s60, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s61, v7
|
|
; SI-NEXT: v_readfirstlane_b32 s62, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s63, v5
|
|
; SI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s73, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s74, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s75, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s76, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
|
|
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v22
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v24
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v25
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v35
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v37
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
|
|
; SI-NEXT: s_cbranch_scc0 .LBB27_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, s4, v34
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s18, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s77, s19, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s77, s5
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s77, s21, 8
|
|
; SI-NEXT: s_or_b32 s5, s5, s77
|
|
; SI-NEXT: s_and_b32 s77, s22, 0xff
|
|
; SI-NEXT: s_lshl_b32 s77, s77, 16
|
|
; SI-NEXT: s_lshl_b32 s78, s23, 24
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s77, s78, s77
|
|
; SI-NEXT: s_or_b32 s5, s5, s77
|
|
; SI-NEXT: s_and_b32 s77, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s78, s25, 8
|
|
; SI-NEXT: s_or_b32 s77, s77, s78
|
|
; SI-NEXT: s_and_b32 s78, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s78, s78, 16
|
|
; SI-NEXT: s_lshl_b32 s79, s27, 24
|
|
; SI-NEXT: s_and_b32 s77, s77, 0xffff
|
|
; SI-NEXT: s_or_b32 s78, s79, s78
|
|
; SI-NEXT: s_or_b32 s77, s77, s78
|
|
; SI-NEXT: s_and_b32 s78, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s79, s29, 8
|
|
; SI-NEXT: s_or_b32 s78, s78, s79
|
|
; SI-NEXT: s_and_b32 s79, s76, 0xff
|
|
; SI-NEXT: s_lshl_b32 s79, s79, 16
|
|
; SI-NEXT: s_lshl_b32 s88, s75, 24
|
|
; SI-NEXT: s_and_b32 s78, s78, 0xffff
|
|
; SI-NEXT: s_or_b32 s79, s88, s79
|
|
; SI-NEXT: s_or_b32 s78, s78, s79
|
|
; SI-NEXT: s_and_b32 s79, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s88, s73, 8
|
|
; SI-NEXT: s_or_b32 s79, s79, s88
|
|
; SI-NEXT: s_and_b32 s88, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s88, s88, 16
|
|
; SI-NEXT: s_lshl_b32 s89, s63, 24
|
|
; SI-NEXT: s_and_b32 s79, s79, 0xffff
|
|
; SI-NEXT: s_or_b32 s88, s89, s88
|
|
; SI-NEXT: s_or_b32 s79, s79, s88
|
|
; SI-NEXT: s_and_b32 s88, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s89, s61, 8
|
|
; SI-NEXT: s_or_b32 s88, s88, s89
|
|
; SI-NEXT: s_and_b32 s89, s60, 0xff
|
|
; SI-NEXT: s_lshl_b32 s89, s89, 16
|
|
; SI-NEXT: s_lshl_b32 s90, s59, 24
|
|
; SI-NEXT: s_and_b32 s88, s88, 0xffff
|
|
; SI-NEXT: s_or_b32 s89, s90, s89
|
|
; SI-NEXT: s_or_b32 s88, s88, s89
|
|
; SI-NEXT: s_and_b32 s89, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s90, s57, 8
|
|
; SI-NEXT: s_or_b32 s89, s89, s90
|
|
; SI-NEXT: s_and_b32 s90, s56, 0xff
|
|
; SI-NEXT: s_lshl_b32 s90, s90, 16
|
|
; SI-NEXT: s_lshl_b32 s91, s47, 24
|
|
; SI-NEXT: s_and_b32 s89, s89, 0xffff
|
|
; SI-NEXT: s_or_b32 s90, s91, s90
|
|
; SI-NEXT: s_or_b32 s89, s89, s90
|
|
; SI-NEXT: s_and_b32 s90, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s91, s45, 8
|
|
; SI-NEXT: s_or_b32 s90, s90, s91
|
|
; SI-NEXT: s_and_b32 s91, s44, 0xff
|
|
; SI-NEXT: s_lshl_b32 s91, s91, 16
|
|
; SI-NEXT: s_lshl_b32 s92, s43, 24
|
|
; SI-NEXT: s_and_b32 s90, s90, 0xffff
|
|
; SI-NEXT: s_or_b32 s91, s92, s91
|
|
; SI-NEXT: s_or_b32 s90, s90, s91
|
|
; SI-NEXT: s_and_b32 s91, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s92, s41, 8
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v20
|
|
; SI-NEXT: s_or_b32 s91, s91, s92
|
|
; SI-NEXT: s_and_b32 s92, s40, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_lshl_b32 s92, s92, 16
|
|
; SI-NEXT: s_lshl_b32 s93, s15, 24
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v33, v1
|
|
; SI-NEXT: s_and_b32 s91, s91, 0xffff
|
|
; SI-NEXT: s_or_b32 s92, s93, s92
|
|
; SI-NEXT: v_or_b32_e32 v11, v0, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v21
|
|
; SI-NEXT: s_or_b32 s91, s91, s92
|
|
; SI-NEXT: s_and_b32 s92, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s93, s13, 8
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s92, s92, s93
|
|
; SI-NEXT: s_and_b32 s93, s12, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v29, v1
|
|
; SI-NEXT: s_lshl_b32 s93, s93, 16
|
|
; SI-NEXT: s_lshl_b32 s94, s11, 24
|
|
; SI-NEXT: v_or_b32_e32 v13, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v19
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
|
|
; SI-NEXT: s_and_b32 s92, s92, 0xffff
|
|
; SI-NEXT: s_or_b32 s93, s94, s93
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s92, s92, s93
|
|
; SI-NEXT: s_and_b32 s93, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s94, s9, 8
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v25, v1
|
|
; SI-NEXT: s_or_b32 s93, s93, s94
|
|
; SI-NEXT: s_and_b32 s94, s8, 0xff
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v28
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v26
|
|
; SI-NEXT: v_or_b32_e32 v14, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
|
|
; SI-NEXT: s_lshl_b32 s94, s94, 16
|
|
; SI-NEXT: s_lshl_b32 s95, s7, 24
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_and_b32 s93, s93, 0xffff
|
|
; SI-NEXT: s_or_b32 s94, s95, s94
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v31, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v22, v1
|
|
; SI-NEXT: s_or_b32 s93, s93, s94
|
|
; SI-NEXT: v_or_b32_e32 v12, v2, v3
|
|
; SI-NEXT: v_or_b32_e32 v15, v0, v1
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
; SI-NEXT: v_mov_b32_e32 v2, s77
|
|
; SI-NEXT: v_mov_b32_e32 v3, s78
|
|
; SI-NEXT: v_mov_b32_e32 v4, s79
|
|
; SI-NEXT: v_mov_b32_e32 v5, s88
|
|
; SI-NEXT: v_mov_b32_e32 v6, s89
|
|
; SI-NEXT: v_mov_b32_e32 v7, s90
|
|
; SI-NEXT: v_mov_b32_e32 v8, s91
|
|
; SI-NEXT: v_mov_b32_e32 v9, s92
|
|
; SI-NEXT: v_mov_b32_e32 v10, s93
|
|
; SI-NEXT: s_cbranch_execnz .LBB27_3
|
|
; SI-NEXT: .LBB27_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s16, s18, 0xff
|
|
; SI-NEXT: s_addk_i32 s4, 0x300
|
|
; SI-NEXT: s_lshl_b32 s5, s19, 24
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s5, s16
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s16, s21, 8
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_or_b32 s5, s16, s5
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xff
|
|
; SI-NEXT: s_addk_i32 s5, 0x300
|
|
; SI-NEXT: s_lshl_b32 s16, s23, 24
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_or_b32 s5, s16, s5
|
|
; SI-NEXT: s_and_b32 s16, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s25, 8
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s6, s6, 3
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s18, s26, 0xff
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
|
|
; SI-NEXT: s_addk_i32 s16, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s27, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, s6, v34
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s17, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s18, s29, 8
|
|
; SI-NEXT: s_add_i32 s76, s76, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v33, v1
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_and_b32 s19, s76, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_addk_i32 s17, 0x300
|
|
; SI-NEXT: s_lshl_b32 s18, s75, 24
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v28
|
|
; SI-NEXT: s_and_b32 s17, s17, 0xffff
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_add_i32 s74, s74, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_and_b32 s18, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s19, s73, 8
|
|
; SI-NEXT: s_add_i32 s72, s72, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v32, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_and_b32 s20, s72, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_addk_i32 s18, 0x300
|
|
; SI-NEXT: s_lshl_b32 s19, s63, 24
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v31, v1
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xffff
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_add_i32 s62, s62, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_and_b32 s19, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s20, s61, 8
|
|
; SI-NEXT: s_add_i32 s60, s60, 3
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v23
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s21, s60, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v21
|
|
; SI-NEXT: s_addk_i32 s19, 0x300
|
|
; SI-NEXT: s_lshl_b32 s20, s59, 24
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, v30, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s19, s19, 0xffff
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_add_i32 s58, s58, 3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s20, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s21, s57, 8
|
|
; SI-NEXT: s_add_i32 s56, s56, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v29, v1
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s22, s56, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_addk_i32 s20, 0x300
|
|
; SI-NEXT: s_lshl_b32 s21, s47, 24
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
|
|
; SI-NEXT: s_and_b32 s20, s20, 0xffff
|
|
; SI-NEXT: s_or_b32 s21, s21, s22
|
|
; SI-NEXT: s_add_i32 s46, s46, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s21, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s22, s45, 8
|
|
; SI-NEXT: s_add_i32 s44, s44, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v27, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_or_b32 s21, s22, s21
|
|
; SI-NEXT: s_and_b32 s23, s44, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_addk_i32 s21, 0x300
|
|
; SI-NEXT: s_lshl_b32 s22, s43, 24
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v25, v1
|
|
; SI-NEXT: s_and_b32 s21, s21, 0xffff
|
|
; SI-NEXT: s_or_b32 s22, s22, s23
|
|
; SI-NEXT: s_add_i32 s42, s42, 3
|
|
; SI-NEXT: s_add_i32 s14, s14, 3
|
|
; SI-NEXT: s_add_i32 s10, s10, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_or_b32 s21, s22, s21
|
|
; SI-NEXT: s_and_b32 s22, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s23, s41, 8
|
|
; SI-NEXT: s_add_i32 s40, s40, 3
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 8
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 8
|
|
; SI-NEXT: s_add_i32 s8, s8, 3
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
|
|
; SI-NEXT: s_or_b32 s22, s23, s22
|
|
; SI-NEXT: s_and_b32 s23, s40, 0xff
|
|
; SI-NEXT: s_or_b32 s13, s13, s14
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xff
|
|
; SI-NEXT: s_or_b32 s9, s9, s10
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
|
|
; SI-NEXT: s_addk_i32 s22, 0x300
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 24
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_addk_i32 s13, 0x300
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 24
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_addk_i32 s9, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 24
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, v24, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s22, s22, 0xffff
|
|
; SI-NEXT: s_or_b32 s15, s15, s23
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_or_b32 s11, s11, s12
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s8
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s15, s15, s22
|
|
; SI-NEXT: s_or_b32 s11, s11, s13
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v22, v1
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
|
|
; SI-NEXT: s_add_i32 s16, s16, 0x3000000
|
|
; SI-NEXT: s_add_i32 s17, s17, 0x3000000
|
|
; SI-NEXT: s_add_i32 s18, s18, 0x3000000
|
|
; SI-NEXT: s_add_i32 s19, s19, 0x3000000
|
|
; SI-NEXT: s_add_i32 s20, s20, 0x3000000
|
|
; SI-NEXT: s_add_i32 s21, s21, 0x3000000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
; SI-NEXT: v_mov_b32_e32 v2, s16
|
|
; SI-NEXT: v_mov_b32_e32 v3, s17
|
|
; SI-NEXT: v_mov_b32_e32 v4, s18
|
|
; SI-NEXT: v_mov_b32_e32 v5, s19
|
|
; SI-NEXT: v_mov_b32_e32 v6, s20
|
|
; SI-NEXT: v_mov_b32_e32 v7, s21
|
|
; SI-NEXT: v_mov_b32_e32 v8, s15
|
|
; SI-NEXT: v_mov_b32_e32 v9, s11
|
|
; SI-NEXT: v_mov_b32_e32 v10, s7
|
|
; SI-NEXT: .LBB27_3: ; %end
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB27_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_branch .LBB27_2
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v16i32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v30
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v29
|
|
; VI-NEXT: v_readfirstlane_b32 s8, v28
|
|
; VI-NEXT: v_readfirstlane_b32 s9, v27
|
|
; VI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; VI-NEXT: v_readfirstlane_b32 s11, v25
|
|
; VI-NEXT: v_readfirstlane_b32 s12, v24
|
|
; VI-NEXT: v_readfirstlane_b32 s13, v23
|
|
; VI-NEXT: v_readfirstlane_b32 s14, v22
|
|
; VI-NEXT: v_readfirstlane_b32 s15, v21
|
|
; VI-NEXT: v_readfirstlane_b32 s40, v20
|
|
; VI-NEXT: v_readfirstlane_b32 s41, v19
|
|
; VI-NEXT: v_readfirstlane_b32 s42, v18
|
|
; VI-NEXT: v_readfirstlane_b32 s43, v17
|
|
; VI-NEXT: v_readfirstlane_b32 s44, v16
|
|
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: v_readfirstlane_b32 s45, v15
|
|
; VI-NEXT: v_readfirstlane_b32 s46, v14
|
|
; VI-NEXT: v_readfirstlane_b32 s47, v13
|
|
; VI-NEXT: v_readfirstlane_b32 s56, v12
|
|
; VI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; VI-NEXT: v_readfirstlane_b32 s58, v10
|
|
; VI-NEXT: v_readfirstlane_b32 s59, v9
|
|
; VI-NEXT: v_readfirstlane_b32 s60, v8
|
|
; VI-NEXT: v_readfirstlane_b32 s61, v7
|
|
; VI-NEXT: v_readfirstlane_b32 s62, v6
|
|
; VI-NEXT: v_readfirstlane_b32 s63, v5
|
|
; VI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; VI-NEXT: v_readfirstlane_b32 s73, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s74, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s75, v1
|
|
; VI-NEXT: v_readfirstlane_b32 s76, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; VI-NEXT: s_cbranch_scc0 .LBB27_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_mov_b32_e32 v3, s23
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_mov_b32_e32 v2, s21
|
|
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s75
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_mov_b32_e32 v5, s63
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_mov_b32_e32 v4, s73
|
|
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_mov_b32_e32 v5, s61
|
|
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_mov_b32_e32 v7, s47
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_mov_b32_e32 v6, s57
|
|
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_mov_b32_e32 v8, s43
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_mov_b32_e32 v7, s45
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_mov_b32_e32 v9, s15
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_mov_b32_e32 v8, s41
|
|
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_mov_b32_e32 v10, s11
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_mov_b32_e32 v9, s13
|
|
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_mov_b32_e32 v12, s7
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_mov_b32_e32 v10, s9
|
|
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; VI-NEXT: v_perm_b32 v12, v24, v22, s4
|
|
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
|
|
; VI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
|
|
; VI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
|
|
; VI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
|
|
; VI-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; VI-NEXT: s_cbranch_execnz .LBB27_3
|
|
; VI-NEXT: .LBB27_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x300, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s21
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: v_mov_b32_e32 v2, s23
|
|
; VI-NEXT: v_perm_b32 v1, s20, v1, v11
|
|
; VI-NEXT: v_perm_b32 v2, s22, v2, v11
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x300, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x300, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: s_add_i32 s76, s76, 3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s75
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x300, v3
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s74, s74, 3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s73
|
|
; VI-NEXT: s_add_i32 s72, s72, 3
|
|
; VI-NEXT: v_mov_b32_e32 v5, s63
|
|
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x300, v4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s62, s62, 3
|
|
; VI-NEXT: v_mov_b32_e32 v5, s61
|
|
; VI-NEXT: s_add_i32 s60, s60, 3
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x300, v5
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s58, s58, 3
|
|
; VI-NEXT: v_mov_b32_e32 v6, s57
|
|
; VI-NEXT: s_add_i32 s56, s56, 3
|
|
; VI-NEXT: v_mov_b32_e32 v7, s47
|
|
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x300, v6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s46, s46, 3
|
|
; VI-NEXT: v_mov_b32_e32 v7, s45
|
|
; VI-NEXT: s_add_i32 s44, s44, 3
|
|
; VI-NEXT: v_mov_b32_e32 v8, s43
|
|
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x300, v7
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s42, s42, 3
|
|
; VI-NEXT: v_mov_b32_e32 v8, s41
|
|
; VI-NEXT: s_add_i32 s40, s40, 3
|
|
; VI-NEXT: v_mov_b32_e32 v9, s15
|
|
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x300, v8
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s14, s14, 3
|
|
; VI-NEXT: v_mov_b32_e32 v9, s13
|
|
; VI-NEXT: s_add_i32 s12, s12, 3
|
|
; VI-NEXT: v_mov_b32_e32 v10, s11
|
|
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x300, v9
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s10, s10, 3
|
|
; VI-NEXT: v_mov_b32_e32 v10, s9
|
|
; VI-NEXT: s_add_i32 s8, s8, 3
|
|
; VI-NEXT: v_mov_b32_e32 v12, s7
|
|
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x300, v10
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_sdwa v10, v12, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v24
|
|
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
|
|
; VI-NEXT: v_perm_b32 v12, v12, v22, s4
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x300, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v34
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v32
|
|
; VI-NEXT: v_perm_b32 v12, v12, v33, s4
|
|
; VI-NEXT: v_perm_b32 v13, v13, v31, s4
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x300, v12
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v30
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v28
|
|
; VI-NEXT: v_perm_b32 v13, v13, v29, s4
|
|
; VI-NEXT: v_perm_b32 v14, v14, v27, s4
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x300, v13
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v25
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v21
|
|
; VI-NEXT: v_perm_b32 v14, v14, v23, s4
|
|
; VI-NEXT: v_perm_b32 v15, v15, v20, s4
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x300, v14
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v19
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
|
|
; VI-NEXT: v_perm_b32 v15, v15, v18, s4
|
|
; VI-NEXT: v_perm_b32 v16, v17, v16, s4
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x300, v15
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x3000000, v3
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x3000000, v4
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x3000000, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x3000000, v6
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x3000000, v10
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x3000000, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x3000000, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x3000000, v13
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x3000000, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x3000000, v15
|
|
; VI-NEXT: .LBB27_3: ; %end
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB27_4:
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_branch .LBB27_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v16i32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v30
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v29
|
|
; GFX9-NEXT: v_readfirstlane_b32 s8, v28
|
|
; GFX9-NEXT: v_readfirstlane_b32 s9, v27
|
|
; GFX9-NEXT: v_readfirstlane_b32 s10, v26
|
|
; GFX9-NEXT: v_readfirstlane_b32 s11, v25
|
|
; GFX9-NEXT: v_readfirstlane_b32 s12, v24
|
|
; GFX9-NEXT: v_readfirstlane_b32 s13, v23
|
|
; GFX9-NEXT: v_readfirstlane_b32 s14, v22
|
|
; GFX9-NEXT: v_readfirstlane_b32 s15, v21
|
|
; GFX9-NEXT: v_readfirstlane_b32 s40, v20
|
|
; GFX9-NEXT: v_readfirstlane_b32 s41, v19
|
|
; GFX9-NEXT: v_readfirstlane_b32 s42, v18
|
|
; GFX9-NEXT: v_readfirstlane_b32 s43, v17
|
|
; GFX9-NEXT: v_readfirstlane_b32 s44, v16
|
|
; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s46, v14
|
|
; GFX9-NEXT: v_readfirstlane_b32 s47, v13
|
|
; GFX9-NEXT: v_readfirstlane_b32 s56, v12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s57, v11
|
|
; GFX9-NEXT: v_readfirstlane_b32 s58, v10
|
|
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
|
|
; GFX9-NEXT: v_readfirstlane_b32 s60, v8
|
|
; GFX9-NEXT: v_readfirstlane_b32 s61, v7
|
|
; GFX9-NEXT: v_readfirstlane_b32 s62, v6
|
|
; GFX9-NEXT: v_readfirstlane_b32 s63, v5
|
|
; GFX9-NEXT: v_readfirstlane_b32 s72, v4
|
|
; GFX9-NEXT: v_readfirstlane_b32 s73, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s74, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s75, v1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s76, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s75
|
|
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s63
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s73
|
|
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s59
|
|
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s61
|
|
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s47
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s57
|
|
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s43
|
|
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s45
|
|
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s15
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s41
|
|
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s11
|
|
; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s13
|
|
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s7
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s9
|
|
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
|
|
; GFX9-NEXT: .LBB27_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; GFX9-NEXT: s_movk_i32 s4, 0x300
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_add_u32_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u32_sdwa v3, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u32_sdwa v3, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: s_add_i32 s76, s76, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s75
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_add_u32_sdwa v4, v4, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s73
|
|
; GFX9-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s63
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_add_u32_sdwa v5, v5, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s61
|
|
; GFX9-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s59
|
|
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_add_u32_sdwa v6, v6, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s57
|
|
; GFX9-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s47
|
|
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_add_u32_sdwa v7, v7, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s45
|
|
; GFX9-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s43
|
|
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_add_u32_sdwa v8, v8, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s41
|
|
; GFX9-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s15
|
|
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 0x300, v8
|
|
; GFX9-NEXT: v_add_u32_sdwa v9, v9, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s13
|
|
; GFX9-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s11
|
|
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 0x300, v9
|
|
; GFX9-NEXT: v_add_u32_sdwa v10, v10, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s9
|
|
; GFX9-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s7
|
|
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
|
|
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v23
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v21, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v11
|
|
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v34
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v32
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v33, s5
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v31, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v12
|
|
; GFX9-NEXT: v_add_u32_sdwa v13, v13, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v30
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v28
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v29, s5
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v27, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v26
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v22
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v24, s5
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v20, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v14
|
|
; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v18, s5
|
|
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v15
|
|
; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: .LBB27_3: ; %end
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB27_4:
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_branch .LBB27_2
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v16i32_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0xf
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB27_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB27_3
|
|
; GFX11-TRUE16-NEXT: .LBB27_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s24, s25, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s28, s29, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s74, s73, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s62, s61, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s58, s57, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s46, s45, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s42, s41, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s14, s13, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s12, s11, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s10, s9, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v13
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v14, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-TRUE16-NEXT: .LBB27_3: ; %end
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB27_4:
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB27_2
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v16i32_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_clause 0xf
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v30
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v29
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v28
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v27
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v26
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v25
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v24
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v23
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v22
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v21
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v19
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v18
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v16
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v15
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v14
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v13
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v12
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v11
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v10
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v9
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v8
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v7
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v6
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v5
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v4
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v3
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v2
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB27_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB27_3
|
|
; GFX11-FAKE16-NEXT: .LBB27_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s24, s25, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s26, s27, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s28, s29, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s74, s73, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s62, s61, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s58, s57, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s46, s45, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s42, s41, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s13, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s12, s11, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s10, s9, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v13
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v14, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v51
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s8, s7, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s6, s5, v11
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s4, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-FAKE16-NEXT: .LBB27_3: ; %end
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB27_4:
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB27_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <16 x i32>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <16 x i32>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x i32> %phi
|
|
}
|
|
|
|
define <8 x i64> @bitcast_v16f32_to_v8i64(<16 x float> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v8i64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB28_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: .LBB28_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v8i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB28_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: .LBB28_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v8i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB28_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX9-NEXT: .LBB28_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v8i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB28_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
|
|
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
|
|
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
|
|
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
|
|
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
|
|
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
|
|
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
|
|
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
|
|
; GFX11-NEXT: .LBB28_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define inreg <8 x i64> @bitcast_v16f32_to_v8i64_scalar(<16 x float> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v8i64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB29_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB29_4
|
|
; SI-NEXT: .LBB29_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; SI-NEXT: s_branch .LBB29_5
|
|
; SI-NEXT: .LBB29_3:
|
|
; SI-NEXT: s_branch .LBB29_2
|
|
; SI-NEXT: .LBB29_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s30
|
|
; SI-NEXT: v_mov_b32_e32 v15, s31
|
|
; SI-NEXT: .LBB29_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; SI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v8i64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB29_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB29_4
|
|
; VI-NEXT: .LBB29_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; VI-NEXT: s_branch .LBB29_5
|
|
; VI-NEXT: .LBB29_3:
|
|
; VI-NEXT: s_branch .LBB29_2
|
|
; VI-NEXT: .LBB29_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB29_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v8i64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB29_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB29_4
|
|
; GFX9-NEXT: .LBB29_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; GFX9-NEXT: s_branch .LBB29_5
|
|
; GFX9-NEXT: .LBB29_3:
|
|
; GFX9-NEXT: s_branch .LBB29_2
|
|
; GFX9-NEXT: .LBB29_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB29_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v8i64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB29_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB29_4
|
|
; GFX11-NEXT: .LBB29_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f32_e64 v15, s27, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v14, s26, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB29_3:
|
|
; GFX11-NEXT: s_branch .LBB29_2
|
|
; GFX11-NEXT: .LBB29_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define <16 x float> @bitcast_v8i64_to_v16f32(<8 x i64> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v16f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB30_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; SI-NEXT: .LBB30_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v16f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB30_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: .LBB30_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v16f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB30_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: .LBB30_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v16f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB30_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
|
|
; GFX11-NEXT: .LBB30_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define inreg <16 x float> @bitcast_v8i64_to_v16f32_scalar(<8 x i64> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v16f32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB31_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB31_3
|
|
; SI-NEXT: .LBB31_2: ; %cmp.true
|
|
; SI-NEXT: s_add_u32 s7, s7, 3
|
|
; SI-NEXT: s_addc_u32 s6, s6, 0
|
|
; SI-NEXT: s_add_u32 s28, s28, 3
|
|
; SI-NEXT: s_addc_u32 s29, s29, 0
|
|
; SI-NEXT: s_add_u32 s26, s26, 3
|
|
; SI-NEXT: s_addc_u32 s27, s27, 0
|
|
; SI-NEXT: s_add_u32 s24, s24, 3
|
|
; SI-NEXT: s_addc_u32 s25, s25, 0
|
|
; SI-NEXT: s_add_u32 s22, s22, 3
|
|
; SI-NEXT: s_addc_u32 s23, s23, 0
|
|
; SI-NEXT: s_add_u32 s20, s20, 3
|
|
; SI-NEXT: s_addc_u32 s21, s21, 0
|
|
; SI-NEXT: s_add_u32 s18, s18, 3
|
|
; SI-NEXT: s_addc_u32 s19, s19, 0
|
|
; SI-NEXT: s_add_u32 s16, s16, 3
|
|
; SI-NEXT: s_addc_u32 s17, s17, 0
|
|
; SI-NEXT: .LBB31_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s7
|
|
; SI-NEXT: v_mov_b32_e32 v15, s6
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB31_4:
|
|
; SI-NEXT: s_branch .LBB31_2
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v16f32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB31_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB31_3
|
|
; VI-NEXT: .LBB31_2: ; %cmp.true
|
|
; VI-NEXT: s_add_u32 s7, s7, 3
|
|
; VI-NEXT: s_addc_u32 s6, s6, 0
|
|
; VI-NEXT: s_add_u32 s28, s28, 3
|
|
; VI-NEXT: s_addc_u32 s29, s29, 0
|
|
; VI-NEXT: s_add_u32 s26, s26, 3
|
|
; VI-NEXT: s_addc_u32 s27, s27, 0
|
|
; VI-NEXT: s_add_u32 s24, s24, 3
|
|
; VI-NEXT: s_addc_u32 s25, s25, 0
|
|
; VI-NEXT: s_add_u32 s22, s22, 3
|
|
; VI-NEXT: s_addc_u32 s23, s23, 0
|
|
; VI-NEXT: s_add_u32 s20, s20, 3
|
|
; VI-NEXT: s_addc_u32 s21, s21, 0
|
|
; VI-NEXT: s_add_u32 s18, s18, 3
|
|
; VI-NEXT: s_addc_u32 s19, s19, 0
|
|
; VI-NEXT: s_add_u32 s16, s16, 3
|
|
; VI-NEXT: s_addc_u32 s17, s17, 0
|
|
; VI-NEXT: .LBB31_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB31_4:
|
|
; VI-NEXT: s_branch .LBB31_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v16f32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB31_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB31_3
|
|
; GFX9-NEXT: .LBB31_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_u32 s7, s7, 3
|
|
; GFX9-NEXT: s_addc_u32 s6, s6, 0
|
|
; GFX9-NEXT: s_add_u32 s28, s28, 3
|
|
; GFX9-NEXT: s_addc_u32 s29, s29, 0
|
|
; GFX9-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX9-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX9-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX9-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX9-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX9-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX9-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX9-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX9-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX9-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX9-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX9-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX9-NEXT: .LBB31_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB31_4:
|
|
; GFX9-NEXT: s_branch .LBB31_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v16f32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB31_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB31_3
|
|
; GFX11-NEXT: .LBB31_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX11-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX11-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX11-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX11-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX11-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX11-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX11-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX11-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX11-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX11-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX11-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX11-NEXT: s_add_u32 s2, s2, 3
|
|
; GFX11-NEXT: s_addc_u32 s3, s3, 0
|
|
; GFX11-NEXT: s_add_u32 s0, s0, 3
|
|
; GFX11-NEXT: s_addc_u32 s1, s1, 0
|
|
; GFX11-NEXT: .LBB31_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB31_4:
|
|
; GFX11-NEXT: s_branch .LBB31_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define <8 x double> @bitcast_v16f32_to_v8f64(<16 x float> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v8f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB32_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: .LBB32_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v8f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB32_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: .LBB32_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v8f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB32_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX9-NEXT: .LBB32_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v8f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB32_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
|
|
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
|
|
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
|
|
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
|
|
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
|
|
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
|
|
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
|
|
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
|
|
; GFX11-NEXT: .LBB32_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define inreg <8 x double> @bitcast_v16f32_to_v8f64_scalar(<16 x float> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v8f64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB33_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB33_4
|
|
; SI-NEXT: .LBB33_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; SI-NEXT: s_branch .LBB33_5
|
|
; SI-NEXT: .LBB33_3:
|
|
; SI-NEXT: s_branch .LBB33_2
|
|
; SI-NEXT: .LBB33_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s30
|
|
; SI-NEXT: v_mov_b32_e32 v15, s31
|
|
; SI-NEXT: .LBB33_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; SI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v8f64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB33_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB33_4
|
|
; VI-NEXT: .LBB33_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; VI-NEXT: s_branch .LBB33_5
|
|
; VI-NEXT: .LBB33_3:
|
|
; VI-NEXT: s_branch .LBB33_2
|
|
; VI-NEXT: .LBB33_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB33_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v8f64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB33_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB33_4
|
|
; GFX9-NEXT: .LBB33_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; GFX9-NEXT: s_branch .LBB33_5
|
|
; GFX9-NEXT: .LBB33_3:
|
|
; GFX9-NEXT: s_branch .LBB33_2
|
|
; GFX9-NEXT: .LBB33_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB33_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v8f64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB33_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB33_4
|
|
; GFX11-NEXT: .LBB33_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f32_e64 v15, s27, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v14, s26, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB33_3:
|
|
; GFX11-NEXT: s_branch .LBB33_2
|
|
; GFX11-NEXT: .LBB33_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define <16 x float> @bitcast_v8f64_to_v16f32(<8 x double> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v16f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB34_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: .LBB34_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v16f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB34_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: .LBB34_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v16f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB34_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX9-NEXT: .LBB34_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v16f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB34_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: .LBB34_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define inreg <16 x float> @bitcast_v8f64_to_v16f32_scalar(<8 x double> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v16f32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB35_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB35_4
|
|
; SI-NEXT: .LBB35_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; SI-NEXT: s_branch .LBB35_5
|
|
; SI-NEXT: .LBB35_3:
|
|
; SI-NEXT: s_branch .LBB35_2
|
|
; SI-NEXT: .LBB35_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s30
|
|
; SI-NEXT: v_mov_b32_e32 v15, s31
|
|
; SI-NEXT: .LBB35_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; SI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v16f32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB35_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB35_4
|
|
; VI-NEXT: .LBB35_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; VI-NEXT: s_branch .LBB35_5
|
|
; VI-NEXT: .LBB35_3:
|
|
; VI-NEXT: s_branch .LBB35_2
|
|
; VI-NEXT: .LBB35_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB35_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v16f32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB35_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB35_4
|
|
; GFX9-NEXT: .LBB35_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; GFX9-NEXT: s_branch .LBB35_5
|
|
; GFX9-NEXT: .LBB35_3:
|
|
; GFX9-NEXT: s_branch .LBB35_2
|
|
; GFX9-NEXT: .LBB35_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB35_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v16f32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB35_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB35_4
|
|
; GFX11-NEXT: .LBB35_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], s[26:27], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB35_3:
|
|
; GFX11-NEXT: s_branch .LBB35_2
|
|
; GFX11-NEXT: .LBB35_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define <32 x i16> @bitcast_v16f32_to_v32i16(<16 x float> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v32i16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB36_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB36_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB36_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB36_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v24
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v27
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v24
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v32i16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB36_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: .LBB36_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v32i16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB36_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX9-NEXT: .LBB36_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v32i16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB36_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
|
|
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
|
|
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
|
|
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
|
|
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
|
|
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
|
|
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
|
|
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
|
|
; GFX11-NEXT: .LBB36_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define inreg <32 x i16> @bitcast_v16f32_to_v32i16_scalar(<16 x float> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v32i16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB37_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s63, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB37_4
|
|
; SI-NEXT: .LBB37_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e64 v15, s5, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v14, s4, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[16:17], v[14:15], 16
|
|
; SI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[17:18], v[12:13], 16
|
|
; SI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[18:19], v[10:11], 16
|
|
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[19:20], v[8:9], 16
|
|
; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[20:21], v[6:7], 16
|
|
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[21:22], v[4:5], 16
|
|
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[22:23], v[2:3], 16
|
|
; SI-NEXT: v_lshr_b64 v[23:24], v[0:1], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
|
|
; SI-NEXT: s_branch .LBB37_5
|
|
; SI-NEXT: .LBB37_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: s_branch .LBB37_2
|
|
; SI-NEXT: .LBB37_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: v_mov_b32_e32 v32, s56
|
|
; SI-NEXT: v_mov_b32_e32 v31, s57
|
|
; SI-NEXT: v_mov_b32_e32 v30, s58
|
|
; SI-NEXT: v_mov_b32_e32 v29, s59
|
|
; SI-NEXT: v_mov_b32_e32 v28, s60
|
|
; SI-NEXT: v_mov_b32_e32 v27, s61
|
|
; SI-NEXT: v_mov_b32_e32 v26, s62
|
|
; SI-NEXT: v_mov_b32_e32 v25, s63
|
|
; SI-NEXT: v_mov_b32_e32 v16, s6
|
|
; SI-NEXT: v_mov_b32_e32 v17, s8
|
|
; SI-NEXT: v_mov_b32_e32 v18, s10
|
|
; SI-NEXT: v_mov_b32_e32 v19, s12
|
|
; SI-NEXT: v_mov_b32_e32 v20, s14
|
|
; SI-NEXT: v_mov_b32_e32 v21, s40
|
|
; SI-NEXT: v_mov_b32_e32 v22, s42
|
|
; SI-NEXT: v_mov_b32_e32 v23, s44
|
|
; SI-NEXT: .LBB37_5: ; %end
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v32
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v22
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v21
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v23
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v22
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v21
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v32i16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB37_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB37_4
|
|
; VI-NEXT: .LBB37_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; VI-NEXT: s_branch .LBB37_5
|
|
; VI-NEXT: .LBB37_3:
|
|
; VI-NEXT: s_branch .LBB37_2
|
|
; VI-NEXT: .LBB37_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB37_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v32i16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB37_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB37_4
|
|
; GFX9-NEXT: .LBB37_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; GFX9-NEXT: s_branch .LBB37_5
|
|
; GFX9-NEXT: .LBB37_3:
|
|
; GFX9-NEXT: s_branch .LBB37_2
|
|
; GFX9-NEXT: .LBB37_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB37_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v32i16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB37_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB37_4
|
|
; GFX11-NEXT: .LBB37_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f32_e64 v15, s27, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v14, s26, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB37_3:
|
|
; GFX11-NEXT: s_branch .LBB37_2
|
|
; GFX11-NEXT: .LBB37_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define <16 x float> @bitcast_v32i16_to_v16f32(<32 x i16> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v16f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v32, v15
|
|
; SI-NEXT: v_mov_b32_e32 v17, v14
|
|
; SI-NEXT: v_mov_b32_e32 v18, v13
|
|
; SI-NEXT: v_mov_b32_e32 v19, v12
|
|
; SI-NEXT: v_mov_b32_e32 v20, v11
|
|
; SI-NEXT: v_mov_b32_e32 v21, v10
|
|
; SI-NEXT: v_mov_b32_e32 v22, v9
|
|
; SI-NEXT: v_mov_b32_e32 v23, v8
|
|
; SI-NEXT: v_mov_b32_e32 v24, v7
|
|
; SI-NEXT: v_mov_b32_e32 v25, v6
|
|
; SI-NEXT: v_mov_b32_e32 v26, v5
|
|
; SI-NEXT: v_mov_b32_e32 v27, v4
|
|
; SI-NEXT: v_mov_b32_e32 v28, v3
|
|
; SI-NEXT: v_mov_b32_e32 v29, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB38_3
|
|
; SI-NEXT: ; %bb.1: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB38_4
|
|
; SI-NEXT: .LBB38_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB38_3: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v55
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v54
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v53
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v51
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v50
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v49
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v39
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v38
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v36
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v35
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v34
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v33
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB38_2
|
|
; SI-NEXT: .LBB38_4: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_or_b32_e32 v0, v55, v0
|
|
; SI-NEXT: s_mov_b32 s6, 0x30000
|
|
; SI-NEXT: v_or_b32_e32 v1, v54, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v53, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v52, v3
|
|
; SI-NEXT: v_or_b32_e32 v4, v51, v4
|
|
; SI-NEXT: v_or_b32_e32 v5, v50, v5
|
|
; SI-NEXT: v_or_b32_e32 v6, v49, v6
|
|
; SI-NEXT: v_or_b32_e32 v7, v48, v7
|
|
; SI-NEXT: v_or_b32_e32 v8, v39, v8
|
|
; SI-NEXT: v_or_b32_e32 v9, v38, v9
|
|
; SI-NEXT: v_or_b32_e32 v10, v37, v10
|
|
; SI-NEXT: v_or_b32_e32 v11, v36, v11
|
|
; SI-NEXT: v_or_b32_e32 v12, v35, v12
|
|
; SI-NEXT: v_or_b32_e32 v13, v34, v13
|
|
; SI-NEXT: v_or_b32_e32 v14, v33, v14
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v16f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB38_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v17, 3
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v15
|
|
; VI-NEXT: v_add_u16_sdwa v15, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v14
|
|
; VI-NEXT: v_add_u16_sdwa v14, v14, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v16, v14
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v13
|
|
; VI-NEXT: v_add_u16_sdwa v13, v13, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v16, v13
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v12
|
|
; VI-NEXT: v_add_u16_sdwa v12, v12, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v11
|
|
; VI-NEXT: v_add_u16_sdwa v11, v11, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v16, v11
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v10
|
|
; VI-NEXT: v_add_u16_sdwa v10, v10, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v16, v10
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v9
|
|
; VI-NEXT: v_add_u16_sdwa v9, v9, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v16, v9
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v8
|
|
; VI-NEXT: v_add_u16_sdwa v8, v8, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v16, v8
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v7
|
|
; VI-NEXT: v_add_u16_sdwa v7, v7, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v16, v7
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v6
|
|
; VI-NEXT: v_add_u16_sdwa v6, v6, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v16, v6
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v5
|
|
; VI-NEXT: v_add_u16_sdwa v5, v5, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v16, v5
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v4
|
|
; VI-NEXT: v_add_u16_sdwa v4, v4, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v3
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v3, v16, v3
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v2
|
|
; VI-NEXT: v_add_u16_sdwa v2, v2, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v16, v2
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v1
|
|
; VI-NEXT: v_add_u16_sdwa v1, v1, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v16, v0
|
|
; VI-NEXT: .LBB38_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v16f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB38_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB38_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v16f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB38_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: .LBB38_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define inreg <16 x float> @bitcast_v32i16_to_v16f32_scalar(<32 x i16> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v16f32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s36, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s37, 1
|
|
; SI-NEXT: v_writelane_b32 v16, s38, 2
|
|
; SI-NEXT: v_writelane_b32 v16, s39, 3
|
|
; SI-NEXT: v_writelane_b32 v16, s48, 4
|
|
; SI-NEXT: v_writelane_b32 v16, s49, 5
|
|
; SI-NEXT: v_writelane_b32 v16, s50, 6
|
|
; SI-NEXT: v_writelane_b32 v16, s51, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v0
|
|
; SI-NEXT: s_lshr_b32 s6, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s8, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s9, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s12, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB39_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s36, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s37, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s38, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s39, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s44, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s45, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s46, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s47, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 16
|
|
; SI-NEXT: s_or_b32 s48, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 16
|
|
; SI-NEXT: s_or_b32 s49, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s50, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s51, s4, s5
|
|
; SI-NEXT: s_cbranch_execnz .LBB39_3
|
|
; SI-NEXT: .LBB39_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s36, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s37, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s38, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s39, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s40, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s41, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s42, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s43, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s44, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s45, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s46, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s47, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s48, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_add_i32 s49, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s9, s9, 3
|
|
; SI-NEXT: s_add_i32 s50, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s51, s4, 0x30000
|
|
; SI-NEXT: .LBB39_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s39
|
|
; SI-NEXT: v_mov_b32_e32 v4, s40
|
|
; SI-NEXT: v_mov_b32_e32 v5, s41
|
|
; SI-NEXT: v_mov_b32_e32 v6, s42
|
|
; SI-NEXT: v_mov_b32_e32 v7, s43
|
|
; SI-NEXT: v_mov_b32_e32 v8, s44
|
|
; SI-NEXT: v_mov_b32_e32 v9, s45
|
|
; SI-NEXT: v_mov_b32_e32 v10, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s47
|
|
; SI-NEXT: v_mov_b32_e32 v12, s48
|
|
; SI-NEXT: v_mov_b32_e32 v13, s49
|
|
; SI-NEXT: v_mov_b32_e32 v14, s50
|
|
; SI-NEXT: v_mov_b32_e32 v15, s51
|
|
; SI-NEXT: v_readlane_b32 s51, v16, 7
|
|
; SI-NEXT: v_readlane_b32 s50, v16, 6
|
|
; SI-NEXT: v_readlane_b32 s49, v16, 5
|
|
; SI-NEXT: v_readlane_b32 s48, v16, 4
|
|
; SI-NEXT: v_readlane_b32 s39, v16, 3
|
|
; SI-NEXT: v_readlane_b32 s38, v16, 2
|
|
; SI-NEXT: v_readlane_b32 s37, v16, 1
|
|
; SI-NEXT: v_readlane_b32 s36, v16, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB39_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
|
|
; SI-NEXT: s_branch .LBB39_2
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v16f32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB39_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB39_3
|
|
; VI-NEXT: .LBB39_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s5, s6, 3
|
|
; VI-NEXT: s_and_b32 s4, s6, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s7, 3
|
|
; VI-NEXT: s_add_i32 s6, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s7, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s29, 3
|
|
; VI-NEXT: s_add_i32 s7, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s28, 3
|
|
; VI-NEXT: s_add_i32 s29, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s27, 3
|
|
; VI-NEXT: s_add_i32 s28, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s26, 3
|
|
; VI-NEXT: s_add_i32 s27, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s25, 3
|
|
; VI-NEXT: s_add_i32 s26, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s24, 3
|
|
; VI-NEXT: s_add_i32 s25, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s23, 3
|
|
; VI-NEXT: s_add_i32 s24, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s22, 3
|
|
; VI-NEXT: s_add_i32 s23, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s21, 3
|
|
; VI-NEXT: s_add_i32 s22, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s20, 3
|
|
; VI-NEXT: s_add_i32 s21, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s19, 3
|
|
; VI-NEXT: s_add_i32 s20, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s18, 3
|
|
; VI-NEXT: s_add_i32 s19, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s17, 3
|
|
; VI-NEXT: s_add_i32 s18, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s16, 3
|
|
; VI-NEXT: s_add_i32 s17, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s16, s4, 0x30000
|
|
; VI-NEXT: .LBB39_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB39_4:
|
|
; VI-NEXT: s_branch .LBB39_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v16f32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB39_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB39_4
|
|
; GFX9-NEXT: .LBB39_2: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, s31, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, s30, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB39_5
|
|
; GFX9-NEXT: .LBB39_3:
|
|
; GFX9-NEXT: s_branch .LBB39_2
|
|
; GFX9-NEXT: .LBB39_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB39_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v16f32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB39_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB39_4
|
|
; GFX11-NEXT: .LBB39_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB39_3:
|
|
; GFX11-NEXT: s_branch .LBB39_2
|
|
; GFX11-NEXT: .LBB39_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define <32 x half> @bitcast_v16f32_to_v32f16(<16 x float> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v32f16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB40_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB40_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB40_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB40_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v24
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v27
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v24
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v32f16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB40_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: .LBB40_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v32f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB40_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX9-NEXT: .LBB40_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v32f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB40_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
|
|
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
|
|
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
|
|
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
|
|
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
|
|
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
|
|
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
|
|
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
|
|
; GFX11-NEXT: .LBB40_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define inreg <32 x half> @bitcast_v16f32_to_v32f16_scalar(<16 x float> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v32f16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB41_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s63, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB41_4
|
|
; SI-NEXT: .LBB41_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e64 v15, s5, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v14, s4, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[16:17], v[14:15], 16
|
|
; SI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[17:18], v[12:13], 16
|
|
; SI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[18:19], v[10:11], 16
|
|
; SI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[19:20], v[8:9], 16
|
|
; SI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[20:21], v[6:7], 16
|
|
; SI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[21:22], v[4:5], 16
|
|
; SI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; SI-NEXT: v_lshr_b64 v[22:23], v[2:3], 16
|
|
; SI-NEXT: v_lshr_b64 v[23:24], v[0:1], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
|
|
; SI-NEXT: s_branch .LBB41_5
|
|
; SI-NEXT: .LBB41_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: s_branch .LBB41_2
|
|
; SI-NEXT: .LBB41_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: v_mov_b32_e32 v32, s56
|
|
; SI-NEXT: v_mov_b32_e32 v31, s57
|
|
; SI-NEXT: v_mov_b32_e32 v30, s58
|
|
; SI-NEXT: v_mov_b32_e32 v29, s59
|
|
; SI-NEXT: v_mov_b32_e32 v28, s60
|
|
; SI-NEXT: v_mov_b32_e32 v27, s61
|
|
; SI-NEXT: v_mov_b32_e32 v26, s62
|
|
; SI-NEXT: v_mov_b32_e32 v25, s63
|
|
; SI-NEXT: v_mov_b32_e32 v16, s6
|
|
; SI-NEXT: v_mov_b32_e32 v17, s8
|
|
; SI-NEXT: v_mov_b32_e32 v18, s10
|
|
; SI-NEXT: v_mov_b32_e32 v19, s12
|
|
; SI-NEXT: v_mov_b32_e32 v20, s14
|
|
; SI-NEXT: v_mov_b32_e32 v21, s40
|
|
; SI-NEXT: v_mov_b32_e32 v22, s42
|
|
; SI-NEXT: v_mov_b32_e32 v23, s44
|
|
; SI-NEXT: .LBB41_5: ; %end
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v32
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v22
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v21
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v23
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v22
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v21
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v32f16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB41_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB41_4
|
|
; VI-NEXT: .LBB41_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; VI-NEXT: s_branch .LBB41_5
|
|
; VI-NEXT: .LBB41_3:
|
|
; VI-NEXT: s_branch .LBB41_2
|
|
; VI-NEXT: .LBB41_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB41_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v32f16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB41_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB41_4
|
|
; GFX9-NEXT: .LBB41_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; GFX9-NEXT: s_branch .LBB41_5
|
|
; GFX9-NEXT: .LBB41_3:
|
|
; GFX9-NEXT: s_branch .LBB41_2
|
|
; GFX9-NEXT: .LBB41_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB41_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v32f16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB41_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB41_4
|
|
; GFX11-NEXT: .LBB41_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f32_e64 v15, s27, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v14, s26, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB41_3:
|
|
; GFX11-NEXT: s_branch .LBB41_2
|
|
; GFX11-NEXT: .LBB41_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define <16 x float> @bitcast_v32f16_to_v16f32(<32 x half> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v16f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v32, v15
|
|
; SI-NEXT: v_mov_b32_e32 v17, v14
|
|
; SI-NEXT: v_mov_b32_e32 v18, v13
|
|
; SI-NEXT: v_mov_b32_e32 v19, v12
|
|
; SI-NEXT: v_mov_b32_e32 v20, v11
|
|
; SI-NEXT: v_mov_b32_e32 v21, v10
|
|
; SI-NEXT: v_mov_b32_e32 v22, v9
|
|
; SI-NEXT: v_mov_b32_e32 v23, v8
|
|
; SI-NEXT: v_mov_b32_e32 v24, v7
|
|
; SI-NEXT: v_mov_b32_e32 v25, v6
|
|
; SI-NEXT: v_mov_b32_e32 v26, v5
|
|
; SI-NEXT: v_mov_b32_e32 v27, v4
|
|
; SI-NEXT: v_mov_b32_e32 v28, v3
|
|
; SI-NEXT: v_mov_b32_e32 v29, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v31
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB42_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: .LBB42_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB42_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v40
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v55
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v31
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v30
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v54
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v29
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v53
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v28
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v27
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v52
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v26
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v50
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v49
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v24
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v48
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v23
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v39
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v22
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v38
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v21
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_or_b32_e32 v9, v11, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v37
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v20
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v36
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v35
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v18
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_or_b32_e32 v12, v14, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v33
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v32
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; SI-NEXT: .LBB42_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v16f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB42_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x200
|
|
; VI-NEXT: v_add_f16_sdwa v17, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v13, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v12, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v11, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v10, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v9, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v8, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v7, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v6, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v5, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v4, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v3, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v1, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
|
|
; VI-NEXT: v_add_f16_sdwa v16, v0, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v17
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: .LBB42_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v16f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB42_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB42_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v16f32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB42_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: .LBB42_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define inreg <16 x float> @bitcast_v32f16_to_v16f32_scalar(<32 x half> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v16f32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v18, s36, 0
|
|
; SI-NEXT: v_writelane_b32 v18, s37, 1
|
|
; SI-NEXT: v_writelane_b32 v18, s38, 2
|
|
; SI-NEXT: v_writelane_b32 v18, s39, 3
|
|
; SI-NEXT: v_writelane_b32 v18, s48, 4
|
|
; SI-NEXT: v_writelane_b32 v18, s49, 5
|
|
; SI-NEXT: v_writelane_b32 v18, s50, 6
|
|
; SI-NEXT: v_writelane_b32 v18, s51, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v0
|
|
; SI-NEXT: s_lshr_b32 s9, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s12, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s6, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s8, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB43_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s36, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s37, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s38, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s39, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s44, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s45, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s46, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s12, 16
|
|
; SI-NEXT: s_or_b32 s47, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s48, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s9, 16
|
|
; SI-NEXT: s_or_b32 s49, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s8, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s50, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s51, s4, s5
|
|
; SI-NEXT: s_cbranch_execnz .LBB43_4
|
|
; SI-NEXT: .LBB43_2: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s63
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s62
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s17
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s61
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s18
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s60
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s19
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s59
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s21
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s57
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s22
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s56
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s23
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s24
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s14
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s25
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s26
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_or_b32_e32 v9, v11, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s27
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s11
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s28
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_or_b32_e32 v12, v14, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, s7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, s6
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; SI-NEXT: s_branch .LBB43_5
|
|
; SI-NEXT: .LBB43_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
|
|
; SI-NEXT: s_branch .LBB43_2
|
|
; SI-NEXT: .LBB43_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s39
|
|
; SI-NEXT: v_mov_b32_e32 v4, s40
|
|
; SI-NEXT: v_mov_b32_e32 v5, s41
|
|
; SI-NEXT: v_mov_b32_e32 v6, s42
|
|
; SI-NEXT: v_mov_b32_e32 v7, s43
|
|
; SI-NEXT: v_mov_b32_e32 v8, s44
|
|
; SI-NEXT: v_mov_b32_e32 v9, s45
|
|
; SI-NEXT: v_mov_b32_e32 v10, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s47
|
|
; SI-NEXT: v_mov_b32_e32 v12, s48
|
|
; SI-NEXT: v_mov_b32_e32 v13, s49
|
|
; SI-NEXT: v_mov_b32_e32 v14, s50
|
|
; SI-NEXT: v_mov_b32_e32 v15, s51
|
|
; SI-NEXT: .LBB43_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s51, v18, 7
|
|
; SI-NEXT: v_readlane_b32 s50, v18, 6
|
|
; SI-NEXT: v_readlane_b32 s49, v18, 5
|
|
; SI-NEXT: v_readlane_b32 s48, v18, 4
|
|
; SI-NEXT: v_readlane_b32 s39, v18, 3
|
|
; SI-NEXT: v_readlane_b32 s38, v18, 2
|
|
; SI-NEXT: v_readlane_b32 s37, v18, 1
|
|
; SI-NEXT: v_readlane_b32 s36, v18, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v16f32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v17, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v17, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB43_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB43_4
|
|
; VI-NEXT: .LBB43_2: ; %cmp.true
|
|
; VI-NEXT: s_lshr_b32 s4, s31, 16
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s31, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s30, 16
|
|
; VI-NEXT: v_or_b32_e32 v15, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s30, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s29, 16
|
|
; VI-NEXT: v_or_b32_e32 v14, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s29, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s28, 16
|
|
; VI-NEXT: v_or_b32_e32 v13, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s28, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s27, 16
|
|
; VI-NEXT: v_or_b32_e32 v12, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s27, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s26, 16
|
|
; VI-NEXT: v_or_b32_e32 v11, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s26, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s25, 16
|
|
; VI-NEXT: v_or_b32_e32 v10, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s25, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s24, 16
|
|
; VI-NEXT: v_or_b32_e32 v9, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s24, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s23, 16
|
|
; VI-NEXT: v_or_b32_e32 v8, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s23, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s22, 16
|
|
; VI-NEXT: v_or_b32_e32 v7, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s22, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s21, 16
|
|
; VI-NEXT: v_or_b32_e32 v6, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s21, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s20, 16
|
|
; VI-NEXT: v_or_b32_e32 v5, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s20, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s19, 16
|
|
; VI-NEXT: v_or_b32_e32 v4, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s19, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s18, 16
|
|
; VI-NEXT: v_or_b32_e32 v3, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s18, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s17, 16
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v16, s17, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s16, 16
|
|
; VI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; VI-NEXT: v_mov_b32_e32 v16, s4
|
|
; VI-NEXT: v_add_f16_sdwa v16, v16, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v0, s16, v0
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: s_branch .LBB43_5
|
|
; VI-NEXT: .LBB43_3:
|
|
; VI-NEXT: s_branch .LBB43_2
|
|
; VI-NEXT: .LBB43_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB43_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v17, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v17, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v16f32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB43_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB43_4
|
|
; GFX9-NEXT: .LBB43_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, s31, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, s30, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB43_5
|
|
; GFX9-NEXT: .LBB43_3:
|
|
; GFX9-NEXT: s_branch .LBB43_2
|
|
; GFX9-NEXT: .LBB43_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB43_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v16f32_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB43_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB43_4
|
|
; GFX11-NEXT: .LBB43_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB43_3:
|
|
; GFX11-NEXT: s_branch .LBB43_2
|
|
; GFX11-NEXT: .LBB43_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define <32 x bfloat> @bitcast_v16f32_to_v32bf16(<16 x float> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v32bf16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB44_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: .LBB44_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB44_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: .LBB44_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v36
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v35
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v28
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v24
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v22
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v18
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v32bf16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB44_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; VI-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; VI-NEXT: .LBB44_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v32bf16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB44_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0
|
|
; GFX9-NEXT: .LBB44_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v32bf16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB44_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_dual_add_f32 v15, 1.0, v15 :: v_dual_add_f32 v14, 1.0, v14
|
|
; GFX11-NEXT: v_dual_add_f32 v13, 1.0, v13 :: v_dual_add_f32 v12, 1.0, v12
|
|
; GFX11-NEXT: v_dual_add_f32 v11, 1.0, v11 :: v_dual_add_f32 v10, 1.0, v10
|
|
; GFX11-NEXT: v_dual_add_f32 v9, 1.0, v9 :: v_dual_add_f32 v8, 1.0, v8
|
|
; GFX11-NEXT: v_dual_add_f32 v7, 1.0, v7 :: v_dual_add_f32 v6, 1.0, v6
|
|
; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4
|
|
; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2
|
|
; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0
|
|
; GFX11-NEXT: .LBB44_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define inreg <32 x bfloat> @bitcast_v16f32_to_v32bf16_scalar(<16 x float> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v32bf16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB45_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s8, s6, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s9, s6, 16
|
|
; SI-NEXT: s_and_b32 s10, s7, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s7, 16
|
|
; SI-NEXT: s_and_b32 s12, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s29, 16
|
|
; SI-NEXT: s_and_b32 s14, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s28, 16
|
|
; SI-NEXT: s_and_b32 s40, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s41, s27, 16
|
|
; SI-NEXT: s_and_b32 s42, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s43, s26, 16
|
|
; SI-NEXT: s_and_b32 s44, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s45, s25, 16
|
|
; SI-NEXT: s_and_b32 s46, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s47, s24, 16
|
|
; SI-NEXT: s_and_b32 s56, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s57, s23, 16
|
|
; SI-NEXT: s_and_b32 s58, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s59, s22, 16
|
|
; SI-NEXT: s_and_b32 s60, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s61, s21, 16
|
|
; SI-NEXT: s_and_b32 s62, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s63, s20, 16
|
|
; SI-NEXT: s_and_b32 s72, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s73, s19, 16
|
|
; SI-NEXT: s_and_b32 s74, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s75, s18, 16
|
|
; SI-NEXT: s_and_b32 s76, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s77, s17, 16
|
|
; SI-NEXT: s_and_b32 s78, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s79, s16, 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB45_4
|
|
; SI-NEXT: .LBB45_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e64 v20, s21, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v18, s22, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v16, s23, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v14, s24, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v12, s25, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v8, s27, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v6, s28, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v4, s29, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v2, s7, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v0, s6, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v22, s20, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v24, s19, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v26, s18, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v28, s17, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v30, s16, 1.0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
|
|
; SI-NEXT: s_branch .LBB45_5
|
|
; SI-NEXT: .LBB45_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr79
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr43
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr41
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr15
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr13
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr11
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr9
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: s_branch .LBB45_2
|
|
; SI-NEXT: .LBB45_4:
|
|
; SI-NEXT: v_mov_b32_e32 v30, s79
|
|
; SI-NEXT: v_mov_b32_e32 v31, s78
|
|
; SI-NEXT: v_mov_b32_e32 v28, s77
|
|
; SI-NEXT: v_mov_b32_e32 v29, s76
|
|
; SI-NEXT: v_mov_b32_e32 v26, s75
|
|
; SI-NEXT: v_mov_b32_e32 v27, s74
|
|
; SI-NEXT: v_mov_b32_e32 v24, s73
|
|
; SI-NEXT: v_mov_b32_e32 v25, s72
|
|
; SI-NEXT: v_mov_b32_e32 v22, s63
|
|
; SI-NEXT: v_mov_b32_e32 v23, s62
|
|
; SI-NEXT: v_mov_b32_e32 v20, s61
|
|
; SI-NEXT: v_mov_b32_e32 v21, s60
|
|
; SI-NEXT: v_mov_b32_e32 v18, s59
|
|
; SI-NEXT: v_mov_b32_e32 v19, s58
|
|
; SI-NEXT: v_mov_b32_e32 v16, s57
|
|
; SI-NEXT: v_mov_b32_e32 v17, s56
|
|
; SI-NEXT: v_mov_b32_e32 v14, s47
|
|
; SI-NEXT: v_mov_b32_e32 v15, s46
|
|
; SI-NEXT: v_mov_b32_e32 v12, s45
|
|
; SI-NEXT: v_mov_b32_e32 v13, s44
|
|
; SI-NEXT: v_mov_b32_e32 v10, s43
|
|
; SI-NEXT: v_mov_b32_e32 v11, s42
|
|
; SI-NEXT: v_mov_b32_e32 v8, s41
|
|
; SI-NEXT: v_mov_b32_e32 v9, s40
|
|
; SI-NEXT: v_mov_b32_e32 v6, s15
|
|
; SI-NEXT: v_mov_b32_e32 v7, s14
|
|
; SI-NEXT: v_mov_b32_e32 v4, s13
|
|
; SI-NEXT: v_mov_b32_e32 v5, s12
|
|
; SI-NEXT: v_mov_b32_e32 v2, s11
|
|
; SI-NEXT: v_mov_b32_e32 v3, s10
|
|
; SI-NEXT: v_mov_b32_e32 v0, s9
|
|
; SI-NEXT: v_mov_b32_e32 v1, s8
|
|
; SI-NEXT: .LBB45_5: ; %end
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
|
|
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v0
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[30:31], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v2
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[28:29], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
|
|
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[26:27], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v4
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[24:25], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[22:23], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
|
|
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v6
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[20:21], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[18:19], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v8
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[16:17], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v9
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[14:15], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v10
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[12:13], 16
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[32:33], 16
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[34:35], 16
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[36:37], 16
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[38:39], 16
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[48:49], 16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[50:51], 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v32bf16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB45_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB45_4
|
|
; VI-NEXT: .LBB45_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; VI-NEXT: s_branch .LBB45_5
|
|
; VI-NEXT: .LBB45_3:
|
|
; VI-NEXT: s_branch .LBB45_2
|
|
; VI-NEXT: .LBB45_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB45_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v32bf16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB45_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB45_4
|
|
; GFX9-NEXT: .LBB45_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e64 v15, s31, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v14, s30, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v13, s29, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v12, s28, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v11, s27, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v10, s26, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v9, s25, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0
|
|
; GFX9-NEXT: s_branch .LBB45_5
|
|
; GFX9-NEXT: .LBB45_3:
|
|
; GFX9-NEXT: s_branch .LBB45_2
|
|
; GFX9-NEXT: .LBB45_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB45_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v32bf16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB45_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB45_4
|
|
; GFX11-NEXT: .LBB45_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f32_e64 v15, s27, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v14, s26, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v13, s25, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v12, s24, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v11, s23, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v10, s22, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v9, s21, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB45_3:
|
|
; GFX11-NEXT: s_branch .LBB45_2
|
|
; GFX11-NEXT: .LBB45_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define <16 x float> @bitcast_v32bf16_to_v16f32(<32 x bfloat> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v16f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_mul_f32_e32 v54, 1.0, v32
|
|
; SI-NEXT: v_mul_f32_e32 v55, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v52, 1.0, v31
|
|
; SI-NEXT: v_mul_f32_e32 v53, 1.0, v1
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v51, 1.0, v2
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v49, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v39, 1.0, v4
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
|
|
; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v35, 1.0, v6
|
|
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v8
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v23
|
|
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v10
|
|
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v23, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v19
|
|
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
|
|
; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB46_3
|
|
; SI-NEXT: ; %bb.1: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB46_4
|
|
; SI-NEXT: .LBB46_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB46_3: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v38
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v55, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v53, 16
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v51, 16
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v49, 16
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v39, 16
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v37, 16
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v35, 16
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v17, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB46_2
|
|
; SI-NEXT: .LBB46_4: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v50
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
|
|
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v38
|
|
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v36
|
|
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v34
|
|
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
|
|
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
|
|
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
|
|
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
|
|
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
|
|
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
|
|
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
|
|
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
|
|
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v16f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB46_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
|
|
; VI-NEXT: s_movk_i32 s6, 0x7fff
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v14
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v14
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_alignbit_b32 v14, v14, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_alignbit_b32 v13, v13, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v12
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v12, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v12
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v12
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_alignbit_b32 v12, v12, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_alignbit_b32 v11, v11, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v10
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v10, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v10
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v10
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_alignbit_b32 v10, v10, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v9
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_alignbit_b32 v9, v9, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v8
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v8
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_alignbit_b32 v8, v8, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v7
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_alignbit_b32 v7, v7, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v6
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v6
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v6
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_alignbit_b32 v6, v6, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v5
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_alignbit_b32 v5, v5, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v4, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v4
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_alignbit_b32 v4, v4, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v3
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_alignbit_b32 v3, v3, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v2
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_alignbit_b32 v2, v2, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v1
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_alignbit_b32 v1, v1, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
|
|
; VI-NEXT: .LBB46_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v16f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB46_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v15, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v15, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v15
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
|
|
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v14, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v14, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v13, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v12, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v12, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v12
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v11, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v10, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v10, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v10
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v10, v10, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v9, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v9
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v8, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v8, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v8
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v7, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v7
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v6, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v6
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v6, v6, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v5, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v4, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v4, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v4, v4, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v3, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v3, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v2, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v1, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v0, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v0, v0, v16, s7
|
|
; GFX9-NEXT: .LBB46_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v16f32:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v30, v14
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
|
|
; GFX11-TRUE16-NEXT: .LBB46_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB46_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v4, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.h
|
|
; GFX11-TRUE16-NEXT: .LBB46_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v16f32:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB46_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v23, v14, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v16, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v22, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v2, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v2, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v1, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v21, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
|
|
; GFX11-FAKE16-NEXT: .LBB46_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define inreg <16 x float> @bitcast_v32bf16_to_v16f32_scalar(<32 x bfloat> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v16f32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v0
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s5, s29, 16
|
|
; SI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s28, 16
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s9, s27, 16
|
|
; SI-NEXT: s_and_b32 s10, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s26, 16
|
|
; SI-NEXT: s_and_b32 s12, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s25, 16
|
|
; SI-NEXT: s_and_b32 s14, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s24, 16
|
|
; SI-NEXT: s_and_b32 s24, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_and_b32 s25, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: s_and_b32 s26, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s27, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s28, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: s_and_b32 s29, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s40, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s41, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s43, s42, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s42, 16
|
|
; SI-NEXT: s_and_b32 s45, s44, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s46, 0
|
|
; SI-NEXT: v_mul_f32_e64 v41, 1.0, s41
|
|
; SI-NEXT: v_mul_f32_e64 v52, 1.0, s16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v63, 1.0, s40
|
|
; SI-NEXT: v_mul_f32_e64 v48, 1.0, s17
|
|
; SI-NEXT: v_mul_f32_e64 v62, 1.0, s29
|
|
; SI-NEXT: v_mul_f32_e64 v61, 1.0, s28
|
|
; SI-NEXT: v_mul_f32_e64 v60, 1.0, s27
|
|
; SI-NEXT: v_mul_f32_e64 v59, 1.0, s26
|
|
; SI-NEXT: v_mul_f32_e64 v58, 1.0, s25
|
|
; SI-NEXT: v_mul_f32_e64 v57, 1.0, s24
|
|
; SI-NEXT: v_mul_f32_e64 v56, 1.0, s14
|
|
; SI-NEXT: v_mul_f32_e64 v47, 1.0, s12
|
|
; SI-NEXT: v_mul_f32_e64 v46, 1.0, s10
|
|
; SI-NEXT: v_mul_f32_e64 v45, 1.0, s8
|
|
; SI-NEXT: v_mul_f32_e64 v44, 1.0, s6
|
|
; SI-NEXT: v_mul_f32_e64 v43, 1.0, s4
|
|
; SI-NEXT: v_mul_f32_e64 v42, 1.0, s45
|
|
; SI-NEXT: v_mul_f32_e64 v16, 1.0, s43
|
|
; SI-NEXT: v_mul_f32_e64 v39, 1.0, s18
|
|
; SI-NEXT: v_mul_f32_e64 v54, 1.0, s19
|
|
; SI-NEXT: v_mul_f32_e64 v50, 1.0, s20
|
|
; SI-NEXT: v_mul_f32_e64 v37, 1.0, s21
|
|
; SI-NEXT: v_mul_f32_e64 v35, 1.0, s22
|
|
; SI-NEXT: v_mul_f32_e64 v33, 1.0, s23
|
|
; SI-NEXT: v_mul_f32_e64 v31, 1.0, s15
|
|
; SI-NEXT: v_mul_f32_e64 v29, 1.0, s13
|
|
; SI-NEXT: v_mul_f32_e64 v27, 1.0, s11
|
|
; SI-NEXT: v_mul_f32_e64 v25, 1.0, s9
|
|
; SI-NEXT: v_mul_f32_e64 v23, 1.0, s7
|
|
; SI-NEXT: v_mul_f32_e64 v21, 1.0, s5
|
|
; SI-NEXT: v_mul_f32_e64 v19, 1.0, s44
|
|
; SI-NEXT: v_mul_f32_e64 v17, 1.0, s42
|
|
; SI-NEXT: s_cbranch_scc0 .LBB47_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v63
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[52:53], 16
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v62
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[39:40], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v61
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[54:55], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v60
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[50:51], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v59
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[37:38], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v58
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[35:36], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v57
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[33:34], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v56
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[31:32], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v47
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[29:30], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v46
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[27:28], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v45
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[25:26], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v44
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[23:24], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v43
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[21:22], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v42
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[19:20], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v16
|
|
; SI-NEXT: v_mov_b32_e32 v20, v16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[17:18], 16
|
|
; SI-NEXT: v_mov_b32_e32 v16, v20
|
|
; SI-NEXT: s_cbranch_execnz .LBB47_3
|
|
; SI-NEXT: .LBB47_2: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v52
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v63
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v48
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v62
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v61
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v54
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v60
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v50
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v59
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v58
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v57
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v56
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v47
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v46
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v45
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v44
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v43
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v42
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
|
|
; SI-NEXT: .LBB47_3: ; %end
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB47_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_branch .LBB47_2
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v16f32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v20, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v20, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB47_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB47_4
|
|
; VI-NEXT: .LBB47_2: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
|
|
; VI-NEXT: s_lshl_b32 s4, s30, 16
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
|
|
; VI-NEXT: v_add_f32_e32 v1, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s28, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; VI-NEXT: v_add_f32_e32 v2, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[0:1]
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: s_and_b32 s5, s26, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s26, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s24, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s24, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s22, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s20, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s20, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s18, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s18, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s16, 16
|
|
; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s17, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s19, 16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v1, v5, s[4:5]
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
|
|
; VI-NEXT: s_lshl_b32 s6, s21, 16
|
|
; VI-NEXT: v_mov_b32_e32 v1, v17
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v5, v7, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v16
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v5, v5
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
|
|
; VI-NEXT: v_bfe_u32 v11, v5, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v5
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: s_lshl_b32 s6, s23, 16
|
|
; VI-NEXT: v_mov_b32_e32 v3, v17
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v7, v9, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v11, v13, vcc
|
|
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v7, v7
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
|
|
; VI-NEXT: s_lshl_b32 s6, s25, 16
|
|
; VI-NEXT: v_mov_b32_e32 v5, v17
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v9, v11, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v16
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v9, v9
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
|
|
; VI-NEXT: v_bfe_u32 v15, v9, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v9
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v7, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v15, v17, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s27, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v11, v13, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v11, v11
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v16
|
|
; VI-NEXT: v_mov_b32_e32 v9, v17
|
|
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: s_and_b32 s7, s31, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v13, v15, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v13, s7, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: s_lshl_b32 s6, s31, 16
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v11, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: s_lshl_b32 s4, s29, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
|
|
; VI-NEXT: v_add_f32_e32 v15, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[17:18]
|
|
; VI-NEXT: v_mov_b32_e32 v13, v15
|
|
; VI-NEXT: v_mov_b32_e32 v15, v16
|
|
; VI-NEXT: s_branch .LBB47_5
|
|
; VI-NEXT: .LBB47_3:
|
|
; VI-NEXT: s_branch .LBB47_2
|
|
; VI-NEXT: .LBB47_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB47_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v20, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v20, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v16f32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB47_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB47_4
|
|
; GFX9-NEXT: .LBB47_2: ; %cmp.true
|
|
; GFX9-NEXT: s_and_b32 s4, s31, 0xffff0000
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s31, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v3, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: s_lshl_b32 s4, s30, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v4, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, 0xffff
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v1, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v3
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s29, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s28, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s27, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s26, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s25, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s24, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s23, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s22, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s21, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s20, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s19, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s18, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v17, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s17, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v17, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: s_lshl_b32 s4, s16, 16
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v0, s4, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v0, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v0
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_and_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v16
|
|
; GFX9-NEXT: s_branch .LBB47_5
|
|
; GFX9-NEXT: .LBB47_3:
|
|
; GFX9-NEXT: s_branch .LBB47_2
|
|
; GFX9-NEXT: .LBB47_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB47_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v20, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v16f32_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB47_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB47_4
|
|
; GFX11-TRUE16-NEXT: .LBB47_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s27, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s26, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v7, v7, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v2, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v17 :: v_dual_add_nc_u32 v3, v3, v4
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s15, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s12, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v17, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v16, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v18, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v16, v20, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v18
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v16, v19, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s12, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v19 :: v_dual_add_nc_u32 v19, v21, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, v22, v17
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v20, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v21, v22, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v23, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v24, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v17.l
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB47_3:
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB47_2
|
|
; GFX11-TRUE16-NEXT: .LBB47_4:
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v16f32_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB47_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB47_4
|
|
; GFX11-FAKE16-NEXT: .LBB47_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s26, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s25, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_nc_u32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v8, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v6, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s17, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v6, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v7, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v17, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v19, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v18, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v6, v16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s15, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v17, v18 :: v_dual_add_nc_u32 v17, v19, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s12, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v24
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v21, v24, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v18, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v16, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v20, 16, v17
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB47_3:
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB47_2
|
|
; GFX11-FAKE16-NEXT: .LBB47_4:
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v64i8:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; kill: killed $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB48_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v17, v16, v15, 24
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v15, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v16, v15, 8
|
|
; SI-NEXT: v_alignbit_b32 v20, v14, v13, 24
|
|
; SI-NEXT: v_alignbit_b32 v21, v14, v13, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v14, v13, 8
|
|
; SI-NEXT: v_alignbit_b32 v23, v12, v11, 24
|
|
; SI-NEXT: v_alignbit_b32 v24, v12, v11, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v12, v11, 8
|
|
; SI-NEXT: v_alignbit_b32 v29, v10, v9, 24
|
|
; SI-NEXT: v_alignbit_b32 v30, v10, v9, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v10, v9, 8
|
|
; SI-NEXT: v_alignbit_b32 v35, v8, v7, 24
|
|
; SI-NEXT: v_alignbit_b32 v36, v8, v7, 16
|
|
; SI-NEXT: v_alignbit_b32 v37, v8, v7, 8
|
|
; SI-NEXT: v_alignbit_b32 v49, v6, v5, 24
|
|
; SI-NEXT: v_alignbit_b32 v50, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v52, v6, v5, 8
|
|
; SI-NEXT: v_alignbit_b32 v55, v4, v3, 24
|
|
; SI-NEXT: v_alignbit_b32 v41, v4, v3, 16
|
|
; SI-NEXT: v_alignbit_b32 v43, v4, v3, 8
|
|
; SI-NEXT: v_alignbit_b32 v46, v2, v1, 24
|
|
; SI-NEXT: v_alignbit_b32 v56, v2, v1, 16
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_alignbit_b32 v58, v2, v1, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v57, 8, v6
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v4
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v4
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v2
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
|
|
; SI-NEXT: .LBB48_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB48_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e32 v16, 1.0, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_alignbit_b32 v17, v16, v15, 24
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v15, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v16, v15, 8
|
|
; SI-NEXT: v_alignbit_b32 v20, v14, v13, 24
|
|
; SI-NEXT: v_alignbit_b32 v21, v14, v13, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v14, v13, 8
|
|
; SI-NEXT: v_alignbit_b32 v23, v12, v11, 24
|
|
; SI-NEXT: v_alignbit_b32 v24, v12, v11, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v12, v11, 8
|
|
; SI-NEXT: v_alignbit_b32 v29, v10, v9, 24
|
|
; SI-NEXT: v_alignbit_b32 v30, v10, v9, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v10, v9, 8
|
|
; SI-NEXT: v_alignbit_b32 v35, v8, v7, 24
|
|
; SI-NEXT: v_alignbit_b32 v36, v8, v7, 16
|
|
; SI-NEXT: v_alignbit_b32 v37, v8, v7, 8
|
|
; SI-NEXT: v_alignbit_b32 v49, v6, v5, 24
|
|
; SI-NEXT: v_alignbit_b32 v50, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v52, v6, v5, 8
|
|
; SI-NEXT: v_alignbit_b32 v55, v4, v3, 24
|
|
; SI-NEXT: v_alignbit_b32 v41, v4, v3, 16
|
|
; SI-NEXT: v_alignbit_b32 v43, v4, v3, 8
|
|
; SI-NEXT: v_alignbit_b32 v46, v2, v1, 24
|
|
; SI-NEXT: v_alignbit_b32 v56, v2, v1, 16
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_alignbit_b32 v58, v2, v1, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v57, 8, v6
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v4
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v4
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v2
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
|
|
; SI-NEXT: .LBB48_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v58
|
|
; SI-NEXT: v_and_b32_e32 v56, 0xff, v56
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v56
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v46
|
|
; SI-NEXT: v_or_b32_e32 v46, v46, v56
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v46
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v17
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v63
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v62
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v17, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v41
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v55
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v61
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v60
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v59
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v52
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v49
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v57
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v47
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v45
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v37
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v44
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v40
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v31
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v29
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v54
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v53
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v51
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v25
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v48
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v38
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v22
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v20
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v32
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v19
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v28
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v26
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v64i8:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB48_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: v_mov_b32_e32 v27, v21
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: .LBB48_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB48_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e32 v16, 1.0, v16
|
|
; VI-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; VI-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; VI-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; VI-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; VI-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; VI-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; VI-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; VI-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; VI-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; VI-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; VI-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; VI-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: .LBB48_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v21
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; VI-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
|
|
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
|
|
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
|
|
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v64i8:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB48_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v16
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, v22
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: .LBB48_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB48_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 1.0, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 1.0, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 1.0, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 1.0, v13
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 1.0, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 1.0, v11
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 1.0, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 1.0, v9
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: .LBB48_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v22, v30, v24, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v22, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v21, v62, v21, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v61, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v21, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v43, v23, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v54, v20, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v27, v25, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v16f32_to_v64i8:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB48_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB48_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v15, 1.0, v15
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v16, 1.0, v16 :: v_dual_add_f32 v7, 1.0, v7
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v13, 1.0, v13
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v9, 1.0, v9
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB48_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
|
|
; GFX11-TRUE16-NEXT: s_clause 0x3
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v16f32_to_v64i8:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB48_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB48_2: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB48_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v15, 1.0, v15
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v16, 1.0, v16 :: v_dual_add_f32 v7, 1.0, v7
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v10, 1.0, v10 :: v_dual_add_f32 v13, 1.0, v13
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v14, 1.0, v14 :: v_dual_add_f32 v9, 1.0, v9
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v12, 1.0, v12 :: v_dual_add_f32 v11, 1.0, v11
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB48_4: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
|
|
; GFX11-FAKE16-NEXT: s_clause 0x3
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v16f32_to_v64i8_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v40, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v40, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v40, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v40, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v40, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v40, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v40, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v40, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v40, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v40, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v40, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v40, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v40, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v40, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v40, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v40, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v40, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v40, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v40, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v40, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v40, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v40, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v40, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v40, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v40, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v40, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v40, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v40, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v40, s30, 28
|
|
; SI-NEXT: v_writelane_b32 v40, s31, 29
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s37, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s36, v1
|
|
; SI-NEXT: s_cbranch_scc0 .LBB49_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s82, s37, 24
|
|
; SI-NEXT: s_lshr_b32 s84, s37, 16
|
|
; SI-NEXT: s_lshr_b32 s85, s37, 8
|
|
; SI-NEXT: s_lshr_b32 s71, s29, 24
|
|
; SI-NEXT: s_lshr_b32 s81, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s83, s29, 8
|
|
; SI-NEXT: s_lshr_b32 s68, s27, 24
|
|
; SI-NEXT: s_lshr_b32 s70, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s80, s27, 8
|
|
; SI-NEXT: s_lshr_b32 s65, s25, 24
|
|
; SI-NEXT: s_lshr_b32 s67, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s69, s25, 8
|
|
; SI-NEXT: s_lshr_b32 s54, s23, 24
|
|
; SI-NEXT: s_lshr_b32 s64, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s66, s23, 8
|
|
; SI-NEXT: s_lshr_b32 s51, s21, 24
|
|
; SI-NEXT: s_lshr_b32 s53, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s55, s21, 8
|
|
; SI-NEXT: s_lshr_b32 s48, s19, 24
|
|
; SI-NEXT: s_lshr_b32 s50, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s52, s19, 8
|
|
; SI-NEXT: s_lshr_b32 s38, s17, 24
|
|
; SI-NEXT: s_lshr_b32 s39, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s49, s17, 8
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[36:37], 24
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[36:37], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[36:37], 8
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[28:29], 24
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[28:29], 8
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[24:25], 24
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 8
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[22:23], 8
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[20:21], 8
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[18:19], 24
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 8
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 8
|
|
; SI-NEXT: s_cbranch_execnz .LBB49_4
|
|
; SI-NEXT: .LBB49_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f32_e64 v20, s17, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v22, s16, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v16, s19, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v18, s18, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v11, s21, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v15, s20, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v9, s23, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v10, s22, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v7, s25, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v8, s24, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v5, s27, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v6, s26, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v3, s29, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v4, s28, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v1, s37, 1.0
|
|
; SI-NEXT: v_add_f32_e64 v2, s36, 1.0
|
|
; SI-NEXT: v_readfirstlane_b32 s16, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s17, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s18, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s19, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s20, v15
|
|
; SI-NEXT: v_readfirstlane_b32 s21, v11
|
|
; SI-NEXT: v_readfirstlane_b32 s22, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s23, v9
|
|
; SI-NEXT: v_readfirstlane_b32 s24, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s25, v7
|
|
; SI-NEXT: v_readfirstlane_b32 s26, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s27, v5
|
|
; SI-NEXT: v_readfirstlane_b32 s14, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s15, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v1
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], 24
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[8:9], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[8:9], 8
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[14:15], 24
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[14:15], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[14:15], 8
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[24:25], 24
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 8
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[22:23], 24
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[22:23], 8
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[20:21], 8
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[18:19], 24
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 8
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 24, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 8, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 24, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 8, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 24, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 8, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 8, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 24, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 8, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v20
|
|
; SI-NEXT: s_branch .LBB49_5
|
|
; SI-NEXT: .LBB49_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr49
|
|
; SI-NEXT: ; implicit-def: $sgpr39
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr90
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: ; implicit-def: $sgpr52
|
|
; SI-NEXT: ; implicit-def: $sgpr50
|
|
; SI-NEXT: ; implicit-def: $sgpr48
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr55
|
|
; SI-NEXT: ; implicit-def: $sgpr53
|
|
; SI-NEXT: ; implicit-def: $sgpr51
|
|
; SI-NEXT: ; implicit-def: $sgpr66
|
|
; SI-NEXT: ; implicit-def: $sgpr64
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr69
|
|
; SI-NEXT: ; implicit-def: $sgpr67
|
|
; SI-NEXT: ; implicit-def: $sgpr65
|
|
; SI-NEXT: ; implicit-def: $sgpr80
|
|
; SI-NEXT: ; implicit-def: $sgpr70
|
|
; SI-NEXT: ; implicit-def: $sgpr68
|
|
; SI-NEXT: ; implicit-def: $sgpr83
|
|
; SI-NEXT: ; implicit-def: $sgpr81
|
|
; SI-NEXT: ; implicit-def: $sgpr71
|
|
; SI-NEXT: ; implicit-def: $sgpr85
|
|
; SI-NEXT: ; implicit-def: $sgpr84
|
|
; SI-NEXT: ; implicit-def: $sgpr82
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: s_branch .LBB49_2
|
|
; SI-NEXT: .LBB49_4:
|
|
; SI-NEXT: v_mov_b32_e32 v22, s16
|
|
; SI-NEXT: v_mov_b32_e32 v20, s17
|
|
; SI-NEXT: v_mov_b32_e32 v18, s18
|
|
; SI-NEXT: v_mov_b32_e32 v16, s19
|
|
; SI-NEXT: v_mov_b32_e32 v15, s20
|
|
; SI-NEXT: v_mov_b32_e32 v11, s21
|
|
; SI-NEXT: v_mov_b32_e32 v10, s22
|
|
; SI-NEXT: v_mov_b32_e32 v9, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v7, s25
|
|
; SI-NEXT: v_mov_b32_e32 v6, s26
|
|
; SI-NEXT: v_mov_b32_e32 v5, s27
|
|
; SI-NEXT: v_mov_b32_e32 v4, s28
|
|
; SI-NEXT: v_mov_b32_e32 v3, s29
|
|
; SI-NEXT: v_mov_b32_e32 v2, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v48, s49
|
|
; SI-NEXT: v_mov_b32_e32 v39, s39
|
|
; SI-NEXT: v_mov_b32_e32 v38, s38
|
|
; SI-NEXT: v_mov_b32_e32 v37, s52
|
|
; SI-NEXT: v_mov_b32_e32 v36, s50
|
|
; SI-NEXT: v_mov_b32_e32 v35, s48
|
|
; SI-NEXT: v_mov_b32_e32 v34, s55
|
|
; SI-NEXT: v_mov_b32_e32 v33, s53
|
|
; SI-NEXT: v_mov_b32_e32 v32, s51
|
|
; SI-NEXT: v_mov_b32_e32 v31, s66
|
|
; SI-NEXT: v_mov_b32_e32 v30, s64
|
|
; SI-NEXT: v_mov_b32_e32 v29, s54
|
|
; SI-NEXT: v_mov_b32_e32 v28, s69
|
|
; SI-NEXT: v_mov_b32_e32 v27, s67
|
|
; SI-NEXT: v_mov_b32_e32 v26, s65
|
|
; SI-NEXT: v_mov_b32_e32 v25, s80
|
|
; SI-NEXT: v_mov_b32_e32 v24, s70
|
|
; SI-NEXT: v_mov_b32_e32 v23, s68
|
|
; SI-NEXT: v_mov_b32_e32 v21, s83
|
|
; SI-NEXT: v_mov_b32_e32 v19, s81
|
|
; SI-NEXT: v_mov_b32_e32 v17, s71
|
|
; SI-NEXT: v_mov_b32_e32 v14, s85
|
|
; SI-NEXT: v_mov_b32_e32 v13, s84
|
|
; SI-NEXT: v_mov_b32_e32 v12, s82
|
|
; SI-NEXT: .LBB49_5: ; %end
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; SI-NEXT: s_lshl_b32 s5, s34, 8
|
|
; SI-NEXT: v_or_b32_e32 v22, s5, v22
|
|
; SI-NEXT: s_and_b32 s5, s30, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s94, 24
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
|
|
; SI-NEXT: s_or_b32 s5, s7, s5
|
|
; SI-NEXT: v_or_b32_e32 v22, s5, v22
|
|
; SI-NEXT: buffer_store_dword v22, v0, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xff, v20
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v48
|
|
; SI-NEXT: v_or_b32_e32 v20, v20, v22
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xff, v39
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xff, v18
|
|
; SI-NEXT: s_lshl_b32 s5, s92, 8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 24, v38
|
|
; SI-NEXT: v_or_b32_e32 v18, s5, v18
|
|
; SI-NEXT: s_and_b32 s5, s90, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
|
|
; SI-NEXT: v_or_b32_e32 v22, v38, v22
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s88, 24
|
|
; SI-NEXT: v_or_b32_e32 v20, v20, v22
|
|
; SI-NEXT: v_add_i32_e32 v22, vcc, 4, v0
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff, v18
|
|
; SI-NEXT: s_or_b32 s5, s7, s5
|
|
; SI-NEXT: buffer_store_dword v20, v22, s[0:3], 0 offen
|
|
; SI-NEXT: v_or_b32_e32 v18, s5, v18
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v20, vcc, 8, v0
|
|
; SI-NEXT: buffer_store_dword v18, v20, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v37
|
|
; SI-NEXT: v_or_b32_e32 v16, v16, v18
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xff, v36
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: s_lshl_b32 s5, s74, 8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v35
|
|
; SI-NEXT: v_or_b32_e32 v15, s5, v15
|
|
; SI-NEXT: s_and_b32 s5, s62, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
|
|
; SI-NEXT: v_or_b32_e32 v18, v20, v18
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s60, 24
|
|
; SI-NEXT: v_or_b32_e32 v16, v16, v18
|
|
; SI-NEXT: v_add_i32_e32 v18, vcc, 12, v0
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_or_b32 s5, s7, s5
|
|
; SI-NEXT: buffer_store_dword v16, v18, s[0:3], 0 offen
|
|
; SI-NEXT: v_or_b32_e32 v15, s5, v15
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 16, v0
|
|
; SI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v34
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v33
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: s_lshl_b32 s5, s78, 8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v32
|
|
; SI-NEXT: v_or_b32_e32 v10, s5, v10
|
|
; SI-NEXT: s_and_b32 s5, s76, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s72, 24
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v15
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 20, v0
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: s_or_b32 s5, s7, s5
|
|
; SI-NEXT: buffer_store_dword v11, v15, s[0:3], 0 offen
|
|
; SI-NEXT: v_or_b32_e32 v10, s5, v10
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 24, v0
|
|
; SI-NEXT: buffer_store_dword v10, v11, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v31
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v30
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v29
|
|
; SI-NEXT: v_or_b32_e32 v8, s5, v8
|
|
; SI-NEXT: s_and_b32 s5, s56, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s46, 24
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 28, v0
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: s_or_b32 s5, s7, s5
|
|
; SI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
|
|
; SI-NEXT: v_or_b32_e32 v8, s5, v8
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 32, v0
|
|
; SI-NEXT: buffer_store_dword v8, v9, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v28
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v27
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: s_lshl_b32 s5, s44, 8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v26
|
|
; SI-NEXT: v_or_b32_e32 v6, s5, v6
|
|
; SI-NEXT: s_and_b32 s5, s42, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s40, 24
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 36, v0
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: s_or_b32 s5, s7, s5
|
|
; SI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
|
|
; SI-NEXT: v_or_b32_e32 v6, s5, v6
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 40, v0
|
|
; SI-NEXT: buffer_store_dword v6, v7, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v24
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 24, v23
|
|
; SI-NEXT: v_or_b32_e32 v4, s5, v4
|
|
; SI-NEXT: s_and_b32 s5, s12, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s10, 24
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 44, v0
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: s_or_b32 s5, s7, s5
|
|
; SI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
|
|
; SI-NEXT: v_or_b32_e32 v4, s5, v4
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 48, v0
|
|
; SI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v21
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v19
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v17
|
|
; SI-NEXT: v_or_b32_e32 v2, s5, v2
|
|
; SI-NEXT: s_and_b32 s5, s6, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 24
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 52, v0
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
|
|
; SI-NEXT: v_or_b32_e32 v2, s4, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 56, v0
|
|
; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v14
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v12
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: v_readlane_b32 s30, v40, 28
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: v_readlane_b32 s31, v40, 29
|
|
; SI-NEXT: v_readlane_b32 s85, v40, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v40, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v40, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v40, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v40, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v40, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v40, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v40, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v40, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v40, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v40, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v40, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v40, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v40, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v40, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v40, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v40, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v40, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v40, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v40, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v40, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v40, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v40, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v40, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v40, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v40, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v40, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v40, 0
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v16f32_to_v64i8_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_writelane_b32 v63, s34, 0
|
|
; VI-NEXT: v_writelane_b32 v63, s35, 1
|
|
; VI-NEXT: v_writelane_b32 v63, s36, 2
|
|
; VI-NEXT: v_writelane_b32 v63, s37, 3
|
|
; VI-NEXT: v_writelane_b32 v63, s38, 4
|
|
; VI-NEXT: v_writelane_b32 v63, s39, 5
|
|
; VI-NEXT: v_writelane_b32 v63, s48, 6
|
|
; VI-NEXT: v_writelane_b32 v63, s49, 7
|
|
; VI-NEXT: v_writelane_b32 v63, s50, 8
|
|
; VI-NEXT: v_writelane_b32 v63, s51, 9
|
|
; VI-NEXT: v_writelane_b32 v63, s52, 10
|
|
; VI-NEXT: v_writelane_b32 v63, s53, 11
|
|
; VI-NEXT: v_writelane_b32 v63, s54, 12
|
|
; VI-NEXT: v_writelane_b32 v63, s55, 13
|
|
; VI-NEXT: v_writelane_b32 v63, s64, 14
|
|
; VI-NEXT: v_writelane_b32 v63, s65, 15
|
|
; VI-NEXT: v_writelane_b32 v63, s66, 16
|
|
; VI-NEXT: v_writelane_b32 v63, s67, 17
|
|
; VI-NEXT: v_writelane_b32 v63, s30, 18
|
|
; VI-NEXT: v_writelane_b32 v63, s31, 19
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; VI-NEXT: s_cbranch_scc0 .LBB49_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_lshr_b32 s56, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s59, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s58, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s60, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s61, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s72, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s63, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s74, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s75, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s77, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s76, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s78, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s79, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s90, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s89, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s91, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s31, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s35, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s34, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s36, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s48, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s39, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s49, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s50, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s51, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s53, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s52, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s54, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s66, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s65, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 8
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; VI-NEXT: s_cbranch_execnz .LBB49_4
|
|
; VI-NEXT: .LBB49_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f32_e64 v6, s27, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v5, s26, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v2, s5, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v1, s4, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v8, s25, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v7, s24, 1.0
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
|
|
; VI-NEXT: v_add_f32_e64 v10, s23, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v9, s22, 1.0
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
|
|
; VI-NEXT: v_add_f32_e64 v12, s21, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v11, s20, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v4, s29, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v3, s28, 1.0
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[9:10]
|
|
; VI-NEXT: v_add_f32_e64 v14, s19, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v13, s18, 1.0
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[11:12]
|
|
; VI-NEXT: v_add_f32_e64 v16, s17, 1.0
|
|
; VI-NEXT: v_add_f32_e64 v15, s16, 1.0
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v26, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v25, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 16, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v15
|
|
; VI-NEXT: s_branch .LBB49_5
|
|
; VI-NEXT: .LBB49_3:
|
|
; VI-NEXT: ; implicit-def: $sgpr67
|
|
; VI-NEXT: ; implicit-def: $sgpr65
|
|
; VI-NEXT: ; implicit-def: $sgpr6
|
|
; VI-NEXT: ; implicit-def: $sgpr66
|
|
; VI-NEXT: ; implicit-def: $sgpr64
|
|
; VI-NEXT: ; implicit-def: $sgpr55
|
|
; VI-NEXT: ; implicit-def: $sgpr54
|
|
; VI-NEXT: ; implicit-def: $sgpr52
|
|
; VI-NEXT: ; implicit-def: $sgpr8
|
|
; VI-NEXT: ; implicit-def: $sgpr53
|
|
; VI-NEXT: ; implicit-def: $sgpr51
|
|
; VI-NEXT: ; implicit-def: $sgpr50
|
|
; VI-NEXT: ; implicit-def: $sgpr49
|
|
; VI-NEXT: ; implicit-def: $sgpr39
|
|
; VI-NEXT: ; implicit-def: $sgpr10
|
|
; VI-NEXT: ; implicit-def: $sgpr48
|
|
; VI-NEXT: ; implicit-def: $sgpr38
|
|
; VI-NEXT: ; implicit-def: $sgpr37
|
|
; VI-NEXT: ; implicit-def: $sgpr36
|
|
; VI-NEXT: ; implicit-def: $sgpr34
|
|
; VI-NEXT: ; implicit-def: $sgpr12
|
|
; VI-NEXT: ; implicit-def: $sgpr35
|
|
; VI-NEXT: ; implicit-def: $sgpr31
|
|
; VI-NEXT: ; implicit-def: $sgpr30
|
|
; VI-NEXT: ; implicit-def: $sgpr91
|
|
; VI-NEXT: ; implicit-def: $sgpr89
|
|
; VI-NEXT: ; implicit-def: $sgpr14
|
|
; VI-NEXT: ; implicit-def: $sgpr90
|
|
; VI-NEXT: ; implicit-def: $sgpr88
|
|
; VI-NEXT: ; implicit-def: $sgpr79
|
|
; VI-NEXT: ; implicit-def: $sgpr78
|
|
; VI-NEXT: ; implicit-def: $sgpr76
|
|
; VI-NEXT: ; implicit-def: $sgpr40
|
|
; VI-NEXT: ; implicit-def: $sgpr77
|
|
; VI-NEXT: ; implicit-def: $sgpr75
|
|
; VI-NEXT: ; implicit-def: $sgpr74
|
|
; VI-NEXT: ; implicit-def: $sgpr73
|
|
; VI-NEXT: ; implicit-def: $sgpr63
|
|
; VI-NEXT: ; implicit-def: $sgpr42
|
|
; VI-NEXT: ; implicit-def: $sgpr72
|
|
; VI-NEXT: ; implicit-def: $sgpr62
|
|
; VI-NEXT: ; implicit-def: $sgpr61
|
|
; VI-NEXT: ; implicit-def: $sgpr60
|
|
; VI-NEXT: ; implicit-def: $sgpr58
|
|
; VI-NEXT: ; implicit-def: $sgpr44
|
|
; VI-NEXT: ; implicit-def: $sgpr59
|
|
; VI-NEXT: ; implicit-def: $sgpr57
|
|
; VI-NEXT: ; implicit-def: $sgpr56
|
|
; VI-NEXT: s_branch .LBB49_2
|
|
; VI-NEXT: .LBB49_4:
|
|
; VI-NEXT: v_mov_b32_e32 v19, s44
|
|
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v19, s42
|
|
; VI-NEXT: v_mov_b32_e32 v15, s16
|
|
; VI-NEXT: v_mov_b32_e32 v16, s17
|
|
; VI-NEXT: v_mov_b32_e32 v13, s18
|
|
; VI-NEXT: v_mov_b32_e32 v14, s19
|
|
; VI-NEXT: v_mov_b32_e32 v11, s20
|
|
; VI-NEXT: v_mov_b32_e32 v12, s21
|
|
; VI-NEXT: v_mov_b32_e32 v9, s22
|
|
; VI-NEXT: v_mov_b32_e32 v10, s23
|
|
; VI-NEXT: v_mov_b32_e32 v7, s24
|
|
; VI-NEXT: v_mov_b32_e32 v8, s25
|
|
; VI-NEXT: v_mov_b32_e32 v5, s26
|
|
; VI-NEXT: v_mov_b32_e32 v6, s27
|
|
; VI-NEXT: v_mov_b32_e32 v3, s28
|
|
; VI-NEXT: v_mov_b32_e32 v4, s29
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_mov_b32_e32 v2, s5
|
|
; VI-NEXT: v_mov_b32_e32 v17, s67
|
|
; VI-NEXT: v_mov_b32_e32 v18, s65
|
|
; VI-NEXT: v_mov_b32_e32 v62, s66
|
|
; VI-NEXT: v_mov_b32_e32 v60, s64
|
|
; VI-NEXT: v_mov_b32_e32 v61, s55
|
|
; VI-NEXT: v_mov_b32_e32 v58, s54
|
|
; VI-NEXT: v_mov_b32_e32 v59, s52
|
|
; VI-NEXT: v_mov_b32_e32 v57, s53
|
|
; VI-NEXT: v_mov_b32_e32 v47, s51
|
|
; VI-NEXT: v_mov_b32_e32 v56, s50
|
|
; VI-NEXT: v_mov_b32_e32 v46, s49
|
|
; VI-NEXT: v_mov_b32_e32 v45, s39
|
|
; VI-NEXT: v_mov_b32_e32 v44, s48
|
|
; VI-NEXT: v_mov_b32_e32 v42, s38
|
|
; VI-NEXT: v_mov_b32_e32 v43, s37
|
|
; VI-NEXT: v_mov_b32_e32 v41, s36
|
|
; VI-NEXT: v_mov_b32_e32 v40, s34
|
|
; VI-NEXT: v_mov_b32_e32 v55, s35
|
|
; VI-NEXT: v_mov_b32_e32 v53, s31
|
|
; VI-NEXT: v_mov_b32_e32 v54, s30
|
|
; VI-NEXT: v_mov_b32_e32 v52, s91
|
|
; VI-NEXT: v_mov_b32_e32 v51, s89
|
|
; VI-NEXT: v_mov_b32_e32 v50, s90
|
|
; VI-NEXT: v_mov_b32_e32 v48, s88
|
|
; VI-NEXT: v_mov_b32_e32 v49, s79
|
|
; VI-NEXT: v_mov_b32_e32 v39, s78
|
|
; VI-NEXT: v_mov_b32_e32 v38, s76
|
|
; VI-NEXT: v_mov_b32_e32 v37, s77
|
|
; VI-NEXT: v_mov_b32_e32 v35, s75
|
|
; VI-NEXT: v_mov_b32_e32 v36, s74
|
|
; VI-NEXT: v_mov_b32_e32 v34, s73
|
|
; VI-NEXT: v_mov_b32_e32 v33, s63
|
|
; VI-NEXT: v_mov_b32_e32 v32, s72
|
|
; VI-NEXT: v_mov_b32_e32 v30, s62
|
|
; VI-NEXT: v_mov_b32_e32 v31, s61
|
|
; VI-NEXT: v_mov_b32_e32 v29, s60
|
|
; VI-NEXT: v_mov_b32_e32 v28, s58
|
|
; VI-NEXT: v_mov_b32_e32 v27, s59
|
|
; VI-NEXT: v_mov_b32_e32 v25, s57
|
|
; VI-NEXT: v_mov_b32_e32 v26, s56
|
|
; VI-NEXT: v_mov_b32_e32 v21, s12
|
|
; VI-NEXT: v_mov_b32_e32 v22, s10
|
|
; VI-NEXT: v_mov_b32_e32 v23, s8
|
|
; VI-NEXT: v_mov_b32_e32 v24, s6
|
|
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v19, s40
|
|
; VI-NEXT: v_mov_b32_e32 v20, s14
|
|
; VI-NEXT: .LBB49_5: ; %end
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v18, v18, v24, s4
|
|
; VI-NEXT: v_perm_b32 v15, v15, v17, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v17
|
|
; VI-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v15, v60, v61, s4
|
|
; VI-NEXT: v_perm_b32 v16, v16, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v15, v59, v23, s4
|
|
; VI-NEXT: v_perm_b32 v13, v13, v58, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v15
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v13, v14, v57, s4
|
|
; VI-NEXT: v_perm_b32 v14, v47, v56, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v13, v45, v22, s4
|
|
; VI-NEXT: v_perm_b32 v11, v11, v46, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v13
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v11, v12, v44, s4
|
|
; VI-NEXT: v_perm_b32 v12, v42, v43, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v11, v40, v21, s4
|
|
; VI-NEXT: v_perm_b32 v9, v9, v41, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v11
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v9, v10, v55, s4
|
|
; VI-NEXT: v_perm_b32 v10, v53, v54, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v9, v51, v20, s4
|
|
; VI-NEXT: v_perm_b32 v7, v7, v52, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v9
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v7, v8, v50, s4
|
|
; VI-NEXT: v_perm_b32 v8, v48, v49, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v7, v38, v19, s4
|
|
; VI-NEXT: v_perm_b32 v5, v5, v39, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v5, v6, v37, s4
|
|
; VI-NEXT: v_perm_b32 v6, v35, v36, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v3, v3, v34, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v29, s4
|
|
; VI-NEXT: v_readlane_b32 s30, v63, 18
|
|
; VI-NEXT: v_readlane_b32 s31, v63, 19
|
|
; VI-NEXT: v_readlane_b32 s67, v63, 17
|
|
; VI-NEXT: v_readlane_b32 s66, v63, 16
|
|
; VI-NEXT: v_readlane_b32 s65, v63, 15
|
|
; VI-NEXT: v_readlane_b32 s64, v63, 14
|
|
; VI-NEXT: v_readlane_b32 s55, v63, 13
|
|
; VI-NEXT: v_readlane_b32 s54, v63, 12
|
|
; VI-NEXT: v_readlane_b32 s53, v63, 11
|
|
; VI-NEXT: v_readlane_b32 s52, v63, 10
|
|
; VI-NEXT: v_readlane_b32 s51, v63, 9
|
|
; VI-NEXT: v_readlane_b32 s50, v63, 8
|
|
; VI-NEXT: v_readlane_b32 s49, v63, 7
|
|
; VI-NEXT: v_readlane_b32 s48, v63, 6
|
|
; VI-NEXT: v_readlane_b32 s39, v63, 5
|
|
; VI-NEXT: v_readlane_b32 s38, v63, 4
|
|
; VI-NEXT: v_readlane_b32 s37, v63, 3
|
|
; VI-NEXT: v_readlane_b32 s36, v63, 2
|
|
; VI-NEXT: v_readlane_b32 s35, v63, 1
|
|
; VI-NEXT: v_readlane_b32 s34, v63, 0
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v5, v33, v5, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v3, v4, v32, s4
|
|
; VI-NEXT: v_perm_b32 v4, v30, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v3, v28, v3, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v2, v27, s4
|
|
; VI-NEXT: v_perm_b32 v2, v25, v26, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v16f32_to_v64i8_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
|
|
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
|
|
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
|
|
; GFX9-NEXT: v_writelane_b32 v63, s37, 3
|
|
; GFX9-NEXT: v_writelane_b32 v63, s38, 4
|
|
; GFX9-NEXT: v_writelane_b32 v63, s39, 5
|
|
; GFX9-NEXT: v_writelane_b32 v63, s48, 6
|
|
; GFX9-NEXT: v_writelane_b32 v63, s49, 7
|
|
; GFX9-NEXT: v_writelane_b32 v63, s50, 8
|
|
; GFX9-NEXT: v_writelane_b32 v63, s51, 9
|
|
; GFX9-NEXT: v_writelane_b32 v63, s52, 10
|
|
; GFX9-NEXT: v_writelane_b32 v63, s53, 11
|
|
; GFX9-NEXT: v_writelane_b32 v63, s54, 12
|
|
; GFX9-NEXT: v_writelane_b32 v63, s55, 13
|
|
; GFX9-NEXT: v_writelane_b32 v63, s30, 14
|
|
; GFX9-NEXT: v_writelane_b32 v63, s31, 15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB49_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s57, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s59, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s58, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s60, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s61, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s62, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s72, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s63, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s74, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s75, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s77, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s76, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s78, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s79, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s88, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s90, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s89, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s91, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s92, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s93, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s95, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s94, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s30, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s36, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s35, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s37, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s38, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s39, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s49, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s48, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s50, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s52, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s54, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s53, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB49_4
|
|
; GFX9-NEXT: .LBB49_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f32_e64 v6, s27, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v5, s26, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v2, s5, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v1, s4, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v8, s25, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v7, s24, 1.0
|
|
; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
|
|
; GFX9-NEXT: v_add_f32_e64 v10, s23, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v9, s22, 1.0
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX9-NEXT: v_add_f32_e64 v12, s21, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v11, s20, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v4, s29, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v3, s28, 1.0
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; GFX9-NEXT: v_add_f32_e64 v14, s19, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v13, s18, 1.0
|
|
; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
|
|
; GFX9-NEXT: v_add_f32_e64 v19, s17, 1.0
|
|
; GFX9-NEXT: v_add_f32_e64 v18, s16, 1.0
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[25:26], 24, v[18:19]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v18
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v18
|
|
; GFX9-NEXT: s_branch .LBB49_5
|
|
; GFX9-NEXT: .LBB49_3:
|
|
; GFX9-NEXT: ; implicit-def: $sgpr55
|
|
; GFX9-NEXT: ; implicit-def: $sgpr53
|
|
; GFX9-NEXT: ; implicit-def: $sgpr6
|
|
; GFX9-NEXT: ; implicit-def: $sgpr54
|
|
; GFX9-NEXT: ; implicit-def: $sgpr52
|
|
; GFX9-NEXT: ; implicit-def: $sgpr51
|
|
; GFX9-NEXT: ; implicit-def: $sgpr50
|
|
; GFX9-NEXT: ; implicit-def: $sgpr48
|
|
; GFX9-NEXT: ; implicit-def: $sgpr8
|
|
; GFX9-NEXT: ; implicit-def: $sgpr49
|
|
; GFX9-NEXT: ; implicit-def: $sgpr39
|
|
; GFX9-NEXT: ; implicit-def: $sgpr38
|
|
; GFX9-NEXT: ; implicit-def: $sgpr37
|
|
; GFX9-NEXT: ; implicit-def: $sgpr35
|
|
; GFX9-NEXT: ; implicit-def: $sgpr10
|
|
; GFX9-NEXT: ; implicit-def: $sgpr36
|
|
; GFX9-NEXT: ; implicit-def: $sgpr34
|
|
; GFX9-NEXT: ; implicit-def: $sgpr31
|
|
; GFX9-NEXT: ; implicit-def: $sgpr30
|
|
; GFX9-NEXT: ; implicit-def: $sgpr94
|
|
; GFX9-NEXT: ; implicit-def: $sgpr12
|
|
; GFX9-NEXT: ; implicit-def: $sgpr95
|
|
; GFX9-NEXT: ; implicit-def: $sgpr93
|
|
; GFX9-NEXT: ; implicit-def: $sgpr92
|
|
; GFX9-NEXT: ; implicit-def: $sgpr91
|
|
; GFX9-NEXT: ; implicit-def: $sgpr89
|
|
; GFX9-NEXT: ; implicit-def: $sgpr14
|
|
; GFX9-NEXT: ; implicit-def: $sgpr90
|
|
; GFX9-NEXT: ; implicit-def: $sgpr88
|
|
; GFX9-NEXT: ; implicit-def: $sgpr79
|
|
; GFX9-NEXT: ; implicit-def: $sgpr78
|
|
; GFX9-NEXT: ; implicit-def: $sgpr76
|
|
; GFX9-NEXT: ; implicit-def: $sgpr40
|
|
; GFX9-NEXT: ; implicit-def: $sgpr77
|
|
; GFX9-NEXT: ; implicit-def: $sgpr75
|
|
; GFX9-NEXT: ; implicit-def: $sgpr74
|
|
; GFX9-NEXT: ; implicit-def: $sgpr73
|
|
; GFX9-NEXT: ; implicit-def: $sgpr63
|
|
; GFX9-NEXT: ; implicit-def: $sgpr42
|
|
; GFX9-NEXT: ; implicit-def: $sgpr72
|
|
; GFX9-NEXT: ; implicit-def: $sgpr62
|
|
; GFX9-NEXT: ; implicit-def: $sgpr61
|
|
; GFX9-NEXT: ; implicit-def: $sgpr60
|
|
; GFX9-NEXT: ; implicit-def: $sgpr58
|
|
; GFX9-NEXT: ; implicit-def: $sgpr44
|
|
; GFX9-NEXT: ; implicit-def: $sgpr59
|
|
; GFX9-NEXT: ; implicit-def: $sgpr57
|
|
; GFX9-NEXT: ; implicit-def: $sgpr56
|
|
; GFX9-NEXT: s_branch .LBB49_2
|
|
; GFX9-NEXT: .LBB49_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s44
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s42
|
|
; GFX9-NEXT: v_mov_b32_e32 v18, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s5
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s55
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, s53
|
|
; GFX9-NEXT: v_mov_b32_e32 v62, s54
|
|
; GFX9-NEXT: v_mov_b32_e32 v59, s52
|
|
; GFX9-NEXT: v_mov_b32_e32 v60, s51
|
|
; GFX9-NEXT: v_mov_b32_e32 v58, s50
|
|
; GFX9-NEXT: v_mov_b32_e32 v61, s48
|
|
; GFX9-NEXT: v_mov_b32_e32 v57, s49
|
|
; GFX9-NEXT: v_mov_b32_e32 v47, s39
|
|
; GFX9-NEXT: v_mov_b32_e32 v56, s38
|
|
; GFX9-NEXT: v_mov_b32_e32 v46, s37
|
|
; GFX9-NEXT: v_mov_b32_e32 v45, s35
|
|
; GFX9-NEXT: v_mov_b32_e32 v44, s36
|
|
; GFX9-NEXT: v_mov_b32_e32 v42, s34
|
|
; GFX9-NEXT: v_mov_b32_e32 v43, s31
|
|
; GFX9-NEXT: v_mov_b32_e32 v41, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v40, s94
|
|
; GFX9-NEXT: v_mov_b32_e32 v55, s95
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, s93
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, s92
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, s91
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, s89
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, s90
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, s88
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, s79
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, s78
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, s76
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, s77
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, s75
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, s74
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, s73
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, s63
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, s72
|
|
; GFX9-NEXT: v_mov_b32_e32 v30, s62
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, s61
|
|
; GFX9-NEXT: v_mov_b32_e32 v29, s60
|
|
; GFX9-NEXT: v_mov_b32_e32 v28, s58
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, s59
|
|
; GFX9-NEXT: v_mov_b32_e32 v17, s57
|
|
; GFX9-NEXT: v_mov_b32_e32 v26, s56
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s12
|
|
; GFX9-NEXT: v_mov_b32_e32 v23, s10
|
|
; GFX9-NEXT: v_mov_b32_e32 v24, s8
|
|
; GFX9-NEXT: v_mov_b32_e32 v25, s6
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s40
|
|
; GFX9-NEXT: v_mov_b32_e32 v21, s14
|
|
; GFX9-NEXT: .LBB49_5: ; %end
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
|
|
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
|
|
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
|
|
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
|
|
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
|
|
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
|
|
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v34, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v29, s4
|
|
; GFX9-NEXT: v_readlane_b32 s30, v63, 14
|
|
; GFX9-NEXT: v_readlane_b32 s31, v63, 15
|
|
; GFX9-NEXT: v_readlane_b32 s55, v63, 13
|
|
; GFX9-NEXT: v_readlane_b32 s54, v63, 12
|
|
; GFX9-NEXT: v_readlane_b32 s53, v63, 11
|
|
; GFX9-NEXT: v_readlane_b32 s52, v63, 10
|
|
; GFX9-NEXT: v_readlane_b32 s51, v63, 9
|
|
; GFX9-NEXT: v_readlane_b32 s50, v63, 8
|
|
; GFX9-NEXT: v_readlane_b32 s49, v63, 7
|
|
; GFX9-NEXT: v_readlane_b32 s48, v63, 6
|
|
; GFX9-NEXT: v_readlane_b32 s39, v63, 5
|
|
; GFX9-NEXT: v_readlane_b32 s38, v63, 4
|
|
; GFX9-NEXT: v_readlane_b32 s37, v63, 3
|
|
; GFX9-NEXT: v_readlane_b32 s36, v63, 2
|
|
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
|
|
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
|
|
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v16f32_to_v64i8_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_or_saveexec_b32 s4, -1
|
|
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s4
|
|
; GFX11-NEXT: v_writelane_b32 v40, s34, 0
|
|
; GFX11-NEXT: v_writelane_b32 v40, s35, 1
|
|
; GFX11-NEXT: v_writelane_b32 v40, s36, 2
|
|
; GFX11-NEXT: v_writelane_b32 v40, s37, 3
|
|
; GFX11-NEXT: v_writelane_b32 v40, s38, 4
|
|
; GFX11-NEXT: v_writelane_b32 v40, s39, 5
|
|
; GFX11-NEXT: v_writelane_b32 v40, s48, 6
|
|
; GFX11-NEXT: v_writelane_b32 v40, s49, 7
|
|
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
|
|
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s42, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB49_3
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
|
|
; GFX11-NEXT: s_lshr_b32 s44, s27, 16
|
|
; GFX11-NEXT: s_lshr_b32 s46, s27, 8
|
|
; GFX11-NEXT: s_lshr_b32 s45, s26, 16
|
|
; GFX11-NEXT: s_lshr_b32 s47, s26, 8
|
|
; GFX11-NEXT: s_lshr_b32 s56, s25, 24
|
|
; GFX11-NEXT: s_lshr_b32 s57, s25, 16
|
|
; GFX11-NEXT: s_lshr_b32 s59, s25, 8
|
|
; GFX11-NEXT: s_lshr_b32 s58, s24, 16
|
|
; GFX11-NEXT: s_lshr_b32 s60, s24, 8
|
|
; GFX11-NEXT: s_lshr_b32 s61, s23, 24
|
|
; GFX11-NEXT: s_lshr_b32 s62, s23, 16
|
|
; GFX11-NEXT: s_lshr_b32 s72, s23, 8
|
|
; GFX11-NEXT: s_lshr_b32 s63, s22, 16
|
|
; GFX11-NEXT: s_lshr_b32 s73, s22, 8
|
|
; GFX11-NEXT: s_lshr_b32 s74, s21, 24
|
|
; GFX11-NEXT: s_lshr_b32 s75, s21, 16
|
|
; GFX11-NEXT: s_lshr_b32 s77, s21, 8
|
|
; GFX11-NEXT: s_lshr_b32 s76, s20, 16
|
|
; GFX11-NEXT: s_lshr_b32 s78, s20, 8
|
|
; GFX11-NEXT: s_lshr_b32 s79, s19, 24
|
|
; GFX11-NEXT: s_lshr_b32 s88, s19, 16
|
|
; GFX11-NEXT: s_lshr_b32 s90, s19, 8
|
|
; GFX11-NEXT: s_lshr_b32 s89, s18, 16
|
|
; GFX11-NEXT: s_lshr_b32 s91, s18, 8
|
|
; GFX11-NEXT: s_lshr_b32 s92, s17, 24
|
|
; GFX11-NEXT: s_lshr_b32 s93, s17, 16
|
|
; GFX11-NEXT: s_lshr_b32 s95, s17, 8
|
|
; GFX11-NEXT: s_lshr_b32 s94, s16, 16
|
|
; GFX11-NEXT: s_lshr_b32 vcc_hi, s16, 8
|
|
; GFX11-NEXT: s_lshr_b32 s30, s3, 24
|
|
; GFX11-NEXT: s_lshr_b32 s31, s3, 16
|
|
; GFX11-NEXT: s_lshr_b32 s35, s3, 8
|
|
; GFX11-NEXT: s_lshr_b32 s34, s2, 16
|
|
; GFX11-NEXT: s_lshr_b32 s36, s2, 8
|
|
; GFX11-NEXT: s_lshr_b32 s37, s1, 24
|
|
; GFX11-NEXT: s_lshr_b32 s38, s1, 16
|
|
; GFX11-NEXT: s_lshr_b32 s48, s1, 8
|
|
; GFX11-NEXT: s_lshr_b32 s39, s0, 16
|
|
; GFX11-NEXT: s_lshr_b32 s49, s0, 8
|
|
; GFX11-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[28:29], s[24:25], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[12:13], s[20:21], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[10:11], s[18:19], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[8:9], s[16:17], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[6:7], s[2:3], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[4:5], s[0:1], 24
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB49_4
|
|
; GFX11-NEXT: .LBB49_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f32_e64 v4, s25, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v3, s24, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v6, s23, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v5, s22, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v8, s21, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v7, s20, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v10, s19, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v9, s18, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v12, s17, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v11, s16, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v14, s3, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v13, s2, 1.0
|
|
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[3:4]
|
|
; GFX11-NEXT: v_add_f32_e64 v18, s1, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v17, s0, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v2, s27, 1.0
|
|
; GFX11-NEXT: v_add_f32_e64 v1, s26, 1.0
|
|
; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[17:18]
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v5
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v5
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v7
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v49, 8, v7
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v55, 24, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v9
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v64, 8, v9
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v69, 24, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v67, 8, v11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v13
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v13
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v87, 24, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v17
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v17
|
|
; GFX11-NEXT: s_branch .LBB49_5
|
|
; GFX11-NEXT: .LBB49_3:
|
|
; GFX11-NEXT: ; implicit-def: $sgpr49
|
|
; GFX11-NEXT: ; implicit-def: $sgpr39
|
|
; GFX11-NEXT: ; implicit-def: $sgpr4
|
|
; GFX11-NEXT: ; implicit-def: $sgpr48
|
|
; GFX11-NEXT: ; implicit-def: $sgpr38
|
|
; GFX11-NEXT: ; implicit-def: $sgpr37
|
|
; GFX11-NEXT: ; implicit-def: $sgpr36
|
|
; GFX11-NEXT: ; implicit-def: $sgpr34
|
|
; GFX11-NEXT: ; implicit-def: $sgpr6
|
|
; GFX11-NEXT: ; implicit-def: $sgpr35
|
|
; GFX11-NEXT: ; implicit-def: $sgpr31
|
|
; GFX11-NEXT: ; implicit-def: $sgpr30
|
|
; GFX11-NEXT: ; implicit-def: $vcc_hi
|
|
; GFX11-NEXT: ; implicit-def: $sgpr94
|
|
; GFX11-NEXT: ; implicit-def: $sgpr8
|
|
; GFX11-NEXT: ; implicit-def: $sgpr95
|
|
; GFX11-NEXT: ; implicit-def: $sgpr93
|
|
; GFX11-NEXT: ; implicit-def: $sgpr92
|
|
; GFX11-NEXT: ; implicit-def: $sgpr91
|
|
; GFX11-NEXT: ; implicit-def: $sgpr89
|
|
; GFX11-NEXT: ; implicit-def: $sgpr10
|
|
; GFX11-NEXT: ; implicit-def: $sgpr90
|
|
; GFX11-NEXT: ; implicit-def: $sgpr88
|
|
; GFX11-NEXT: ; implicit-def: $sgpr79
|
|
; GFX11-NEXT: ; implicit-def: $sgpr78
|
|
; GFX11-NEXT: ; implicit-def: $sgpr76
|
|
; GFX11-NEXT: ; implicit-def: $sgpr12
|
|
; GFX11-NEXT: ; implicit-def: $sgpr77
|
|
; GFX11-NEXT: ; implicit-def: $sgpr75
|
|
; GFX11-NEXT: ; implicit-def: $sgpr74
|
|
; GFX11-NEXT: ; implicit-def: $sgpr73
|
|
; GFX11-NEXT: ; implicit-def: $sgpr63
|
|
; GFX11-NEXT: ; implicit-def: $sgpr14
|
|
; GFX11-NEXT: ; implicit-def: $sgpr72
|
|
; GFX11-NEXT: ; implicit-def: $sgpr62
|
|
; GFX11-NEXT: ; implicit-def: $sgpr61
|
|
; GFX11-NEXT: ; implicit-def: $sgpr60
|
|
; GFX11-NEXT: ; implicit-def: $sgpr58
|
|
; GFX11-NEXT: ; implicit-def: $sgpr28
|
|
; GFX11-NEXT: ; implicit-def: $sgpr59
|
|
; GFX11-NEXT: ; implicit-def: $sgpr57
|
|
; GFX11-NEXT: ; implicit-def: $sgpr56
|
|
; GFX11-NEXT: ; implicit-def: $sgpr47
|
|
; GFX11-NEXT: ; implicit-def: $sgpr45
|
|
; GFX11-NEXT: ; implicit-def: $sgpr40
|
|
; GFX11-NEXT: ; implicit-def: $sgpr46
|
|
; GFX11-NEXT: ; implicit-def: $sgpr44
|
|
; GFX11-NEXT: ; implicit-def: $sgpr43
|
|
; GFX11-NEXT: s_branch .LBB49_2
|
|
; GFX11-NEXT: .LBB49_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v17, s0 :: v_dual_mov_b32 v18, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v14, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v12, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v8, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v4, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
|
|
; GFX11-NEXT: v_dual_mov_b32 v85, s49 :: v_dual_mov_b32 v96, s39
|
|
; GFX11-NEXT: v_dual_mov_b32 v83, s48 :: v_dual_mov_b32 v86, s38
|
|
; GFX11-NEXT: v_dual_mov_b32 v87, s37 :: v_dual_mov_b32 v82, s36
|
|
; GFX11-NEXT: v_dual_mov_b32 v84, s34 :: v_dual_mov_b32 v71, s35
|
|
; GFX11-NEXT: v_dual_mov_b32 v80, s31 :: v_dual_mov_b32 v81, s30
|
|
; GFX11-NEXT: v_dual_mov_b32 v67, vcc_hi :: v_dual_mov_b32 v70, s94
|
|
; GFX11-NEXT: v_dual_mov_b32 v65, s95 :: v_dual_mov_b32 v68, s93
|
|
; GFX11-NEXT: v_dual_mov_b32 v69, s92 :: v_dual_mov_b32 v64, s91
|
|
; GFX11-NEXT: v_dual_mov_b32 v66, s89 :: v_dual_mov_b32 v53, s90
|
|
; GFX11-NEXT: v_dual_mov_b32 v54, s88 :: v_dual_mov_b32 v55, s79
|
|
; GFX11-NEXT: v_dual_mov_b32 v49, s78 :: v_dual_mov_b32 v52, s76
|
|
; GFX11-NEXT: v_dual_mov_b32 v39, s77 :: v_dual_mov_b32 v50, s75
|
|
; GFX11-NEXT: v_dual_mov_b32 v51, s74 :: v_dual_mov_b32 v38, s73
|
|
; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v37, s61
|
|
; GFX11-NEXT: v_dual_mov_b32 v34, s72 :: v_dual_mov_b32 v33, s60
|
|
; GFX11-NEXT: v_dual_mov_b32 v36, s62 :: v_dual_mov_b32 v35, s58
|
|
; GFX11-NEXT: v_dual_mov_b32 v29, s59 :: v_dual_mov_b32 v32, s56
|
|
; GFX11-NEXT: v_dual_mov_b32 v31, s57 :: v_dual_mov_b32 v26, s47
|
|
; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v27, s44
|
|
; GFX11-NEXT: v_dual_mov_b32 v16, s46 :: v_dual_mov_b32 v15, s40
|
|
; GFX11-NEXT: v_dual_mov_b32 v28, s43 :: v_dual_mov_b32 v19, s28
|
|
; GFX11-NEXT: v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v21, s12
|
|
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
|
|
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
|
|
; GFX11-NEXT: .LBB49_5: ; %end
|
|
; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
|
|
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
|
|
; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
|
|
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
|
|
; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
|
|
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
|
|
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
|
|
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
|
|
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
|
|
; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
|
|
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
|
|
; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
|
|
; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
|
|
; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
|
|
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
|
|
; GFX11-NEXT: s_clause 0x3
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:16
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:32
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
|
|
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
|
|
; GFX11-NEXT: v_readlane_b32 s49, v40, 7
|
|
; GFX11-NEXT: v_readlane_b32 s48, v40, 6
|
|
; GFX11-NEXT: v_readlane_b32 s39, v40, 5
|
|
; GFX11-NEXT: v_readlane_b32 s38, v40, 4
|
|
; GFX11-NEXT: v_readlane_b32 s37, v40, 3
|
|
; GFX11-NEXT: v_readlane_b32 s36, v40, 2
|
|
; GFX11-NEXT: v_readlane_b32 s35, v40, 1
|
|
; GFX11-NEXT: v_readlane_b32 s34, v40, 0
|
|
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
|
|
; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s0
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <16 x float> %a, splat (float 1.000000e+00)
|
|
%a2 = bitcast <16 x float> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <16 x float> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v16f32:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v34, v6
|
|
; SI-NEXT: v_mov_b32_e32 v33, v4
|
|
; SI-NEXT: v_mov_b32_e32 v32, v2
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:80
|
|
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:88
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:96
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:104
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:112
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:120
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:128
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 8, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v17
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v8
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v10
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v12
|
|
; SI-NEXT: s_waitcnt vmcnt(10)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v50
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v51
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v52
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v53
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v55
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v40
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v42
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v44
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v58
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v47
|
|
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100
|
|
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB50_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v49
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v1, v48, v1
|
|
; SI-NEXT: v_or_b32_e32 v3, v35, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v57
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v62, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v56, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v52
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v43, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v54, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v44
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v21, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v53
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v27, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v37, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v20, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v24, v6
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v28, v7
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v38
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v17, v8
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v18
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v30
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v63
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v45
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v59
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v46
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v41
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v47
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v51
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v19
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v25
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v50, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: .LBB50_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB50_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
|
|
; SI-NEXT: v_or_b32_e32 v0, v49, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v48, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
|
|
; SI-NEXT: v_or_b32_e32 v1, v39, v1
|
|
; SI-NEXT: s_movk_i32 s6, 0x300
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v35, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v57
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v62, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v42
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v56, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v43, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v54, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v44
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v21, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v27, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: s_mov_b32 s7, 0x3000000
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v36, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v37, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v20, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v24, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v28, v7
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v38, v3
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v17, v8
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v18, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v22, v5
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v26, v6
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v30, v7
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v60
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v63, v8
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v59, v9
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v46, v10
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v41, v11
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v47
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v51, v12
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v19, v13
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v23
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v25, v14
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x300, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v50, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
|
|
; SI-NEXT: .LBB50_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v16f32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v53, v1
|
|
; VI-NEXT: v_mov_b32_e32 v54, v0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:128
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:88
|
|
; VI-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; VI-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:80
|
|
; VI-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: v_mov_b32_e32 v31, v15
|
|
; VI-NEXT: v_mov_b32_e32 v32, v14
|
|
; VI-NEXT: v_mov_b32_e32 v33, v13
|
|
; VI-NEXT: v_mov_b32_e32 v34, v12
|
|
; VI-NEXT: v_mov_b32_e32 v35, v11
|
|
; VI-NEXT: v_mov_b32_e32 v36, v10
|
|
; VI-NEXT: v_mov_b32_e32 v37, v9
|
|
; VI-NEXT: v_mov_b32_e32 v38, v8
|
|
; VI-NEXT: v_mov_b32_e32 v39, v7
|
|
; VI-NEXT: v_mov_b32_e32 v48, v6
|
|
; VI-NEXT: v_mov_b32_e32 v49, v5
|
|
; VI-NEXT: v_mov_b32_e32 v50, v4
|
|
; VI-NEXT: v_mov_b32_e32 v51, v3
|
|
; VI-NEXT: v_mov_b32_e32 v52, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:124
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:120
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:116
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:112
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:108
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:104
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:100
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:96
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:92
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB50_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
|
|
; VI-NEXT: v_perm_b32 v3, v48, v39, s6
|
|
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
|
|
; VI-NEXT: v_perm_b32 v2, v50, v49, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
|
|
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v16, v25, v16, s6
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: .LBB50_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB50_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v54
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v53
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v52
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v51
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v50
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v49
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v48
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v39
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_mov_b32_e32 v15, 0x300
|
|
; VI-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; VI-NEXT: v_add_u16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v38
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v37
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v36
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v35
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v33
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v32
|
|
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v31
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; VI-NEXT: v_add_u16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v16
|
|
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v17
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v18
|
|
; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v19
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v4, 0x300, v4
|
|
; VI-NEXT: v_add_u16_sdwa v5, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v20
|
|
; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v21
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v22
|
|
; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v23
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v5, 0x300, v5
|
|
; VI-NEXT: v_add_u16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v30
|
|
; VI-NEXT: v_lshlrev_b16_e32 v10, 8, v27
|
|
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29
|
|
; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v42
|
|
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v63
|
|
; VI-NEXT: v_lshlrev_b16_e32 v14, 8, v59
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(5)
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v7
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v6, 0x300, v6
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; VI-NEXT: s_waitcnt vmcnt(3)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v18, 8, v18
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v7, 0x300, v7
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v57
|
|
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v56
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v26
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
|
|
; VI-NEXT: v_add_u16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v47
|
|
; VI-NEXT: v_lshlrev_b16_e32 v10, 8, v46
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v28
|
|
; VI-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v9, 0x300, v9
|
|
; VI-NEXT: v_add_u16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v45
|
|
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v44
|
|
; VI-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v43
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v10, 0x300, v10
|
|
; VI-NEXT: v_add_u16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v41
|
|
; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v40
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v55
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v11, 0x300, v11
|
|
; VI-NEXT: v_add_u16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v62
|
|
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v61
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v60
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v12, 0x300, v12
|
|
; VI-NEXT: v_add_u16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v58
|
|
; VI-NEXT: v_lshlrev_b16_e32 v14, 8, v24
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v13, 0x300, v13
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: v_or_b32_sdwa v14, v16, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v14, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; VI-NEXT: v_or_b32_sdwa v14, v16, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v16
|
|
; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v16, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v16
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v17, 3, v25
|
|
; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v16
|
|
; VI-NEXT: v_add_u16_sdwa v15, v17, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: .LBB50_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v16f32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:128
|
|
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
|
|
; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:80
|
|
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, v15
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, v14
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, v13
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, v12
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, v11
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, v2
|
|
; GFX9-NEXT: s_waitcnt vmcnt(24)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(22)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:124
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:120
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:116
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:112
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:108
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:104
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:100
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:96
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:92
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB50_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v0, v54, v53, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v52, v51, s6
|
|
; GFX9-NEXT: v_perm_b32 v2, v50, v49, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v48, v39, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v2, v38, v37, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v36, v35, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v3, v34, v33, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v32, v31, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v9, v47, v46, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v45, v44, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v42, v30, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v55, v63, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v60, v59, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr22
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v43, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
|
|
; GFX9-NEXT: v_perm_b32 v8, v24, v25, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
|
|
; GFX9-NEXT: v_perm_b32 v9, v26, v27, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
|
|
; GFX9-NEXT: v_perm_b32 v10, v28, v29, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
|
|
; GFX9-NEXT: v_perm_b32 v11, v41, v40, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, v62, v61, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
|
|
; GFX9-NEXT: v_perm_b32 v13, v58, v57, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v16, v56, v16, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: .LBB50_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB50_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v54
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v53
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 3, v52
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v51
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v50
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v49
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v48
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v39
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x300
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v36
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 3, v32
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 3, v18
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 3, v22
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v46
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v44
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v30
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v63
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v59
|
|
; GFX9-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 3, v24
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v25
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
|
|
; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 3, v26
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v27
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 3, v45
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
|
|
; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 3, v28
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 3, v42
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
|
|
; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 3, v41
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v40
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 3, v55
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
|
|
; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 3, v62
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v61
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 3, v60
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
|
|
; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 3, v58
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v57
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v16, 3, v56
|
|
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
|
|
; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX9-NEXT: .LBB50_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v16f32:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1f
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:128
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:124
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:116
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:112
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:108
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:104
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:100
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:96
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:92
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:88
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:84
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:80
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:76
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:72
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:68
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v128, off, s32 offset:132
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v14.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v13.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v12.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v11.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v9.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v7.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v6.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v5.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v4.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v0.l
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v128
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB50_4
|
|
; GFX11-TRUE16-NEXT: .LBB50_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB50_3: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v119, v118, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v117, v116, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v114, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v113, v112, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v101, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v102, v100, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v99, v98, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v16, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v96, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v30, v87, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v86, v85, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v84, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v81, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v71, v69, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v68, v67, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v65, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v54, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB50_2
|
|
; GFX11-TRUE16-NEXT: .LBB50_4: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v117.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v118.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v116.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v115.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v113.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v114.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v112.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v103.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v102.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v100.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v99.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v101.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v17.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v4.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v97.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v96.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v20.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v4.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v22.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v26.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v27.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v3.h, v4.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v5.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v19.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v21.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v28.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v30.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v23.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v24.l, 3
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v86.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v82.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v81.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v6.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v6.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v25.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v80.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v71.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v68.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v8.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v29.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v87.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v65.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v55.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v54.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v9.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v85.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v84.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v12.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v13.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v52.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v9.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v83.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v51.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v50.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v49.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v70.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v69.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v12.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v13.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v10.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, v37.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v67.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v66.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v35.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v33.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v36.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v64.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v15.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v34.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v32.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v11.h, v11.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v53.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v31.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v17.l, v15.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v17.h, v15.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v12.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v48.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v12.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v13.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v13.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, v38.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v14.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v14.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v39.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v13.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v3.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v4.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v14.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v4.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v18.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v5.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v5.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v6.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v6.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v7.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v8.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v8.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v10.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v10.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v11.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v14.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v14.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v15.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v15.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v16.l
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v16f32:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1f
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:128
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:124
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:120
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:116
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:112
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:108
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:104
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:96
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:92
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:88
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:84
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:80
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:76
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:72
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:68
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:64
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v14
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v34, v12
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB50_4
|
|
; GFX11-FAKE16-NEXT: .LBB50_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB50_3: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v36, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v119, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v118, v117, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v115, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v112, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v113, v103, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v102, v100, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v101, v99, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v96, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v97, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v83, v81, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v70, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v71, v68, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v65, v55, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
|
|
; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v36, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v37
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v34, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v35
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v31
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v16, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v22, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v24, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v119
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v118, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v98, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v83, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v84
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v82
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v81
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v80, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v71, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v69, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v67, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v65, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v18, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v70
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v68
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v66
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v64
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v55
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v23, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v25, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v16f32_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v28
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s11, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v24
|
|
; SI-NEXT: v_readfirstlane_b32 s13, v23
|
|
; SI-NEXT: v_readfirstlane_b32 s14, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s15, v21
|
|
; SI-NEXT: v_readfirstlane_b32 s40, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s41, v19
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s43, v17
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s45, v15
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s47, v13
|
|
; SI-NEXT: v_readfirstlane_b32 s56, v12
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v30
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s59, v9
|
|
; SI-NEXT: v_readfirstlane_b32 s60, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s61, v7
|
|
; SI-NEXT: v_readfirstlane_b32 s62, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s63, v5
|
|
; SI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s73, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s74, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s75, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s76, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
|
|
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v22
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v24
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v25
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v35
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v37
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
|
|
; SI-NEXT: s_cbranch_scc0 .LBB51_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, s4, v34
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s18, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s77, s19, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s77, s5
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s77, s21, 8
|
|
; SI-NEXT: s_or_b32 s5, s5, s77
|
|
; SI-NEXT: s_and_b32 s77, s22, 0xff
|
|
; SI-NEXT: s_lshl_b32 s77, s77, 16
|
|
; SI-NEXT: s_lshl_b32 s78, s23, 24
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s77, s78, s77
|
|
; SI-NEXT: s_or_b32 s5, s5, s77
|
|
; SI-NEXT: s_and_b32 s77, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s78, s25, 8
|
|
; SI-NEXT: s_or_b32 s77, s77, s78
|
|
; SI-NEXT: s_and_b32 s78, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s78, s78, 16
|
|
; SI-NEXT: s_lshl_b32 s79, s27, 24
|
|
; SI-NEXT: s_and_b32 s77, s77, 0xffff
|
|
; SI-NEXT: s_or_b32 s78, s79, s78
|
|
; SI-NEXT: s_or_b32 s77, s77, s78
|
|
; SI-NEXT: s_and_b32 s78, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s79, s29, 8
|
|
; SI-NEXT: s_or_b32 s78, s78, s79
|
|
; SI-NEXT: s_and_b32 s79, s76, 0xff
|
|
; SI-NEXT: s_lshl_b32 s79, s79, 16
|
|
; SI-NEXT: s_lshl_b32 s88, s75, 24
|
|
; SI-NEXT: s_and_b32 s78, s78, 0xffff
|
|
; SI-NEXT: s_or_b32 s79, s88, s79
|
|
; SI-NEXT: s_or_b32 s78, s78, s79
|
|
; SI-NEXT: s_and_b32 s79, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s88, s73, 8
|
|
; SI-NEXT: s_or_b32 s79, s79, s88
|
|
; SI-NEXT: s_and_b32 s88, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s88, s88, 16
|
|
; SI-NEXT: s_lshl_b32 s89, s63, 24
|
|
; SI-NEXT: s_and_b32 s79, s79, 0xffff
|
|
; SI-NEXT: s_or_b32 s88, s89, s88
|
|
; SI-NEXT: s_or_b32 s79, s79, s88
|
|
; SI-NEXT: s_and_b32 s88, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s89, s61, 8
|
|
; SI-NEXT: s_or_b32 s88, s88, s89
|
|
; SI-NEXT: s_and_b32 s89, s60, 0xff
|
|
; SI-NEXT: s_lshl_b32 s89, s89, 16
|
|
; SI-NEXT: s_lshl_b32 s90, s59, 24
|
|
; SI-NEXT: s_and_b32 s88, s88, 0xffff
|
|
; SI-NEXT: s_or_b32 s89, s90, s89
|
|
; SI-NEXT: s_or_b32 s88, s88, s89
|
|
; SI-NEXT: s_and_b32 s89, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s90, s57, 8
|
|
; SI-NEXT: s_or_b32 s89, s89, s90
|
|
; SI-NEXT: s_and_b32 s90, s56, 0xff
|
|
; SI-NEXT: s_lshl_b32 s90, s90, 16
|
|
; SI-NEXT: s_lshl_b32 s91, s47, 24
|
|
; SI-NEXT: s_and_b32 s89, s89, 0xffff
|
|
; SI-NEXT: s_or_b32 s90, s91, s90
|
|
; SI-NEXT: s_or_b32 s89, s89, s90
|
|
; SI-NEXT: s_and_b32 s90, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s91, s45, 8
|
|
; SI-NEXT: s_or_b32 s90, s90, s91
|
|
; SI-NEXT: s_and_b32 s91, s44, 0xff
|
|
; SI-NEXT: s_lshl_b32 s91, s91, 16
|
|
; SI-NEXT: s_lshl_b32 s92, s43, 24
|
|
; SI-NEXT: s_and_b32 s90, s90, 0xffff
|
|
; SI-NEXT: s_or_b32 s91, s92, s91
|
|
; SI-NEXT: s_or_b32 s90, s90, s91
|
|
; SI-NEXT: s_and_b32 s91, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s92, s41, 8
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v20
|
|
; SI-NEXT: s_or_b32 s91, s91, s92
|
|
; SI-NEXT: s_and_b32 s92, s40, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_lshl_b32 s92, s92, 16
|
|
; SI-NEXT: s_lshl_b32 s93, s15, 24
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v33, v1
|
|
; SI-NEXT: s_and_b32 s91, s91, 0xffff
|
|
; SI-NEXT: s_or_b32 s92, s93, s92
|
|
; SI-NEXT: v_or_b32_e32 v11, v0, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v21
|
|
; SI-NEXT: s_or_b32 s91, s91, s92
|
|
; SI-NEXT: s_and_b32 s92, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s93, s13, 8
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s92, s92, s93
|
|
; SI-NEXT: s_and_b32 s93, s12, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v29, v1
|
|
; SI-NEXT: s_lshl_b32 s93, s93, 16
|
|
; SI-NEXT: s_lshl_b32 s94, s11, 24
|
|
; SI-NEXT: v_or_b32_e32 v13, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v19
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
|
|
; SI-NEXT: s_and_b32 s92, s92, 0xffff
|
|
; SI-NEXT: s_or_b32 s93, s94, s93
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s92, s92, s93
|
|
; SI-NEXT: s_and_b32 s93, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s94, s9, 8
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v25, v1
|
|
; SI-NEXT: s_or_b32 s93, s93, s94
|
|
; SI-NEXT: s_and_b32 s94, s8, 0xff
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v28
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v26
|
|
; SI-NEXT: v_or_b32_e32 v14, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
|
|
; SI-NEXT: s_lshl_b32 s94, s94, 16
|
|
; SI-NEXT: s_lshl_b32 s95, s7, 24
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_and_b32 s93, s93, 0xffff
|
|
; SI-NEXT: s_or_b32 s94, s95, s94
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v31, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v22, v1
|
|
; SI-NEXT: s_or_b32 s93, s93, s94
|
|
; SI-NEXT: v_or_b32_e32 v12, v2, v3
|
|
; SI-NEXT: v_or_b32_e32 v15, v0, v1
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
; SI-NEXT: v_mov_b32_e32 v2, s77
|
|
; SI-NEXT: v_mov_b32_e32 v3, s78
|
|
; SI-NEXT: v_mov_b32_e32 v4, s79
|
|
; SI-NEXT: v_mov_b32_e32 v5, s88
|
|
; SI-NEXT: v_mov_b32_e32 v6, s89
|
|
; SI-NEXT: v_mov_b32_e32 v7, s90
|
|
; SI-NEXT: v_mov_b32_e32 v8, s91
|
|
; SI-NEXT: v_mov_b32_e32 v9, s92
|
|
; SI-NEXT: v_mov_b32_e32 v10, s93
|
|
; SI-NEXT: s_cbranch_execnz .LBB51_3
|
|
; SI-NEXT: .LBB51_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s16, s18, 0xff
|
|
; SI-NEXT: s_addk_i32 s4, 0x300
|
|
; SI-NEXT: s_lshl_b32 s5, s19, 24
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s5, s16
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s16, s21, 8
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_or_b32 s5, s16, s5
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xff
|
|
; SI-NEXT: s_addk_i32 s5, 0x300
|
|
; SI-NEXT: s_lshl_b32 s16, s23, 24
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_or_b32 s5, s16, s5
|
|
; SI-NEXT: s_and_b32 s16, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s25, 8
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s6, s6, 3
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s18, s26, 0xff
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
|
|
; SI-NEXT: s_addk_i32 s16, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s27, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, s6, v34
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s17, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s18, s29, 8
|
|
; SI-NEXT: s_add_i32 s76, s76, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v33, v1
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_and_b32 s19, s76, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_addk_i32 s17, 0x300
|
|
; SI-NEXT: s_lshl_b32 s18, s75, 24
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v28
|
|
; SI-NEXT: s_and_b32 s17, s17, 0xffff
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_add_i32 s74, s74, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_and_b32 s18, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s19, s73, 8
|
|
; SI-NEXT: s_add_i32 s72, s72, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v32, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_and_b32 s20, s72, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_addk_i32 s18, 0x300
|
|
; SI-NEXT: s_lshl_b32 s19, s63, 24
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v31, v1
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xffff
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_add_i32 s62, s62, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_and_b32 s19, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s20, s61, 8
|
|
; SI-NEXT: s_add_i32 s60, s60, 3
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v23
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s21, s60, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v21
|
|
; SI-NEXT: s_addk_i32 s19, 0x300
|
|
; SI-NEXT: s_lshl_b32 s20, s59, 24
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, v30, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s19, s19, 0xffff
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_add_i32 s58, s58, 3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s20, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s21, s57, 8
|
|
; SI-NEXT: s_add_i32 s56, s56, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v29, v1
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s22, s56, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_addk_i32 s20, 0x300
|
|
; SI-NEXT: s_lshl_b32 s21, s47, 24
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
|
|
; SI-NEXT: s_and_b32 s20, s20, 0xffff
|
|
; SI-NEXT: s_or_b32 s21, s21, s22
|
|
; SI-NEXT: s_add_i32 s46, s46, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s21, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s22, s45, 8
|
|
; SI-NEXT: s_add_i32 s44, s44, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v27, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_or_b32 s21, s22, s21
|
|
; SI-NEXT: s_and_b32 s23, s44, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_addk_i32 s21, 0x300
|
|
; SI-NEXT: s_lshl_b32 s22, s43, 24
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v25, v1
|
|
; SI-NEXT: s_and_b32 s21, s21, 0xffff
|
|
; SI-NEXT: s_or_b32 s22, s22, s23
|
|
; SI-NEXT: s_add_i32 s42, s42, 3
|
|
; SI-NEXT: s_add_i32 s14, s14, 3
|
|
; SI-NEXT: s_add_i32 s10, s10, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_or_b32 s21, s22, s21
|
|
; SI-NEXT: s_and_b32 s22, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s23, s41, 8
|
|
; SI-NEXT: s_add_i32 s40, s40, 3
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 8
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 8
|
|
; SI-NEXT: s_add_i32 s8, s8, 3
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
|
|
; SI-NEXT: s_or_b32 s22, s23, s22
|
|
; SI-NEXT: s_and_b32 s23, s40, 0xff
|
|
; SI-NEXT: s_or_b32 s13, s13, s14
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xff
|
|
; SI-NEXT: s_or_b32 s9, s9, s10
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
|
|
; SI-NEXT: s_addk_i32 s22, 0x300
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 24
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_addk_i32 s13, 0x300
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 24
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_addk_i32 s9, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 24
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, v24, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s22, s22, 0xffff
|
|
; SI-NEXT: s_or_b32 s15, s15, s23
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_or_b32 s11, s11, s12
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s8
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s15, s15, s22
|
|
; SI-NEXT: s_or_b32 s11, s11, s13
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v22, v1
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
|
|
; SI-NEXT: s_add_i32 s16, s16, 0x3000000
|
|
; SI-NEXT: s_add_i32 s17, s17, 0x3000000
|
|
; SI-NEXT: s_add_i32 s18, s18, 0x3000000
|
|
; SI-NEXT: s_add_i32 s19, s19, 0x3000000
|
|
; SI-NEXT: s_add_i32 s20, s20, 0x3000000
|
|
; SI-NEXT: s_add_i32 s21, s21, 0x3000000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
; SI-NEXT: v_mov_b32_e32 v2, s16
|
|
; SI-NEXT: v_mov_b32_e32 v3, s17
|
|
; SI-NEXT: v_mov_b32_e32 v4, s18
|
|
; SI-NEXT: v_mov_b32_e32 v5, s19
|
|
; SI-NEXT: v_mov_b32_e32 v6, s20
|
|
; SI-NEXT: v_mov_b32_e32 v7, s21
|
|
; SI-NEXT: v_mov_b32_e32 v8, s15
|
|
; SI-NEXT: v_mov_b32_e32 v9, s11
|
|
; SI-NEXT: v_mov_b32_e32 v10, s7
|
|
; SI-NEXT: .LBB51_3: ; %end
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB51_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_branch .LBB51_2
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v16f32_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v30
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v29
|
|
; VI-NEXT: v_readfirstlane_b32 s8, v28
|
|
; VI-NEXT: v_readfirstlane_b32 s9, v27
|
|
; VI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; VI-NEXT: v_readfirstlane_b32 s11, v25
|
|
; VI-NEXT: v_readfirstlane_b32 s12, v24
|
|
; VI-NEXT: v_readfirstlane_b32 s13, v23
|
|
; VI-NEXT: v_readfirstlane_b32 s14, v22
|
|
; VI-NEXT: v_readfirstlane_b32 s15, v21
|
|
; VI-NEXT: v_readfirstlane_b32 s40, v20
|
|
; VI-NEXT: v_readfirstlane_b32 s41, v19
|
|
; VI-NEXT: v_readfirstlane_b32 s42, v18
|
|
; VI-NEXT: v_readfirstlane_b32 s43, v17
|
|
; VI-NEXT: v_readfirstlane_b32 s44, v16
|
|
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: v_readfirstlane_b32 s45, v15
|
|
; VI-NEXT: v_readfirstlane_b32 s46, v14
|
|
; VI-NEXT: v_readfirstlane_b32 s47, v13
|
|
; VI-NEXT: v_readfirstlane_b32 s56, v12
|
|
; VI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; VI-NEXT: v_readfirstlane_b32 s58, v10
|
|
; VI-NEXT: v_readfirstlane_b32 s59, v9
|
|
; VI-NEXT: v_readfirstlane_b32 s60, v8
|
|
; VI-NEXT: v_readfirstlane_b32 s61, v7
|
|
; VI-NEXT: v_readfirstlane_b32 s62, v6
|
|
; VI-NEXT: v_readfirstlane_b32 s63, v5
|
|
; VI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; VI-NEXT: v_readfirstlane_b32 s73, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s74, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s75, v1
|
|
; VI-NEXT: v_readfirstlane_b32 s76, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; VI-NEXT: s_cbranch_scc0 .LBB51_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_mov_b32_e32 v3, s23
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_mov_b32_e32 v2, s21
|
|
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s75
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_mov_b32_e32 v5, s63
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_mov_b32_e32 v4, s73
|
|
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_mov_b32_e32 v5, s61
|
|
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_mov_b32_e32 v7, s47
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_mov_b32_e32 v6, s57
|
|
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_mov_b32_e32 v8, s43
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_mov_b32_e32 v7, s45
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_mov_b32_e32 v9, s15
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_mov_b32_e32 v8, s41
|
|
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_mov_b32_e32 v10, s11
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_mov_b32_e32 v9, s13
|
|
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_mov_b32_e32 v12, s7
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_mov_b32_e32 v10, s9
|
|
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; VI-NEXT: v_perm_b32 v12, v24, v22, s4
|
|
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
|
|
; VI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
|
|
; VI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
|
|
; VI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
|
|
; VI-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; VI-NEXT: s_cbranch_execnz .LBB51_3
|
|
; VI-NEXT: .LBB51_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x300, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s21
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: v_mov_b32_e32 v2, s23
|
|
; VI-NEXT: v_perm_b32 v1, s20, v1, v11
|
|
; VI-NEXT: v_perm_b32 v2, s22, v2, v11
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x300, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x300, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: s_add_i32 s76, s76, 3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s75
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x300, v3
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s74, s74, 3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s73
|
|
; VI-NEXT: s_add_i32 s72, s72, 3
|
|
; VI-NEXT: v_mov_b32_e32 v5, s63
|
|
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x300, v4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s62, s62, 3
|
|
; VI-NEXT: v_mov_b32_e32 v5, s61
|
|
; VI-NEXT: s_add_i32 s60, s60, 3
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x300, v5
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s58, s58, 3
|
|
; VI-NEXT: v_mov_b32_e32 v6, s57
|
|
; VI-NEXT: s_add_i32 s56, s56, 3
|
|
; VI-NEXT: v_mov_b32_e32 v7, s47
|
|
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x300, v6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s46, s46, 3
|
|
; VI-NEXT: v_mov_b32_e32 v7, s45
|
|
; VI-NEXT: s_add_i32 s44, s44, 3
|
|
; VI-NEXT: v_mov_b32_e32 v8, s43
|
|
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x300, v7
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s42, s42, 3
|
|
; VI-NEXT: v_mov_b32_e32 v8, s41
|
|
; VI-NEXT: s_add_i32 s40, s40, 3
|
|
; VI-NEXT: v_mov_b32_e32 v9, s15
|
|
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x300, v8
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s14, s14, 3
|
|
; VI-NEXT: v_mov_b32_e32 v9, s13
|
|
; VI-NEXT: s_add_i32 s12, s12, 3
|
|
; VI-NEXT: v_mov_b32_e32 v10, s11
|
|
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x300, v9
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s10, s10, 3
|
|
; VI-NEXT: v_mov_b32_e32 v10, s9
|
|
; VI-NEXT: s_add_i32 s8, s8, 3
|
|
; VI-NEXT: v_mov_b32_e32 v12, s7
|
|
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x300, v10
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_sdwa v10, v12, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v24
|
|
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
|
|
; VI-NEXT: v_perm_b32 v12, v12, v22, s4
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x300, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v34
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v32
|
|
; VI-NEXT: v_perm_b32 v12, v12, v33, s4
|
|
; VI-NEXT: v_perm_b32 v13, v13, v31, s4
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x300, v12
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v30
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v28
|
|
; VI-NEXT: v_perm_b32 v13, v13, v29, s4
|
|
; VI-NEXT: v_perm_b32 v14, v14, v27, s4
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x300, v13
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v25
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v21
|
|
; VI-NEXT: v_perm_b32 v14, v14, v23, s4
|
|
; VI-NEXT: v_perm_b32 v15, v15, v20, s4
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x300, v14
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v19
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
|
|
; VI-NEXT: v_perm_b32 v15, v15, v18, s4
|
|
; VI-NEXT: v_perm_b32 v16, v17, v16, s4
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x300, v15
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x3000000, v3
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x3000000, v4
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x3000000, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x3000000, v6
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x3000000, v10
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x3000000, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x3000000, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x3000000, v13
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x3000000, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x3000000, v15
|
|
; VI-NEXT: .LBB51_3: ; %end
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB51_4:
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_branch .LBB51_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v16f32_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v30
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v29
|
|
; GFX9-NEXT: v_readfirstlane_b32 s8, v28
|
|
; GFX9-NEXT: v_readfirstlane_b32 s9, v27
|
|
; GFX9-NEXT: v_readfirstlane_b32 s10, v26
|
|
; GFX9-NEXT: v_readfirstlane_b32 s11, v25
|
|
; GFX9-NEXT: v_readfirstlane_b32 s12, v24
|
|
; GFX9-NEXT: v_readfirstlane_b32 s13, v23
|
|
; GFX9-NEXT: v_readfirstlane_b32 s14, v22
|
|
; GFX9-NEXT: v_readfirstlane_b32 s15, v21
|
|
; GFX9-NEXT: v_readfirstlane_b32 s40, v20
|
|
; GFX9-NEXT: v_readfirstlane_b32 s41, v19
|
|
; GFX9-NEXT: v_readfirstlane_b32 s42, v18
|
|
; GFX9-NEXT: v_readfirstlane_b32 s43, v17
|
|
; GFX9-NEXT: v_readfirstlane_b32 s44, v16
|
|
; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s46, v14
|
|
; GFX9-NEXT: v_readfirstlane_b32 s47, v13
|
|
; GFX9-NEXT: v_readfirstlane_b32 s56, v12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s57, v11
|
|
; GFX9-NEXT: v_readfirstlane_b32 s58, v10
|
|
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
|
|
; GFX9-NEXT: v_readfirstlane_b32 s60, v8
|
|
; GFX9-NEXT: v_readfirstlane_b32 s61, v7
|
|
; GFX9-NEXT: v_readfirstlane_b32 s62, v6
|
|
; GFX9-NEXT: v_readfirstlane_b32 s63, v5
|
|
; GFX9-NEXT: v_readfirstlane_b32 s72, v4
|
|
; GFX9-NEXT: v_readfirstlane_b32 s73, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s74, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s75, v1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s76, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s75
|
|
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s63
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s73
|
|
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s59
|
|
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s61
|
|
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s47
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s57
|
|
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s43
|
|
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s45
|
|
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s15
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s41
|
|
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s11
|
|
; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s13
|
|
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s7
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s9
|
|
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
|
|
; GFX9-NEXT: .LBB51_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; GFX9-NEXT: s_movk_i32 s4, 0x300
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_add_u32_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u32_sdwa v3, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u32_sdwa v3, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: s_add_i32 s76, s76, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s75
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_add_u32_sdwa v4, v4, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s73
|
|
; GFX9-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s63
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_add_u32_sdwa v5, v5, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s61
|
|
; GFX9-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s59
|
|
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_add_u32_sdwa v6, v6, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s57
|
|
; GFX9-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s47
|
|
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_add_u32_sdwa v7, v7, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s45
|
|
; GFX9-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s43
|
|
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_add_u32_sdwa v8, v8, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s41
|
|
; GFX9-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s15
|
|
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 0x300, v8
|
|
; GFX9-NEXT: v_add_u32_sdwa v9, v9, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s13
|
|
; GFX9-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s11
|
|
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 0x300, v9
|
|
; GFX9-NEXT: v_add_u32_sdwa v10, v10, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s9
|
|
; GFX9-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s7
|
|
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
|
|
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v23
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v21, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v11
|
|
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v34
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v32
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v33, s5
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v31, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v12
|
|
; GFX9-NEXT: v_add_u32_sdwa v13, v13, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v30
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v28
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v29, s5
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v27, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v26
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v22
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v24, s5
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v20, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v14
|
|
; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v18, s5
|
|
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v15
|
|
; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: .LBB51_3: ; %end
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB51_4:
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_branch .LBB51_2
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v16f32_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0xf
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3
|
|
; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s24, s25, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s28, s29, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s74, s73, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s62, s61, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s58, s57, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s46, s45, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s42, s41, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s14, s13, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s12, s11, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s10, s9, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v13
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v14, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-TRUE16-NEXT: .LBB51_3: ; %end
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB51_4:
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB51_2
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v16f32_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_clause 0xf
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v30
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v29
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v28
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v27
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v26
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v25
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v24
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v23
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v22
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v21
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v19
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v18
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v16
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v15
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v14
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v13
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v12
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v11
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v10
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v9
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v8
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v7
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v6
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v5
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v4
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v3
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v2
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB51_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB51_3
|
|
; GFX11-FAKE16-NEXT: .LBB51_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s24, s25, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s26, s27, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s28, s29, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s74, s73, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s62, s61, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s58, s57, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s46, s45, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s42, s41, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s13, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s12, s11, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s10, s9, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v13
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v14, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v51
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s8, s7, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s6, s5, v11
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s4, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-FAKE16-NEXT: .LBB51_3: ; %end
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB51_4:
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB51_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <16 x float>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <16 x float>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <16 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <16 x float> %phi
|
|
}
|
|
|
|
define <8 x double> @bitcast_v8i64_to_v8f64(<8 x i64> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v8f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB52_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; SI-NEXT: .LBB52_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v8f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB52_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; VI-NEXT: .LBB52_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v8f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB52_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
|
|
; GFX9-NEXT: .LBB52_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v8f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB52_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
|
|
; GFX11-NEXT: .LBB52_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define inreg <8 x double> @bitcast_v8i64_to_v8f64_scalar(<8 x i64> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v8f64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB53_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB53_3
|
|
; SI-NEXT: .LBB53_2: ; %cmp.true
|
|
; SI-NEXT: s_add_u32 s16, s16, 3
|
|
; SI-NEXT: s_addc_u32 s17, s17, 0
|
|
; SI-NEXT: s_add_u32 s18, s18, 3
|
|
; SI-NEXT: s_addc_u32 s19, s19, 0
|
|
; SI-NEXT: s_add_u32 s20, s20, 3
|
|
; SI-NEXT: s_addc_u32 s21, s21, 0
|
|
; SI-NEXT: s_add_u32 s22, s22, 3
|
|
; SI-NEXT: s_addc_u32 s23, s23, 0
|
|
; SI-NEXT: s_add_u32 s24, s24, 3
|
|
; SI-NEXT: s_addc_u32 s25, s25, 0
|
|
; SI-NEXT: s_add_u32 s26, s26, 3
|
|
; SI-NEXT: s_addc_u32 s27, s27, 0
|
|
; SI-NEXT: s_add_u32 s28, s28, 3
|
|
; SI-NEXT: s_addc_u32 s29, s29, 0
|
|
; SI-NEXT: s_add_u32 s7, s7, 3
|
|
; SI-NEXT: s_addc_u32 s6, s6, 0
|
|
; SI-NEXT: .LBB53_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s7
|
|
; SI-NEXT: v_mov_b32_e32 v15, s6
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB53_4:
|
|
; SI-NEXT: s_branch .LBB53_2
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v8f64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB53_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB53_3
|
|
; VI-NEXT: .LBB53_2: ; %cmp.true
|
|
; VI-NEXT: s_add_u32 s16, s16, 3
|
|
; VI-NEXT: s_addc_u32 s17, s17, 0
|
|
; VI-NEXT: s_add_u32 s18, s18, 3
|
|
; VI-NEXT: s_addc_u32 s19, s19, 0
|
|
; VI-NEXT: s_add_u32 s20, s20, 3
|
|
; VI-NEXT: s_addc_u32 s21, s21, 0
|
|
; VI-NEXT: s_add_u32 s22, s22, 3
|
|
; VI-NEXT: s_addc_u32 s23, s23, 0
|
|
; VI-NEXT: s_add_u32 s24, s24, 3
|
|
; VI-NEXT: s_addc_u32 s25, s25, 0
|
|
; VI-NEXT: s_add_u32 s26, s26, 3
|
|
; VI-NEXT: s_addc_u32 s27, s27, 0
|
|
; VI-NEXT: s_add_u32 s28, s28, 3
|
|
; VI-NEXT: s_addc_u32 s29, s29, 0
|
|
; VI-NEXT: s_add_u32 s7, s7, 3
|
|
; VI-NEXT: s_addc_u32 s6, s6, 0
|
|
; VI-NEXT: .LBB53_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB53_4:
|
|
; VI-NEXT: s_branch .LBB53_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v8f64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB53_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB53_3
|
|
; GFX9-NEXT: .LBB53_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX9-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX9-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX9-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX9-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX9-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX9-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX9-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX9-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX9-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX9-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX9-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX9-NEXT: s_add_u32 s28, s28, 3
|
|
; GFX9-NEXT: s_addc_u32 s29, s29, 0
|
|
; GFX9-NEXT: s_add_u32 s7, s7, 3
|
|
; GFX9-NEXT: s_addc_u32 s6, s6, 0
|
|
; GFX9-NEXT: .LBB53_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB53_4:
|
|
; GFX9-NEXT: s_branch .LBB53_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v8f64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB53_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB53_3
|
|
; GFX11-NEXT: .LBB53_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_u32 s0, s0, 3
|
|
; GFX11-NEXT: s_addc_u32 s1, s1, 0
|
|
; GFX11-NEXT: s_add_u32 s2, s2, 3
|
|
; GFX11-NEXT: s_addc_u32 s3, s3, 0
|
|
; GFX11-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX11-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX11-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX11-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX11-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX11-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX11-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX11-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX11-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX11-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX11-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX11-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX11-NEXT: .LBB53_3: ; %end
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB53_4:
|
|
; GFX11-NEXT: s_branch .LBB53_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define <8 x i64> @bitcast_v8f64_to_v8i64(<8 x double> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v8i64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB54_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; SI-NEXT: .LBB54_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v8i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB54_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; VI-NEXT: .LBB54_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v8i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB54_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX9-NEXT: .LBB54_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v8i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB54_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX11-NEXT: .LBB54_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define inreg <8 x i64> @bitcast_v8f64_to_v8i64_scalar(<8 x double> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v8i64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB55_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB55_4
|
|
; SI-NEXT: .LBB55_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; SI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; SI-NEXT: s_branch .LBB55_5
|
|
; SI-NEXT: .LBB55_3:
|
|
; SI-NEXT: s_branch .LBB55_2
|
|
; SI-NEXT: .LBB55_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v14, s30
|
|
; SI-NEXT: v_mov_b32_e32 v15, s31
|
|
; SI-NEXT: .LBB55_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; SI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v8i64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB55_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB55_4
|
|
; VI-NEXT: .LBB55_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; VI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; VI-NEXT: s_branch .LBB55_5
|
|
; VI-NEXT: .LBB55_3:
|
|
; VI-NEXT: s_branch .LBB55_2
|
|
; VI-NEXT: .LBB55_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB55_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v8i64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB55_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB55_4
|
|
; GFX9-NEXT: .LBB55_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; GFX9-NEXT: s_branch .LBB55_5
|
|
; GFX9-NEXT: .LBB55_3:
|
|
; GFX9-NEXT: s_branch .LBB55_2
|
|
; GFX9-NEXT: .LBB55_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB55_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v8i64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB55_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB55_4
|
|
; GFX11-NEXT: .LBB55_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[14:15], s[26:27], 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB55_3:
|
|
; GFX11-NEXT: s_branch .LBB55_2
|
|
; GFX11-NEXT: .LBB55_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define <32 x i16> @bitcast_v8i64_to_v32i16(<8 x i64> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v32i16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB56_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v21, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB56_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB56_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v21, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB56_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v24
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v21
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v22
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v27
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v24
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v21
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v32i16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB56_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: .LBB56_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v32i16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB56_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: .LBB56_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v32i16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB56_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
|
|
; GFX11-NEXT: .LBB56_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define inreg <32 x i16> @bitcast_v8i64_to_v32i16_scalar(<8 x i64> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v32i16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB57_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s56, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB57_3
|
|
; SI-NEXT: .LBB57_2: ; %cmp.true
|
|
; SI-NEXT: s_add_u32 s4, s4, 3
|
|
; SI-NEXT: s_addc_u32 s5, s5, 0
|
|
; SI-NEXT: s_add_u32 s28, s28, 3
|
|
; SI-NEXT: s_addc_u32 s29, s29, 0
|
|
; SI-NEXT: s_add_u32 s26, s26, 3
|
|
; SI-NEXT: s_addc_u32 s27, s27, 0
|
|
; SI-NEXT: s_add_u32 s24, s24, 3
|
|
; SI-NEXT: s_addc_u32 s25, s25, 0
|
|
; SI-NEXT: s_add_u32 s22, s22, 3
|
|
; SI-NEXT: s_addc_u32 s23, s23, 0
|
|
; SI-NEXT: s_add_u32 s20, s20, 3
|
|
; SI-NEXT: s_addc_u32 s21, s21, 0
|
|
; SI-NEXT: s_add_u32 s18, s18, 3
|
|
; SI-NEXT: s_addc_u32 s19, s19, 0
|
|
; SI-NEXT: s_add_u32 s16, s16, 3
|
|
; SI-NEXT: s_addc_u32 s17, s17, 0
|
|
; SI-NEXT: s_lshr_b32 s56, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: .LBB57_3: ; %end
|
|
; SI-NEXT: s_and_b32 s7, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s44, 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s11, s63, 16
|
|
; SI-NEXT: s_or_b32 s9, s9, s11
|
|
; SI-NEXT: s_and_b32 s11, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s13, s42, 16
|
|
; SI-NEXT: s_or_b32 s11, s11, s13
|
|
; SI-NEXT: s_and_b32 s13, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s15, s62, 16
|
|
; SI-NEXT: s_or_b32 s13, s13, s15
|
|
; SI-NEXT: s_and_b32 s15, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s40, 16
|
|
; SI-NEXT: s_or_b32 s15, s15, s16
|
|
; SI-NEXT: s_and_b32 s16, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s17, s61, 16
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_or_b32 s14, s17, s14
|
|
; SI-NEXT: s_and_b32 s17, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s18, s60, 16
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_and_b32 s18, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_or_b32 s12, s18, s12
|
|
; SI-NEXT: s_and_b32 s18, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s19, s59, 16
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_and_b32 s19, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_or_b32 s10, s19, s10
|
|
; SI-NEXT: s_and_b32 s19, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s58, 16
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_and_b32 s20, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_or_b32 s8, s20, s8
|
|
; SI-NEXT: s_and_b32 s20, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s21, s57, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s56, 16
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_or_b32 s5, s5, s6
|
|
; SI-NEXT: v_mov_b32_e32 v0, s7
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
|
; SI-NEXT: v_mov_b32_e32 v2, s11
|
|
; SI-NEXT: v_mov_b32_e32 v3, s13
|
|
; SI-NEXT: v_mov_b32_e32 v4, s15
|
|
; SI-NEXT: v_mov_b32_e32 v5, s16
|
|
; SI-NEXT: v_mov_b32_e32 v6, s14
|
|
; SI-NEXT: v_mov_b32_e32 v7, s17
|
|
; SI-NEXT: v_mov_b32_e32 v8, s12
|
|
; SI-NEXT: v_mov_b32_e32 v9, s18
|
|
; SI-NEXT: v_mov_b32_e32 v10, s10
|
|
; SI-NEXT: v_mov_b32_e32 v11, s19
|
|
; SI-NEXT: v_mov_b32_e32 v12, s8
|
|
; SI-NEXT: v_mov_b32_e32 v13, s20
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB57_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: s_branch .LBB57_2
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v32i16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB57_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB57_3
|
|
; VI-NEXT: .LBB57_2: ; %cmp.true
|
|
; VI-NEXT: s_add_u32 s7, s7, 3
|
|
; VI-NEXT: s_addc_u32 s6, s6, 0
|
|
; VI-NEXT: s_add_u32 s28, s28, 3
|
|
; VI-NEXT: s_addc_u32 s29, s29, 0
|
|
; VI-NEXT: s_add_u32 s26, s26, 3
|
|
; VI-NEXT: s_addc_u32 s27, s27, 0
|
|
; VI-NEXT: s_add_u32 s24, s24, 3
|
|
; VI-NEXT: s_addc_u32 s25, s25, 0
|
|
; VI-NEXT: s_add_u32 s22, s22, 3
|
|
; VI-NEXT: s_addc_u32 s23, s23, 0
|
|
; VI-NEXT: s_add_u32 s20, s20, 3
|
|
; VI-NEXT: s_addc_u32 s21, s21, 0
|
|
; VI-NEXT: s_add_u32 s18, s18, 3
|
|
; VI-NEXT: s_addc_u32 s19, s19, 0
|
|
; VI-NEXT: s_add_u32 s16, s16, 3
|
|
; VI-NEXT: s_addc_u32 s17, s17, 0
|
|
; VI-NEXT: .LBB57_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB57_4:
|
|
; VI-NEXT: s_branch .LBB57_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v32i16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB57_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB57_3
|
|
; GFX9-NEXT: .LBB57_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_u32 s7, s7, 3
|
|
; GFX9-NEXT: s_addc_u32 s6, s6, 0
|
|
; GFX9-NEXT: s_add_u32 s28, s28, 3
|
|
; GFX9-NEXT: s_addc_u32 s29, s29, 0
|
|
; GFX9-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX9-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX9-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX9-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX9-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX9-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX9-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX9-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX9-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX9-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX9-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX9-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX9-NEXT: .LBB57_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB57_4:
|
|
; GFX9-NEXT: s_branch .LBB57_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v32i16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB57_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB57_3
|
|
; GFX11-NEXT: .LBB57_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX11-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX11-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX11-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX11-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX11-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX11-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX11-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX11-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX11-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX11-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX11-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX11-NEXT: s_add_u32 s2, s2, 3
|
|
; GFX11-NEXT: s_addc_u32 s3, s3, 0
|
|
; GFX11-NEXT: s_add_u32 s0, s0, 3
|
|
; GFX11-NEXT: s_addc_u32 s1, s1, 0
|
|
; GFX11-NEXT: .LBB57_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB57_4:
|
|
; GFX11-NEXT: s_branch .LBB57_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define <8 x i64> @bitcast_v32i16_to_v8i64(<32 x i16> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v8i64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v32, v15
|
|
; SI-NEXT: v_mov_b32_e32 v17, v14
|
|
; SI-NEXT: v_mov_b32_e32 v18, v13
|
|
; SI-NEXT: v_mov_b32_e32 v19, v12
|
|
; SI-NEXT: v_mov_b32_e32 v20, v11
|
|
; SI-NEXT: v_mov_b32_e32 v21, v10
|
|
; SI-NEXT: v_mov_b32_e32 v22, v9
|
|
; SI-NEXT: v_mov_b32_e32 v23, v8
|
|
; SI-NEXT: v_mov_b32_e32 v24, v7
|
|
; SI-NEXT: v_mov_b32_e32 v25, v6
|
|
; SI-NEXT: v_mov_b32_e32 v26, v5
|
|
; SI-NEXT: v_mov_b32_e32 v27, v4
|
|
; SI-NEXT: v_mov_b32_e32 v28, v3
|
|
; SI-NEXT: v_mov_b32_e32 v29, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB58_3
|
|
; SI-NEXT: ; %bb.1: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB58_4
|
|
; SI-NEXT: .LBB58_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB58_3: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v55
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v54
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v53
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v51
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v50
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v49
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v39
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v38
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v36
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v35
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v34
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v33
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB58_2
|
|
; SI-NEXT: .LBB58_4: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_or_b32_e32 v0, v55, v0
|
|
; SI-NEXT: s_mov_b32 s6, 0x30000
|
|
; SI-NEXT: v_or_b32_e32 v1, v54, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v53, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v52, v3
|
|
; SI-NEXT: v_or_b32_e32 v4, v51, v4
|
|
; SI-NEXT: v_or_b32_e32 v5, v50, v5
|
|
; SI-NEXT: v_or_b32_e32 v6, v49, v6
|
|
; SI-NEXT: v_or_b32_e32 v7, v48, v7
|
|
; SI-NEXT: v_or_b32_e32 v8, v39, v8
|
|
; SI-NEXT: v_or_b32_e32 v9, v38, v9
|
|
; SI-NEXT: v_or_b32_e32 v10, v37, v10
|
|
; SI-NEXT: v_or_b32_e32 v11, v36, v11
|
|
; SI-NEXT: v_or_b32_e32 v12, v35, v12
|
|
; SI-NEXT: v_or_b32_e32 v13, v34, v13
|
|
; SI-NEXT: v_or_b32_e32 v14, v33, v14
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v8i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB58_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v17, 3
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v15
|
|
; VI-NEXT: v_add_u16_sdwa v15, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v14
|
|
; VI-NEXT: v_add_u16_sdwa v14, v14, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v16, v14
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v13
|
|
; VI-NEXT: v_add_u16_sdwa v13, v13, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v16, v13
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v12
|
|
; VI-NEXT: v_add_u16_sdwa v12, v12, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v11
|
|
; VI-NEXT: v_add_u16_sdwa v11, v11, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v16, v11
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v10
|
|
; VI-NEXT: v_add_u16_sdwa v10, v10, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v16, v10
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v9
|
|
; VI-NEXT: v_add_u16_sdwa v9, v9, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v16, v9
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v8
|
|
; VI-NEXT: v_add_u16_sdwa v8, v8, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v16, v8
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v7
|
|
; VI-NEXT: v_add_u16_sdwa v7, v7, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v16, v7
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v6
|
|
; VI-NEXT: v_add_u16_sdwa v6, v6, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v16, v6
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v5
|
|
; VI-NEXT: v_add_u16_sdwa v5, v5, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v16, v5
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v4
|
|
; VI-NEXT: v_add_u16_sdwa v4, v4, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v3
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v3, v16, v3
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v2
|
|
; VI-NEXT: v_add_u16_sdwa v2, v2, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v16, v2
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v1
|
|
; VI-NEXT: v_add_u16_sdwa v1, v1, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v16, v0
|
|
; VI-NEXT: .LBB58_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v8i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB58_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB58_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v8i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB58_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: .LBB58_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define inreg <8 x i64> @bitcast_v32i16_to_v8i64_scalar(<32 x i16> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v8i64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s36, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s37, 1
|
|
; SI-NEXT: v_writelane_b32 v16, s38, 2
|
|
; SI-NEXT: v_writelane_b32 v16, s39, 3
|
|
; SI-NEXT: v_writelane_b32 v16, s48, 4
|
|
; SI-NEXT: v_writelane_b32 v16, s49, 5
|
|
; SI-NEXT: v_writelane_b32 v16, s50, 6
|
|
; SI-NEXT: v_writelane_b32 v16, s51, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v0
|
|
; SI-NEXT: s_lshr_b32 s6, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s8, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s9, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s12, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB59_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s36, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s37, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s38, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s39, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s44, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s45, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s46, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s47, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 16
|
|
; SI-NEXT: s_or_b32 s48, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 16
|
|
; SI-NEXT: s_or_b32 s49, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s50, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s51, s4, s5
|
|
; SI-NEXT: s_cbranch_execnz .LBB59_3
|
|
; SI-NEXT: .LBB59_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s36, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s37, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s38, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s39, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s40, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s41, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s42, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s43, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s44, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s45, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s46, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s47, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s48, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_add_i32 s49, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s9, s9, 3
|
|
; SI-NEXT: s_add_i32 s50, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s51, s4, 0x30000
|
|
; SI-NEXT: .LBB59_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s39
|
|
; SI-NEXT: v_mov_b32_e32 v4, s40
|
|
; SI-NEXT: v_mov_b32_e32 v5, s41
|
|
; SI-NEXT: v_mov_b32_e32 v6, s42
|
|
; SI-NEXT: v_mov_b32_e32 v7, s43
|
|
; SI-NEXT: v_mov_b32_e32 v8, s44
|
|
; SI-NEXT: v_mov_b32_e32 v9, s45
|
|
; SI-NEXT: v_mov_b32_e32 v10, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s47
|
|
; SI-NEXT: v_mov_b32_e32 v12, s48
|
|
; SI-NEXT: v_mov_b32_e32 v13, s49
|
|
; SI-NEXT: v_mov_b32_e32 v14, s50
|
|
; SI-NEXT: v_mov_b32_e32 v15, s51
|
|
; SI-NEXT: v_readlane_b32 s51, v16, 7
|
|
; SI-NEXT: v_readlane_b32 s50, v16, 6
|
|
; SI-NEXT: v_readlane_b32 s49, v16, 5
|
|
; SI-NEXT: v_readlane_b32 s48, v16, 4
|
|
; SI-NEXT: v_readlane_b32 s39, v16, 3
|
|
; SI-NEXT: v_readlane_b32 s38, v16, 2
|
|
; SI-NEXT: v_readlane_b32 s37, v16, 1
|
|
; SI-NEXT: v_readlane_b32 s36, v16, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB59_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
|
|
; SI-NEXT: s_branch .LBB59_2
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v8i64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB59_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB59_3
|
|
; VI-NEXT: .LBB59_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s5, s6, 3
|
|
; VI-NEXT: s_and_b32 s4, s6, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s7, 3
|
|
; VI-NEXT: s_add_i32 s6, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s7, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s29, 3
|
|
; VI-NEXT: s_add_i32 s7, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s28, 3
|
|
; VI-NEXT: s_add_i32 s29, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s27, 3
|
|
; VI-NEXT: s_add_i32 s28, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s26, 3
|
|
; VI-NEXT: s_add_i32 s27, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s25, 3
|
|
; VI-NEXT: s_add_i32 s26, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s24, 3
|
|
; VI-NEXT: s_add_i32 s25, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s23, 3
|
|
; VI-NEXT: s_add_i32 s24, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s22, 3
|
|
; VI-NEXT: s_add_i32 s23, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s21, 3
|
|
; VI-NEXT: s_add_i32 s22, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s20, 3
|
|
; VI-NEXT: s_add_i32 s21, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s19, 3
|
|
; VI-NEXT: s_add_i32 s20, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s18, 3
|
|
; VI-NEXT: s_add_i32 s19, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s17, 3
|
|
; VI-NEXT: s_add_i32 s18, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s16, 3
|
|
; VI-NEXT: s_add_i32 s17, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s16, s4, 0x30000
|
|
; VI-NEXT: .LBB59_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB59_4:
|
|
; VI-NEXT: s_branch .LBB59_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v8i64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB59_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB59_4
|
|
; GFX9-NEXT: .LBB59_2: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, s31, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, s30, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB59_5
|
|
; GFX9-NEXT: .LBB59_3:
|
|
; GFX9-NEXT: s_branch .LBB59_2
|
|
; GFX9-NEXT: .LBB59_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB59_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v8i64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB59_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB59_4
|
|
; GFX11-NEXT: .LBB59_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB59_3:
|
|
; GFX11-NEXT: s_branch .LBB59_2
|
|
; GFX11-NEXT: .LBB59_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define <32 x half> @bitcast_v8i64_to_v32f16(<8 x i64> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v32f16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB60_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v21, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB60_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB60_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v21, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v24, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB60_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v24
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v21
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v22
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v27
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v24
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v21
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v32f16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB60_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: .LBB60_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v32f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB60_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: .LBB60_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v32f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB60_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
|
|
; GFX11-NEXT: .LBB60_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define inreg <32 x half> @bitcast_v8i64_to_v32f16_scalar(<8 x i64> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v32f16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB61_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s56, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB61_3
|
|
; SI-NEXT: .LBB61_2: ; %cmp.true
|
|
; SI-NEXT: s_add_u32 s4, s4, 3
|
|
; SI-NEXT: s_addc_u32 s5, s5, 0
|
|
; SI-NEXT: s_add_u32 s28, s28, 3
|
|
; SI-NEXT: s_addc_u32 s29, s29, 0
|
|
; SI-NEXT: s_add_u32 s26, s26, 3
|
|
; SI-NEXT: s_addc_u32 s27, s27, 0
|
|
; SI-NEXT: s_add_u32 s24, s24, 3
|
|
; SI-NEXT: s_addc_u32 s25, s25, 0
|
|
; SI-NEXT: s_add_u32 s22, s22, 3
|
|
; SI-NEXT: s_addc_u32 s23, s23, 0
|
|
; SI-NEXT: s_add_u32 s20, s20, 3
|
|
; SI-NEXT: s_addc_u32 s21, s21, 0
|
|
; SI-NEXT: s_add_u32 s18, s18, 3
|
|
; SI-NEXT: s_addc_u32 s19, s19, 0
|
|
; SI-NEXT: s_add_u32 s16, s16, 3
|
|
; SI-NEXT: s_addc_u32 s17, s17, 0
|
|
; SI-NEXT: s_lshr_b32 s56, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: .LBB61_3: ; %end
|
|
; SI-NEXT: s_and_b32 s7, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s44, 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s11, s63, 16
|
|
; SI-NEXT: s_or_b32 s9, s9, s11
|
|
; SI-NEXT: s_and_b32 s11, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s13, s42, 16
|
|
; SI-NEXT: s_or_b32 s11, s11, s13
|
|
; SI-NEXT: s_and_b32 s13, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s15, s62, 16
|
|
; SI-NEXT: s_or_b32 s13, s13, s15
|
|
; SI-NEXT: s_and_b32 s15, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s40, 16
|
|
; SI-NEXT: s_or_b32 s15, s15, s16
|
|
; SI-NEXT: s_and_b32 s16, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s17, s61, 16
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_or_b32 s14, s17, s14
|
|
; SI-NEXT: s_and_b32 s17, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s18, s60, 16
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_and_b32 s18, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_or_b32 s12, s18, s12
|
|
; SI-NEXT: s_and_b32 s18, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s19, s59, 16
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_and_b32 s19, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_or_b32 s10, s19, s10
|
|
; SI-NEXT: s_and_b32 s19, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s58, 16
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_and_b32 s20, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_or_b32 s8, s20, s8
|
|
; SI-NEXT: s_and_b32 s20, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s21, s57, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s56, 16
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_or_b32 s5, s5, s6
|
|
; SI-NEXT: v_mov_b32_e32 v0, s7
|
|
; SI-NEXT: v_mov_b32_e32 v1, s9
|
|
; SI-NEXT: v_mov_b32_e32 v2, s11
|
|
; SI-NEXT: v_mov_b32_e32 v3, s13
|
|
; SI-NEXT: v_mov_b32_e32 v4, s15
|
|
; SI-NEXT: v_mov_b32_e32 v5, s16
|
|
; SI-NEXT: v_mov_b32_e32 v6, s14
|
|
; SI-NEXT: v_mov_b32_e32 v7, s17
|
|
; SI-NEXT: v_mov_b32_e32 v8, s12
|
|
; SI-NEXT: v_mov_b32_e32 v9, s18
|
|
; SI-NEXT: v_mov_b32_e32 v10, s10
|
|
; SI-NEXT: v_mov_b32_e32 v11, s19
|
|
; SI-NEXT: v_mov_b32_e32 v12, s8
|
|
; SI-NEXT: v_mov_b32_e32 v13, s20
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB61_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: s_branch .LBB61_2
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v32f16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB61_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB61_3
|
|
; VI-NEXT: .LBB61_2: ; %cmp.true
|
|
; VI-NEXT: s_add_u32 s7, s7, 3
|
|
; VI-NEXT: s_addc_u32 s6, s6, 0
|
|
; VI-NEXT: s_add_u32 s28, s28, 3
|
|
; VI-NEXT: s_addc_u32 s29, s29, 0
|
|
; VI-NEXT: s_add_u32 s26, s26, 3
|
|
; VI-NEXT: s_addc_u32 s27, s27, 0
|
|
; VI-NEXT: s_add_u32 s24, s24, 3
|
|
; VI-NEXT: s_addc_u32 s25, s25, 0
|
|
; VI-NEXT: s_add_u32 s22, s22, 3
|
|
; VI-NEXT: s_addc_u32 s23, s23, 0
|
|
; VI-NEXT: s_add_u32 s20, s20, 3
|
|
; VI-NEXT: s_addc_u32 s21, s21, 0
|
|
; VI-NEXT: s_add_u32 s18, s18, 3
|
|
; VI-NEXT: s_addc_u32 s19, s19, 0
|
|
; VI-NEXT: s_add_u32 s16, s16, 3
|
|
; VI-NEXT: s_addc_u32 s17, s17, 0
|
|
; VI-NEXT: .LBB61_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB61_4:
|
|
; VI-NEXT: s_branch .LBB61_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v32f16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB61_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB61_3
|
|
; GFX9-NEXT: .LBB61_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_u32 s7, s7, 3
|
|
; GFX9-NEXT: s_addc_u32 s6, s6, 0
|
|
; GFX9-NEXT: s_add_u32 s28, s28, 3
|
|
; GFX9-NEXT: s_addc_u32 s29, s29, 0
|
|
; GFX9-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX9-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX9-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX9-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX9-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX9-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX9-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX9-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX9-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX9-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX9-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX9-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX9-NEXT: .LBB61_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB61_4:
|
|
; GFX9-NEXT: s_branch .LBB61_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v32f16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB61_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB61_3
|
|
; GFX11-NEXT: .LBB61_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX11-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX11-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX11-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX11-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX11-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX11-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX11-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX11-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX11-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX11-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX11-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX11-NEXT: s_add_u32 s2, s2, 3
|
|
; GFX11-NEXT: s_addc_u32 s3, s3, 0
|
|
; GFX11-NEXT: s_add_u32 s0, s0, 3
|
|
; GFX11-NEXT: s_addc_u32 s1, s1, 0
|
|
; GFX11-NEXT: .LBB61_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB61_4:
|
|
; GFX11-NEXT: s_branch .LBB61_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define <8 x i64> @bitcast_v32f16_to_v8i64(<32 x half> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v8i64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v32, v15
|
|
; SI-NEXT: v_mov_b32_e32 v17, v14
|
|
; SI-NEXT: v_mov_b32_e32 v18, v13
|
|
; SI-NEXT: v_mov_b32_e32 v19, v12
|
|
; SI-NEXT: v_mov_b32_e32 v20, v11
|
|
; SI-NEXT: v_mov_b32_e32 v21, v10
|
|
; SI-NEXT: v_mov_b32_e32 v22, v9
|
|
; SI-NEXT: v_mov_b32_e32 v23, v8
|
|
; SI-NEXT: v_mov_b32_e32 v24, v7
|
|
; SI-NEXT: v_mov_b32_e32 v25, v6
|
|
; SI-NEXT: v_mov_b32_e32 v26, v5
|
|
; SI-NEXT: v_mov_b32_e32 v27, v4
|
|
; SI-NEXT: v_mov_b32_e32 v28, v3
|
|
; SI-NEXT: v_mov_b32_e32 v29, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v31
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB62_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: .LBB62_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB62_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v40
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v55
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v31
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v30
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v54
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v29
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v53
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v28
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v27
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v52
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v26
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v50
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v49
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v24
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v48
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v23
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v39
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v22
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v38
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v21
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_or_b32_e32 v9, v11, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v37
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v20
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v36
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v35
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v18
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_or_b32_e32 v12, v14, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v33
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v32
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; SI-NEXT: .LBB62_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v8i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB62_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x200
|
|
; VI-NEXT: v_add_f16_sdwa v17, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v13, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v12, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v11, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v10, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v9, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v8, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v7, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v6, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v5, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v4, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v3, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v1, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
|
|
; VI-NEXT: v_add_f16_sdwa v16, v0, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v17
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: .LBB62_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v8i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB62_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB62_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v8i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB62_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: .LBB62_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define inreg <8 x i64> @bitcast_v32f16_to_v8i64_scalar(<32 x half> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v8i64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v18, s36, 0
|
|
; SI-NEXT: v_writelane_b32 v18, s37, 1
|
|
; SI-NEXT: v_writelane_b32 v18, s38, 2
|
|
; SI-NEXT: v_writelane_b32 v18, s39, 3
|
|
; SI-NEXT: v_writelane_b32 v18, s48, 4
|
|
; SI-NEXT: v_writelane_b32 v18, s49, 5
|
|
; SI-NEXT: v_writelane_b32 v18, s50, 6
|
|
; SI-NEXT: v_writelane_b32 v18, s51, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v0
|
|
; SI-NEXT: s_lshr_b32 s9, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s12, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s6, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s8, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB63_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s36, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s37, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s38, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s39, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s44, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s45, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s46, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s12, 16
|
|
; SI-NEXT: s_or_b32 s47, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s48, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s9, 16
|
|
; SI-NEXT: s_or_b32 s49, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s8, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s50, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s51, s4, s5
|
|
; SI-NEXT: s_cbranch_execnz .LBB63_4
|
|
; SI-NEXT: .LBB63_2: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s63
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s62
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s17
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s61
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s18
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s60
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s19
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s59
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s21
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s57
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s22
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s56
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s23
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s24
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s14
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s25
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s26
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_or_b32_e32 v9, v11, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s27
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s11
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s28
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_or_b32_e32 v12, v14, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, s7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, s6
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; SI-NEXT: s_branch .LBB63_5
|
|
; SI-NEXT: .LBB63_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
|
|
; SI-NEXT: s_branch .LBB63_2
|
|
; SI-NEXT: .LBB63_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s39
|
|
; SI-NEXT: v_mov_b32_e32 v4, s40
|
|
; SI-NEXT: v_mov_b32_e32 v5, s41
|
|
; SI-NEXT: v_mov_b32_e32 v6, s42
|
|
; SI-NEXT: v_mov_b32_e32 v7, s43
|
|
; SI-NEXT: v_mov_b32_e32 v8, s44
|
|
; SI-NEXT: v_mov_b32_e32 v9, s45
|
|
; SI-NEXT: v_mov_b32_e32 v10, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s47
|
|
; SI-NEXT: v_mov_b32_e32 v12, s48
|
|
; SI-NEXT: v_mov_b32_e32 v13, s49
|
|
; SI-NEXT: v_mov_b32_e32 v14, s50
|
|
; SI-NEXT: v_mov_b32_e32 v15, s51
|
|
; SI-NEXT: .LBB63_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s51, v18, 7
|
|
; SI-NEXT: v_readlane_b32 s50, v18, 6
|
|
; SI-NEXT: v_readlane_b32 s49, v18, 5
|
|
; SI-NEXT: v_readlane_b32 s48, v18, 4
|
|
; SI-NEXT: v_readlane_b32 s39, v18, 3
|
|
; SI-NEXT: v_readlane_b32 s38, v18, 2
|
|
; SI-NEXT: v_readlane_b32 s37, v18, 1
|
|
; SI-NEXT: v_readlane_b32 s36, v18, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v8i64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v17, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v17, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB63_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB63_4
|
|
; VI-NEXT: .LBB63_2: ; %cmp.true
|
|
; VI-NEXT: s_lshr_b32 s4, s31, 16
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s31, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s30, 16
|
|
; VI-NEXT: v_or_b32_e32 v15, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s30, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s29, 16
|
|
; VI-NEXT: v_or_b32_e32 v14, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s29, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s28, 16
|
|
; VI-NEXT: v_or_b32_e32 v13, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s28, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s27, 16
|
|
; VI-NEXT: v_or_b32_e32 v12, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s27, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s26, 16
|
|
; VI-NEXT: v_or_b32_e32 v11, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s26, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s25, 16
|
|
; VI-NEXT: v_or_b32_e32 v10, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s25, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s24, 16
|
|
; VI-NEXT: v_or_b32_e32 v9, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s24, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s23, 16
|
|
; VI-NEXT: v_or_b32_e32 v8, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s23, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s22, 16
|
|
; VI-NEXT: v_or_b32_e32 v7, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s22, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s21, 16
|
|
; VI-NEXT: v_or_b32_e32 v6, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s21, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s20, 16
|
|
; VI-NEXT: v_or_b32_e32 v5, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s20, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s19, 16
|
|
; VI-NEXT: v_or_b32_e32 v4, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s19, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s18, 16
|
|
; VI-NEXT: v_or_b32_e32 v3, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s18, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s17, 16
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v16, s17, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s16, 16
|
|
; VI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; VI-NEXT: v_mov_b32_e32 v16, s4
|
|
; VI-NEXT: v_add_f16_sdwa v16, v16, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v0, s16, v0
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: s_branch .LBB63_5
|
|
; VI-NEXT: .LBB63_3:
|
|
; VI-NEXT: s_branch .LBB63_2
|
|
; VI-NEXT: .LBB63_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB63_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v17, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v17, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v8i64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB63_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB63_4
|
|
; GFX9-NEXT: .LBB63_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, s31, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, s30, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB63_5
|
|
; GFX9-NEXT: .LBB63_3:
|
|
; GFX9-NEXT: s_branch .LBB63_2
|
|
; GFX9-NEXT: .LBB63_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB63_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v8i64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB63_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB63_4
|
|
; GFX11-NEXT: .LBB63_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB63_3:
|
|
; GFX11-NEXT: s_branch .LBB63_2
|
|
; GFX11-NEXT: .LBB63_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define <32 x bfloat> @bitcast_v8i64_to_v32bf16(<8 x i64> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v32bf16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB64_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: .LBB64_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB64_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: .LBB64_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v36
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v35
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v28
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v24
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v22
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v18
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v32bf16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB64_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v14
|
|
; VI-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v12
|
|
; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v10
|
|
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8
|
|
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6
|
|
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4
|
|
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: .LBB64_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v32bf16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB64_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_co_u32_e32 v14, vcc, 3, v14
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v12, vcc, 3, v12
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, 0, v13, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, 3, v10
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, 3, v8
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 3, v6
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GFX9-NEXT: .LBB64_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v32bf16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB64_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_co_u32 v14, vcc_lo, v14, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v15, null, 0, v15, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v12, vcc_lo, v12, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v13, null, 0, v13, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v10, vcc_lo, v10, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v11, null, 0, v11, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v8, vcc_lo, v8, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v9, null, 0, v9, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v6, vcc_lo, v6, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v7, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo
|
|
; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3
|
|
; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
|
|
; GFX11-NEXT: .LBB64_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define inreg <32 x bfloat> @bitcast_v8i64_to_v32bf16_scalar(<8 x i64> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v32bf16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s78, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s79, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB65_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s7, s78, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s6, s78, 16
|
|
; SI-NEXT: s_and_b32 s9, s79, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s8, s79, 16
|
|
; SI-NEXT: s_and_b32 s11, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s10, s29, 16
|
|
; SI-NEXT: s_and_b32 s13, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s12, s28, 16
|
|
; SI-NEXT: s_and_b32 s15, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s14, s27, 16
|
|
; SI-NEXT: s_and_b32 s41, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s40, s26, 16
|
|
; SI-NEXT: s_and_b32 s43, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s25, 16
|
|
; SI-NEXT: s_and_b32 s45, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s24, 16
|
|
; SI-NEXT: s_and_b32 s47, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s46, s23, 16
|
|
; SI-NEXT: s_and_b32 s57, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s56, s22, 16
|
|
; SI-NEXT: s_and_b32 s59, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s58, s21, 16
|
|
; SI-NEXT: s_and_b32 s61, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s60, s20, 16
|
|
; SI-NEXT: s_and_b32 s63, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s62, s19, 16
|
|
; SI-NEXT: s_and_b32 s73, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s72, s18, 16
|
|
; SI-NEXT: s_and_b32 s75, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s74, s17, 16
|
|
; SI-NEXT: s_and_b32 s77, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s76, s16, 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB65_3
|
|
; SI-NEXT: .LBB65_2: ; %cmp.true
|
|
; SI-NEXT: s_add_u32 s4, s16, 3
|
|
; SI-NEXT: s_addc_u32 s5, s17, 0
|
|
; SI-NEXT: s_add_u32 s16, s18, 3
|
|
; SI-NEXT: s_addc_u32 s17, s19, 0
|
|
; SI-NEXT: s_add_u32 s18, s20, 3
|
|
; SI-NEXT: s_addc_u32 s19, s21, 0
|
|
; SI-NEXT: s_add_u32 s20, s22, 3
|
|
; SI-NEXT: s_addc_u32 s21, s23, 0
|
|
; SI-NEXT: s_add_u32 s22, s24, 3
|
|
; SI-NEXT: s_addc_u32 s23, s25, 0
|
|
; SI-NEXT: s_add_u32 s24, s26, 3
|
|
; SI-NEXT: s_addc_u32 s14, s27, 0
|
|
; SI-NEXT: s_add_u32 s12, s28, 3
|
|
; SI-NEXT: s_addc_u32 s10, s29, 0
|
|
; SI-NEXT: s_add_u32 s8, s79, 3
|
|
; SI-NEXT: s_addc_u32 s6, s78, 0
|
|
; SI-NEXT: s_and_b32 s7, s6, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_and_b32 s9, s8, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_and_b32 s11, s10, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_and_b32 s13, s12, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_and_b32 s15, s14, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_and_b32 s41, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s40, s24, 16
|
|
; SI-NEXT: s_and_b32 s43, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s23, 16
|
|
; SI-NEXT: s_and_b32 s45, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s22, 16
|
|
; SI-NEXT: s_and_b32 s47, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s46, s21, 16
|
|
; SI-NEXT: s_and_b32 s57, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s56, s20, 16
|
|
; SI-NEXT: s_and_b32 s59, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s58, s19, 16
|
|
; SI-NEXT: s_and_b32 s61, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s60, s18, 16
|
|
; SI-NEXT: s_and_b32 s63, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s62, s17, 16
|
|
; SI-NEXT: s_and_b32 s73, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s72, s16, 16
|
|
; SI-NEXT: s_and_b32 s75, s5, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s74, s5, 16
|
|
; SI-NEXT: s_and_b32 s77, s4, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s76, s4, 16
|
|
; SI-NEXT: .LBB65_3: ; %end
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s77
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s76
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s75
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s74
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s73
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s72
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s63
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s62
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s61
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s60
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s59
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s58
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s56
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s47
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s46
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s45
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s44
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s43
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s42
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s40
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s14
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s12
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s10
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s8
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s6
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB65_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr43
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr41
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr15
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr13
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr11
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr9
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr7
|
|
; SI-NEXT: s_branch .LBB65_2
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v32bf16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB65_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB65_3
|
|
; VI-NEXT: .LBB65_2: ; %cmp.true
|
|
; VI-NEXT: s_add_u32 s7, s7, 3
|
|
; VI-NEXT: s_addc_u32 s6, s6, 0
|
|
; VI-NEXT: s_add_u32 s28, s28, 3
|
|
; VI-NEXT: s_addc_u32 s29, s29, 0
|
|
; VI-NEXT: s_add_u32 s26, s26, 3
|
|
; VI-NEXT: s_addc_u32 s27, s27, 0
|
|
; VI-NEXT: s_add_u32 s24, s24, 3
|
|
; VI-NEXT: s_addc_u32 s25, s25, 0
|
|
; VI-NEXT: s_add_u32 s22, s22, 3
|
|
; VI-NEXT: s_addc_u32 s23, s23, 0
|
|
; VI-NEXT: s_add_u32 s20, s20, 3
|
|
; VI-NEXT: s_addc_u32 s21, s21, 0
|
|
; VI-NEXT: s_add_u32 s18, s18, 3
|
|
; VI-NEXT: s_addc_u32 s19, s19, 0
|
|
; VI-NEXT: s_add_u32 s16, s16, 3
|
|
; VI-NEXT: s_addc_u32 s17, s17, 0
|
|
; VI-NEXT: .LBB65_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB65_4:
|
|
; VI-NEXT: s_branch .LBB65_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v32bf16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB65_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB65_3
|
|
; GFX9-NEXT: .LBB65_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_u32 s7, s7, 3
|
|
; GFX9-NEXT: s_addc_u32 s6, s6, 0
|
|
; GFX9-NEXT: s_add_u32 s28, s28, 3
|
|
; GFX9-NEXT: s_addc_u32 s29, s29, 0
|
|
; GFX9-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX9-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX9-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX9-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX9-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX9-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX9-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX9-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX9-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX9-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX9-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX9-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX9-NEXT: .LBB65_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s7
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s6
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB65_4:
|
|
; GFX9-NEXT: s_branch .LBB65_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v32bf16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s4, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB65_4
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB65_3
|
|
; GFX11-NEXT: .LBB65_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX11-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX11-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX11-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX11-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX11-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX11-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX11-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX11-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX11-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX11-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX11-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX11-NEXT: s_add_u32 s2, s2, 3
|
|
; GFX11-NEXT: s_addc_u32 s3, s3, 0
|
|
; GFX11-NEXT: s_add_u32 s0, s0, 3
|
|
; GFX11-NEXT: s_addc_u32 s1, s1, 0
|
|
; GFX11-NEXT: .LBB65_3: ; %end
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB65_4:
|
|
; GFX11-NEXT: s_branch .LBB65_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define <8 x i64> @bitcast_v32bf16_to_v8i64(<32 x bfloat> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v8i64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_mul_f32_e32 v54, 1.0, v32
|
|
; SI-NEXT: v_mul_f32_e32 v55, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v52, 1.0, v31
|
|
; SI-NEXT: v_mul_f32_e32 v53, 1.0, v1
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v51, 1.0, v2
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v49, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v39, 1.0, v4
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
|
|
; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v35, 1.0, v6
|
|
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v8
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v23
|
|
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v10
|
|
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v23, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v19
|
|
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
|
|
; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB66_3
|
|
; SI-NEXT: ; %bb.1: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB66_4
|
|
; SI-NEXT: .LBB66_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB66_3: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v38
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v55, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v53, 16
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v51, 16
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v49, 16
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v39, 16
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v37, 16
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v35, 16
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v17, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB66_2
|
|
; SI-NEXT: .LBB66_4: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v50
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
|
|
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v38
|
|
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v36
|
|
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v34
|
|
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
|
|
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
|
|
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
|
|
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
|
|
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
|
|
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
|
|
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
|
|
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
|
|
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v8i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB66_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
|
|
; VI-NEXT: s_movk_i32 s6, 0x7fff
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v14
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v14
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_alignbit_b32 v14, v14, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_alignbit_b32 v13, v13, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v12
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v12, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v12
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v12
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_alignbit_b32 v12, v12, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_alignbit_b32 v11, v11, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v10
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v10, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v10
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v10
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_alignbit_b32 v10, v10, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v9
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_alignbit_b32 v9, v9, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v8
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v8
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_alignbit_b32 v8, v8, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v7
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_alignbit_b32 v7, v7, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v6
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v6
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v6
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_alignbit_b32 v6, v6, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v5
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_alignbit_b32 v5, v5, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v4, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v4
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_alignbit_b32 v4, v4, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v3
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_alignbit_b32 v3, v3, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v2
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_alignbit_b32 v2, v2, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v1
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_alignbit_b32 v1, v1, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
|
|
; VI-NEXT: .LBB66_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v8i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB66_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v15, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v15, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v15
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
|
|
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v14, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v14, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v13, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v12, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v12, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v12
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v11, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v10, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v10, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v10
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v10, v10, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v9, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v9
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v8, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v8, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v8
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v7, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v7
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v6, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v6
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v6, v6, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v5, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v4, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v4, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v4, v4, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v3, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v3, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v2, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v1, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v0, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v0, v0, v16, s7
|
|
; GFX9-NEXT: .LBB66_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v8i64:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v30, v14
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
|
|
; GFX11-TRUE16-NEXT: .LBB66_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB66_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v4, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.h
|
|
; GFX11-TRUE16-NEXT: .LBB66_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v8i64:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB66_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v23, v14, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v16, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v22, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v2, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v2, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v1, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v21, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
|
|
; GFX11-FAKE16-NEXT: .LBB66_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define inreg <8 x i64> @bitcast_v32bf16_to_v8i64_scalar(<32 x bfloat> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v8i64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v0
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s5, s29, 16
|
|
; SI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s28, 16
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s9, s27, 16
|
|
; SI-NEXT: s_and_b32 s10, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s26, 16
|
|
; SI-NEXT: s_and_b32 s12, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s25, 16
|
|
; SI-NEXT: s_and_b32 s14, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s24, 16
|
|
; SI-NEXT: s_and_b32 s24, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_and_b32 s25, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: s_and_b32 s26, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s27, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s28, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: s_and_b32 s29, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s40, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s41, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s43, s42, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s42, 16
|
|
; SI-NEXT: s_and_b32 s45, s44, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s46, 0
|
|
; SI-NEXT: v_mul_f32_e64 v41, 1.0, s41
|
|
; SI-NEXT: v_mul_f32_e64 v52, 1.0, s16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v63, 1.0, s40
|
|
; SI-NEXT: v_mul_f32_e64 v48, 1.0, s17
|
|
; SI-NEXT: v_mul_f32_e64 v62, 1.0, s29
|
|
; SI-NEXT: v_mul_f32_e64 v61, 1.0, s28
|
|
; SI-NEXT: v_mul_f32_e64 v60, 1.0, s27
|
|
; SI-NEXT: v_mul_f32_e64 v59, 1.0, s26
|
|
; SI-NEXT: v_mul_f32_e64 v58, 1.0, s25
|
|
; SI-NEXT: v_mul_f32_e64 v57, 1.0, s24
|
|
; SI-NEXT: v_mul_f32_e64 v56, 1.0, s14
|
|
; SI-NEXT: v_mul_f32_e64 v47, 1.0, s12
|
|
; SI-NEXT: v_mul_f32_e64 v46, 1.0, s10
|
|
; SI-NEXT: v_mul_f32_e64 v45, 1.0, s8
|
|
; SI-NEXT: v_mul_f32_e64 v44, 1.0, s6
|
|
; SI-NEXT: v_mul_f32_e64 v43, 1.0, s4
|
|
; SI-NEXT: v_mul_f32_e64 v42, 1.0, s45
|
|
; SI-NEXT: v_mul_f32_e64 v16, 1.0, s43
|
|
; SI-NEXT: v_mul_f32_e64 v39, 1.0, s18
|
|
; SI-NEXT: v_mul_f32_e64 v54, 1.0, s19
|
|
; SI-NEXT: v_mul_f32_e64 v50, 1.0, s20
|
|
; SI-NEXT: v_mul_f32_e64 v37, 1.0, s21
|
|
; SI-NEXT: v_mul_f32_e64 v35, 1.0, s22
|
|
; SI-NEXT: v_mul_f32_e64 v33, 1.0, s23
|
|
; SI-NEXT: v_mul_f32_e64 v31, 1.0, s15
|
|
; SI-NEXT: v_mul_f32_e64 v29, 1.0, s13
|
|
; SI-NEXT: v_mul_f32_e64 v27, 1.0, s11
|
|
; SI-NEXT: v_mul_f32_e64 v25, 1.0, s9
|
|
; SI-NEXT: v_mul_f32_e64 v23, 1.0, s7
|
|
; SI-NEXT: v_mul_f32_e64 v21, 1.0, s5
|
|
; SI-NEXT: v_mul_f32_e64 v19, 1.0, s44
|
|
; SI-NEXT: v_mul_f32_e64 v17, 1.0, s42
|
|
; SI-NEXT: s_cbranch_scc0 .LBB67_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v63
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[52:53], 16
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v62
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[39:40], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v61
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[54:55], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v60
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[50:51], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v59
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[37:38], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v58
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[35:36], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v57
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[33:34], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v56
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[31:32], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v47
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[29:30], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v46
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[27:28], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v45
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[25:26], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v44
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[23:24], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v43
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[21:22], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v42
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[19:20], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v16
|
|
; SI-NEXT: v_mov_b32_e32 v20, v16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[17:18], 16
|
|
; SI-NEXT: v_mov_b32_e32 v16, v20
|
|
; SI-NEXT: s_cbranch_execnz .LBB67_3
|
|
; SI-NEXT: .LBB67_2: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v52
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v63
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v48
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v62
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v61
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v54
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v60
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v50
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v59
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v58
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v57
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v56
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v47
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v46
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v45
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v44
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v43
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v42
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
|
|
; SI-NEXT: .LBB67_3: ; %end
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB67_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_branch .LBB67_2
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v8i64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v20, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v20, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB67_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB67_4
|
|
; VI-NEXT: .LBB67_2: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
|
|
; VI-NEXT: s_lshl_b32 s4, s30, 16
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
|
|
; VI-NEXT: v_add_f32_e32 v1, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s28, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; VI-NEXT: v_add_f32_e32 v2, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[0:1]
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: s_and_b32 s5, s26, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s26, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s24, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s24, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s22, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s20, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s20, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s18, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s18, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s16, 16
|
|
; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s17, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s19, 16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v1, v5, s[4:5]
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
|
|
; VI-NEXT: s_lshl_b32 s6, s21, 16
|
|
; VI-NEXT: v_mov_b32_e32 v1, v17
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v5, v7, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v16
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v5, v5
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
|
|
; VI-NEXT: v_bfe_u32 v11, v5, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v5
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: s_lshl_b32 s6, s23, 16
|
|
; VI-NEXT: v_mov_b32_e32 v3, v17
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v7, v9, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v11, v13, vcc
|
|
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v7, v7
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
|
|
; VI-NEXT: s_lshl_b32 s6, s25, 16
|
|
; VI-NEXT: v_mov_b32_e32 v5, v17
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v9, v11, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v16
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v9, v9
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
|
|
; VI-NEXT: v_bfe_u32 v15, v9, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v9
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v7, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v15, v17, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s27, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v11, v13, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v11, v11
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v16
|
|
; VI-NEXT: v_mov_b32_e32 v9, v17
|
|
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: s_and_b32 s7, s31, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v13, v15, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v13, s7, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: s_lshl_b32 s6, s31, 16
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v11, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: s_lshl_b32 s4, s29, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
|
|
; VI-NEXT: v_add_f32_e32 v15, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[17:18]
|
|
; VI-NEXT: v_mov_b32_e32 v13, v15
|
|
; VI-NEXT: v_mov_b32_e32 v15, v16
|
|
; VI-NEXT: s_branch .LBB67_5
|
|
; VI-NEXT: .LBB67_3:
|
|
; VI-NEXT: s_branch .LBB67_2
|
|
; VI-NEXT: .LBB67_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB67_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v20, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v20, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v8i64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB67_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB67_4
|
|
; GFX9-NEXT: .LBB67_2: ; %cmp.true
|
|
; GFX9-NEXT: s_and_b32 s4, s31, 0xffff0000
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s31, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v3, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: s_lshl_b32 s4, s30, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v4, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, 0xffff
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v1, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v3
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s29, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s28, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s27, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s26, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s25, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s24, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s23, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s22, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s21, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s20, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s19, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s18, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v17, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s17, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v17, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: s_lshl_b32 s4, s16, 16
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v0, s4, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v0, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v0
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_and_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v16
|
|
; GFX9-NEXT: s_branch .LBB67_5
|
|
; GFX9-NEXT: .LBB67_3:
|
|
; GFX9-NEXT: s_branch .LBB67_2
|
|
; GFX9-NEXT: .LBB67_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB67_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v20, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v8i64_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB67_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB67_4
|
|
; GFX11-TRUE16-NEXT: .LBB67_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s27, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s26, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v7, v7, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v2, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v17 :: v_dual_add_nc_u32 v3, v3, v4
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s15, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s12, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v17, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v16, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v18, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v16, v20, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v18
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v16, v19, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s12, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v19 :: v_dual_add_nc_u32 v19, v21, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, v22, v17
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v20, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v21, v22, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v23, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v24, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v17.l
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB67_3:
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB67_2
|
|
; GFX11-TRUE16-NEXT: .LBB67_4:
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v8i64_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB67_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB67_4
|
|
; GFX11-FAKE16-NEXT: .LBB67_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s26, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s25, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_nc_u32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v8, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v6, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s17, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v6, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v7, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v17, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v19, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v18, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v6, v16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s15, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v17, v18 :: v_dual_add_nc_u32 v17, v19, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s12, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v24
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v21, v24, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v18, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v16, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v20, 16, v17
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB67_3:
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB67_2
|
|
; GFX11-FAKE16-NEXT: .LBB67_4:
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v64i8:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; kill: killed $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB68_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v17, v16, v15, 24
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v15, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v16, v15, 8
|
|
; SI-NEXT: v_alignbit_b32 v20, v14, v13, 24
|
|
; SI-NEXT: v_alignbit_b32 v21, v14, v13, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v14, v13, 8
|
|
; SI-NEXT: v_alignbit_b32 v23, v12, v11, 24
|
|
; SI-NEXT: v_alignbit_b32 v24, v12, v11, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v12, v11, 8
|
|
; SI-NEXT: v_alignbit_b32 v28, v10, v9, 24
|
|
; SI-NEXT: v_alignbit_b32 v30, v10, v9, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v10, v9, 8
|
|
; SI-NEXT: v_alignbit_b32 v35, v8, v7, 24
|
|
; SI-NEXT: v_alignbit_b32 v36, v8, v7, 16
|
|
; SI-NEXT: v_alignbit_b32 v37, v8, v7, 8
|
|
; SI-NEXT: v_alignbit_b32 v49, v6, v5, 24
|
|
; SI-NEXT: v_alignbit_b32 v50, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v51, v6, v5, 8
|
|
; SI-NEXT: v_alignbit_b32 v55, v4, v3, 24
|
|
; SI-NEXT: v_alignbit_b32 v40, v4, v3, 16
|
|
; SI-NEXT: v_alignbit_b32 v43, v4, v3, 8
|
|
; SI-NEXT: v_alignbit_b32 v46, v2, v1, 24
|
|
; SI-NEXT: v_alignbit_b32 v56, v2, v1, 16
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_alignbit_b32 v58, v2, v1, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 24, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v41, 24, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v57, 8, v6
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v4
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v4
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v2
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
|
|
; SI-NEXT: .LBB68_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB68_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_addc_u32_e32 v12, vcc, 0, v12, vcc
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_addc_u32_e32 v16, vcc, 0, v16, vcc
|
|
; SI-NEXT: v_alignbit_b32 v17, v16, v15, 24
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v15, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v16, v15, 8
|
|
; SI-NEXT: v_alignbit_b32 v20, v14, v13, 24
|
|
; SI-NEXT: v_alignbit_b32 v21, v14, v13, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v14, v13, 8
|
|
; SI-NEXT: v_alignbit_b32 v23, v12, v11, 24
|
|
; SI-NEXT: v_alignbit_b32 v24, v12, v11, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v12, v11, 8
|
|
; SI-NEXT: v_alignbit_b32 v28, v10, v9, 24
|
|
; SI-NEXT: v_alignbit_b32 v30, v10, v9, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v10, v9, 8
|
|
; SI-NEXT: v_alignbit_b32 v35, v8, v7, 24
|
|
; SI-NEXT: v_alignbit_b32 v36, v8, v7, 16
|
|
; SI-NEXT: v_alignbit_b32 v37, v8, v7, 8
|
|
; SI-NEXT: v_alignbit_b32 v49, v6, v5, 24
|
|
; SI-NEXT: v_alignbit_b32 v50, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v51, v6, v5, 8
|
|
; SI-NEXT: v_alignbit_b32 v55, v4, v3, 24
|
|
; SI-NEXT: v_alignbit_b32 v40, v4, v3, 16
|
|
; SI-NEXT: v_alignbit_b32 v43, v4, v3, 8
|
|
; SI-NEXT: v_alignbit_b32 v46, v2, v1, 24
|
|
; SI-NEXT: v_alignbit_b32 v56, v2, v1, 16
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_alignbit_b32 v58, v2, v1, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 24, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v41, 24, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v57, 8, v6
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v4
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v4
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v2
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
|
|
; SI-NEXT: .LBB68_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v58
|
|
; SI-NEXT: v_and_b32_e32 v56, 0xff, v56
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v56
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v46
|
|
; SI-NEXT: v_or_b32_e32 v46, v46, v56
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v46
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v17
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v63
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v62
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v17, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v40
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v55
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v61
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v60
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v59
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v51
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v49
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v57
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v47
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v45
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v37
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v44
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v41
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v31
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v28
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v54
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v53
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v52
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v25
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v48
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v38
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v22
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v20
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v32
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v19
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v29
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v26
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v64i8:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB68_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: v_mov_b32_e32 v27, v21
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: .LBB68_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB68_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1
|
|
; VI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3
|
|
; VI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5
|
|
; VI-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7
|
|
; VI-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 3, v9
|
|
; VI-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 3, v11
|
|
; VI-NEXT: v_addc_u32_e32 v12, vcc, 0, v12, vcc
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v13
|
|
; VI-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v15
|
|
; VI-NEXT: v_addc_u32_e32 v16, vcc, 0, v16, vcc
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: .LBB68_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v21
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; VI-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
|
|
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
|
|
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
|
|
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v64i8:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB68_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v16
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, v22
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: .LBB68_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB68_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, 3, v1
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, 3, v3
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, 3, v5
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, 3, v7
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, 3, v9
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v10, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, 3, v11
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v12, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, 3, v13
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v14, vcc
|
|
; GFX9-NEXT: v_add_co_u32_e32 v15, vcc, 3, v15
|
|
; GFX9-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v16, vcc
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: .LBB68_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v22, v30, v24, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v22, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v21, v62, v21, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v61, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v21, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v43, v23, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v54, v20, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v27, v25, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v8i64_to_v64i8:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB68_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB68_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_co_u32 v1, vcc_lo, v1, 3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_co_u32 v3, vcc_lo, v3, 3
|
|
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_co_u32 v5, vcc_lo, v5, 3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_co_u32 v9, vcc_lo, v9, 3
|
|
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_co_u32 v11, vcc_lo, v11, 3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_co_u32 v13, vcc_lo, v13, 3
|
|
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v14, null, 0, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_co_u32 v15, vcc_lo, v15, 3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v16, null, 0, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_co_u32 v7, vcc_lo, v7, 3
|
|
; GFX11-TRUE16-NEXT: v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB68_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
|
|
; GFX11-TRUE16-NEXT: s_clause 0x3
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v8i64_to_v64i8:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB68_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB68_2: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB68_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_co_u32 v1, vcc_lo, v1, 3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v2, null, 0, v2, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_co_u32 v3, vcc_lo, v3, 3
|
|
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v4, null, 0, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_co_u32 v5, vcc_lo, v5, 3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v6, null, 0, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_co_u32 v9, vcc_lo, v9, 3
|
|
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v10, null, 0, v10, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_co_u32 v11, vcc_lo, v11, 3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v12, null, 0, v12, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_co_u32 v13, vcc_lo, v13, 3
|
|
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v14, null, 0, v14, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_co_u32 v15, vcc_lo, v15, 3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v16, null, 0, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_co_u32 v7, vcc_lo, v7, 3
|
|
; GFX11-FAKE16-NEXT: v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB68_4: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
|
|
; GFX11-FAKE16-NEXT: s_clause 0x3
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8i64_to_v64i8_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v4, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v4, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v4, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v4, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v4, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v4, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v4, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v4, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v4, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v4, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v4, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v4, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v4, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v4, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v4, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v4, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v4, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v4, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v4, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v4, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v4, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v4, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v4, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v4, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v4, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v4, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v4, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v4, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v4, s30, 28
|
|
; SI-NEXT: v_writelane_b32 v4, s31, 29
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; SI-NEXT: s_cbranch_scc0 .LBB69_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s38, s5, 24
|
|
; SI-NEXT: s_lshr_b32 s39, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s48, s5, 8
|
|
; SI-NEXT: s_lshr_b32 s49, s29, 24
|
|
; SI-NEXT: s_lshr_b32 s50, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s51, s29, 8
|
|
; SI-NEXT: s_lshr_b32 s52, s27, 24
|
|
; SI-NEXT: s_lshr_b32 s53, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s54, s27, 8
|
|
; SI-NEXT: s_lshr_b32 s55, s25, 24
|
|
; SI-NEXT: s_lshr_b32 s64, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s65, s25, 8
|
|
; SI-NEXT: s_lshr_b32 s66, s23, 24
|
|
; SI-NEXT: s_lshr_b32 s67, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s68, s23, 8
|
|
; SI-NEXT: s_lshr_b32 s69, s21, 24
|
|
; SI-NEXT: s_lshr_b32 s70, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s71, s21, 8
|
|
; SI-NEXT: s_lshr_b32 s80, s19, 24
|
|
; SI-NEXT: s_lshr_b32 s81, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s82, s19, 8
|
|
; SI-NEXT: s_lshr_b32 s83, s17, 24
|
|
; SI-NEXT: s_lshr_b32 s84, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s85, s17, 8
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 8
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[28:29], 24
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[28:29], 8
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[24:25], 24
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 8
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 24
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[22:23], 8
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 8
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[18:19], 24
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 8
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 8
|
|
; SI-NEXT: s_cbranch_execnz .LBB69_3
|
|
; SI-NEXT: .LBB69_2: ; %cmp.true
|
|
; SI-NEXT: s_add_u32 s4, s4, 3
|
|
; SI-NEXT: s_addc_u32 s5, s5, 0
|
|
; SI-NEXT: s_add_u32 s28, s28, 3
|
|
; SI-NEXT: s_addc_u32 s29, s29, 0
|
|
; SI-NEXT: s_add_u32 s26, s26, 3
|
|
; SI-NEXT: s_addc_u32 s27, s27, 0
|
|
; SI-NEXT: s_add_u32 s24, s24, 3
|
|
; SI-NEXT: s_addc_u32 s25, s25, 0
|
|
; SI-NEXT: s_add_u32 s22, s22, 3
|
|
; SI-NEXT: s_addc_u32 s23, s23, 0
|
|
; SI-NEXT: s_add_u32 s20, s20, 3
|
|
; SI-NEXT: s_addc_u32 s21, s21, 0
|
|
; SI-NEXT: s_add_u32 s18, s18, 3
|
|
; SI-NEXT: s_addc_u32 s19, s19, 0
|
|
; SI-NEXT: s_add_u32 s16, s16, 3
|
|
; SI-NEXT: s_addc_u32 s17, s17, 0
|
|
; SI-NEXT: s_lshr_b32 s38, s5, 24
|
|
; SI-NEXT: s_lshr_b32 s39, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s48, s5, 8
|
|
; SI-NEXT: s_lshr_b32 s49, s29, 24
|
|
; SI-NEXT: s_lshr_b32 s50, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s51, s29, 8
|
|
; SI-NEXT: s_lshr_b32 s52, s27, 24
|
|
; SI-NEXT: s_lshr_b32 s53, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s54, s27, 8
|
|
; SI-NEXT: s_lshr_b32 s55, s25, 24
|
|
; SI-NEXT: s_lshr_b32 s64, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s65, s25, 8
|
|
; SI-NEXT: s_lshr_b32 s66, s23, 24
|
|
; SI-NEXT: s_lshr_b32 s67, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s68, s23, 8
|
|
; SI-NEXT: s_lshr_b32 s69, s21, 24
|
|
; SI-NEXT: s_lshr_b32 s70, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s71, s21, 8
|
|
; SI-NEXT: s_lshr_b32 s80, s19, 24
|
|
; SI-NEXT: s_lshr_b32 s81, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s82, s19, 8
|
|
; SI-NEXT: s_lshr_b32 s83, s17, 24
|
|
; SI-NEXT: s_lshr_b32 s84, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s85, s17, 8
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 8
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[28:29], 24
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[28:29], 8
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[24:25], 24
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[24:25], 8
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[22:23], 24
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[22:23], 8
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[20:21], 8
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[18:19], 24
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[18:19], 8
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[16:17], 8
|
|
; SI-NEXT: .LBB69_3: ; %end
|
|
; SI-NEXT: s_lshl_b32 s7, s36, 8
|
|
; SI-NEXT: s_and_b32 s9, s16, 0xff
|
|
; SI-NEXT: s_or_b32 s7, s9, s7
|
|
; SI-NEXT: s_and_b32 s9, s34, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s30, 24
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_mov_b32_e32 v1, s7
|
|
; SI-NEXT: s_and_b32 s7, s17, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s85, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s84, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s83, 24
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_lshl_b32 s7, s94, 8
|
|
; SI-NEXT: s_and_b32 s9, s18, 0xff
|
|
; SI-NEXT: s_or_b32 s7, s9, s7
|
|
; SI-NEXT: s_and_b32 s9, s92, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s90, 24
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_mov_b32_e32 v3, s7
|
|
; SI-NEXT: s_and_b32 s7, s19, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s82, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s81, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s80, 24
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s76, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s62, 24
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: buffer_store_dword v3, v1, s[0:3], 0 offen
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s21, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s71, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s70, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s69, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s22, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s88, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s78, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s74, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s23, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s68, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s67, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s66, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s60, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s56, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s25, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s65, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s64, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s55, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s46, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s44, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s42, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s27, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s54, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s53, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s52, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s40, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s12, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s29, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s51, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s50, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s49, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s11, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s10, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s7
|
|
; SI-NEXT: s_and_b32 s7, s8, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s4
|
|
; SI-NEXT: s_and_b32 s4, s5, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s48, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s39, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s38, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: v_mov_b32_e32 v1, s4
|
|
; SI-NEXT: v_readlane_b32 s30, v4, 28
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: v_readlane_b32 s31, v4, 29
|
|
; SI-NEXT: v_readlane_b32 s85, v4, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v4, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v4, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v4, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v4, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v4, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v4, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v4, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v4, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v4, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v4, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v4, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v4, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v4, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v4, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v4, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v4, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v4, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v4, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v4, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v4, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v4, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v4, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v4, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v4, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v4, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v4, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v4, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB69_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr36
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: ; implicit-def: $sgpr85
|
|
; SI-NEXT: ; implicit-def: $sgpr84
|
|
; SI-NEXT: ; implicit-def: $sgpr83
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr90
|
|
; SI-NEXT: ; implicit-def: $sgpr82
|
|
; SI-NEXT: ; implicit-def: $sgpr81
|
|
; SI-NEXT: ; implicit-def: $sgpr80
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr71
|
|
; SI-NEXT: ; implicit-def: $sgpr70
|
|
; SI-NEXT: ; implicit-def: $sgpr69
|
|
; SI-NEXT: ; implicit-def: $sgpr68
|
|
; SI-NEXT: ; implicit-def: $sgpr67
|
|
; SI-NEXT: ; implicit-def: $sgpr66
|
|
; SI-NEXT: ; implicit-def: $sgpr65
|
|
; SI-NEXT: ; implicit-def: $sgpr64
|
|
; SI-NEXT: ; implicit-def: $sgpr55
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr53
|
|
; SI-NEXT: ; implicit-def: $sgpr52
|
|
; SI-NEXT: ; implicit-def: $sgpr51
|
|
; SI-NEXT: ; implicit-def: $sgpr50
|
|
; SI-NEXT: ; implicit-def: $sgpr49
|
|
; SI-NEXT: ; implicit-def: $sgpr48
|
|
; SI-NEXT: ; implicit-def: $sgpr39
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: s_branch .LBB69_2
|
|
;
|
|
; VI-LABEL: bitcast_v8i64_to_v64i8_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v4, s34, 0
|
|
; VI-NEXT: v_writelane_b32 v4, s35, 1
|
|
; VI-NEXT: v_writelane_b32 v4, s36, 2
|
|
; VI-NEXT: v_writelane_b32 v4, s37, 3
|
|
; VI-NEXT: v_writelane_b32 v4, s38, 4
|
|
; VI-NEXT: v_writelane_b32 v4, s39, 5
|
|
; VI-NEXT: v_writelane_b32 v4, s48, 6
|
|
; VI-NEXT: v_writelane_b32 v4, s49, 7
|
|
; VI-NEXT: v_writelane_b32 v4, s50, 8
|
|
; VI-NEXT: v_writelane_b32 v4, s51, 9
|
|
; VI-NEXT: v_writelane_b32 v4, s52, 10
|
|
; VI-NEXT: v_writelane_b32 v4, s53, 11
|
|
; VI-NEXT: v_writelane_b32 v4, s54, 12
|
|
; VI-NEXT: v_writelane_b32 v4, s55, 13
|
|
; VI-NEXT: v_writelane_b32 v4, s64, 14
|
|
; VI-NEXT: v_writelane_b32 v4, s65, 15
|
|
; VI-NEXT: v_writelane_b32 v4, s66, 16
|
|
; VI-NEXT: v_writelane_b32 v4, s67, 17
|
|
; VI-NEXT: v_writelane_b32 v4, s30, 18
|
|
; VI-NEXT: v_writelane_b32 v4, s31, 19
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; VI-NEXT: s_cbranch_scc0 .LBB69_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_lshr_b32 s56, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s58, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s60, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s61, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s63, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s72, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s74, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s75, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s76, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s77, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s78, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s79, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s89, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s90, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s91, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s31, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s34, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s35, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s36, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s39, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s48, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s49, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s50, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s51, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s52, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s53, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s54, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s65, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s66, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 8
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; VI-NEXT: s_cbranch_execnz .LBB69_3
|
|
; VI-NEXT: .LBB69_2: ; %cmp.true
|
|
; VI-NEXT: s_add_u32 s16, s16, 3
|
|
; VI-NEXT: s_addc_u32 s17, s17, 0
|
|
; VI-NEXT: s_add_u32 s18, s18, 3
|
|
; VI-NEXT: s_addc_u32 s19, s19, 0
|
|
; VI-NEXT: s_add_u32 s20, s20, 3
|
|
; VI-NEXT: s_addc_u32 s21, s21, 0
|
|
; VI-NEXT: s_add_u32 s22, s22, 3
|
|
; VI-NEXT: s_addc_u32 s23, s23, 0
|
|
; VI-NEXT: s_add_u32 s24, s24, 3
|
|
; VI-NEXT: s_addc_u32 s25, s25, 0
|
|
; VI-NEXT: s_add_u32 s26, s26, 3
|
|
; VI-NEXT: s_addc_u32 s27, s27, 0
|
|
; VI-NEXT: s_add_u32 s28, s28, 3
|
|
; VI-NEXT: s_addc_u32 s29, s29, 0
|
|
; VI-NEXT: s_add_u32 s4, s4, 3
|
|
; VI-NEXT: s_addc_u32 s5, s5, 0
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; VI-NEXT: s_lshr_b32 s56, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s58, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s60, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s61, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s63, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s72, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s74, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s75, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s76, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s77, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s78, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s79, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s89, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s90, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s91, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s31, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s34, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s35, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s36, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s39, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s48, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s49, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s50, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s51, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s52, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s53, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s54, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s65, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s66, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 8
|
|
; VI-NEXT: .LBB69_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v3, s44
|
|
; VI-NEXT: v_mov_b32_e32 v1, s67
|
|
; VI-NEXT: v_perm_b32 v3, s66, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s55
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v1, s65
|
|
; VI-NEXT: v_perm_b32 v3, s64, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s42
|
|
; VI-NEXT: v_mov_b32_e32 v1, s54
|
|
; VI-NEXT: v_perm_b32 v3, s53, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s50
|
|
; VI-NEXT: v_mov_b32_e32 v1, s52
|
|
; VI-NEXT: v_perm_b32 v3, s51, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s40
|
|
; VI-NEXT: v_mov_b32_e32 v1, s49
|
|
; VI-NEXT: v_perm_b32 v3, s48, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s37
|
|
; VI-NEXT: v_mov_b32_e32 v1, s39
|
|
; VI-NEXT: v_perm_b32 v3, s38, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s14
|
|
; VI-NEXT: v_mov_b32_e32 v1, s36
|
|
; VI-NEXT: v_perm_b32 v3, s35, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s30
|
|
; VI-NEXT: v_mov_b32_e32 v1, s34
|
|
; VI-NEXT: v_perm_b32 v3, s31, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s12
|
|
; VI-NEXT: v_mov_b32_e32 v1, s91
|
|
; VI-NEXT: v_perm_b32 v3, s90, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s79
|
|
; VI-NEXT: v_mov_b32_e32 v1, s89
|
|
; VI-NEXT: v_perm_b32 v3, s88, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s10
|
|
; VI-NEXT: v_mov_b32_e32 v1, s78
|
|
; VI-NEXT: v_perm_b32 v3, s77, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s26, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s74
|
|
; VI-NEXT: v_mov_b32_e32 v1, s76
|
|
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s27, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s8
|
|
; VI-NEXT: v_mov_b32_e32 v1, s73
|
|
; VI-NEXT: v_perm_b32 v3, s72, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s28, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s61
|
|
; VI-NEXT: v_mov_b32_e32 v1, s63
|
|
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s29, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s6
|
|
; VI-NEXT: v_mov_b32_e32 v1, s60
|
|
; VI-NEXT: v_perm_b32 v3, s59, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s4, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v1, s58
|
|
; VI-NEXT: v_mov_b32_e32 v3, s56
|
|
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
|
|
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: v_readlane_b32 s30, v4, 18
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_readlane_b32 s31, v4, 19
|
|
; VI-NEXT: v_readlane_b32 s67, v4, 17
|
|
; VI-NEXT: v_readlane_b32 s66, v4, 16
|
|
; VI-NEXT: v_readlane_b32 s65, v4, 15
|
|
; VI-NEXT: v_readlane_b32 s64, v4, 14
|
|
; VI-NEXT: v_readlane_b32 s55, v4, 13
|
|
; VI-NEXT: v_readlane_b32 s54, v4, 12
|
|
; VI-NEXT: v_readlane_b32 s53, v4, 11
|
|
; VI-NEXT: v_readlane_b32 s52, v4, 10
|
|
; VI-NEXT: v_readlane_b32 s51, v4, 9
|
|
; VI-NEXT: v_readlane_b32 s50, v4, 8
|
|
; VI-NEXT: v_readlane_b32 s49, v4, 7
|
|
; VI-NEXT: v_readlane_b32 s48, v4, 6
|
|
; VI-NEXT: v_readlane_b32 s39, v4, 5
|
|
; VI-NEXT: v_readlane_b32 s38, v4, 4
|
|
; VI-NEXT: v_readlane_b32 s37, v4, 3
|
|
; VI-NEXT: v_readlane_b32 s36, v4, 2
|
|
; VI-NEXT: v_readlane_b32 s35, v4, 1
|
|
; VI-NEXT: v_readlane_b32 s34, v4, 0
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB69_4:
|
|
; VI-NEXT: ; implicit-def: $sgpr67
|
|
; VI-NEXT: ; implicit-def: $sgpr66
|
|
; VI-NEXT: ; implicit-def: $sgpr44
|
|
; VI-NEXT: ; implicit-def: $sgpr65
|
|
; VI-NEXT: ; implicit-def: $sgpr64
|
|
; VI-NEXT: ; implicit-def: $sgpr55
|
|
; VI-NEXT: ; implicit-def: $sgpr54
|
|
; VI-NEXT: ; implicit-def: $sgpr53
|
|
; VI-NEXT: ; implicit-def: $sgpr42
|
|
; VI-NEXT: ; implicit-def: $sgpr52
|
|
; VI-NEXT: ; implicit-def: $sgpr51
|
|
; VI-NEXT: ; implicit-def: $sgpr50
|
|
; VI-NEXT: ; implicit-def: $sgpr49
|
|
; VI-NEXT: ; implicit-def: $sgpr48
|
|
; VI-NEXT: ; implicit-def: $sgpr40
|
|
; VI-NEXT: ; implicit-def: $sgpr39
|
|
; VI-NEXT: ; implicit-def: $sgpr38
|
|
; VI-NEXT: ; implicit-def: $sgpr37
|
|
; VI-NEXT: ; implicit-def: $sgpr36
|
|
; VI-NEXT: ; implicit-def: $sgpr35
|
|
; VI-NEXT: ; implicit-def: $sgpr14
|
|
; VI-NEXT: ; implicit-def: $sgpr34
|
|
; VI-NEXT: ; implicit-def: $sgpr31
|
|
; VI-NEXT: ; implicit-def: $sgpr30
|
|
; VI-NEXT: ; implicit-def: $sgpr91
|
|
; VI-NEXT: ; implicit-def: $sgpr90
|
|
; VI-NEXT: ; implicit-def: $sgpr12
|
|
; VI-NEXT: ; implicit-def: $sgpr89
|
|
; VI-NEXT: ; implicit-def: $sgpr88
|
|
; VI-NEXT: ; implicit-def: $sgpr79
|
|
; VI-NEXT: ; implicit-def: $sgpr78
|
|
; VI-NEXT: ; implicit-def: $sgpr77
|
|
; VI-NEXT: ; implicit-def: $sgpr10
|
|
; VI-NEXT: ; implicit-def: $sgpr76
|
|
; VI-NEXT: ; implicit-def: $sgpr75
|
|
; VI-NEXT: ; implicit-def: $sgpr74
|
|
; VI-NEXT: ; implicit-def: $sgpr73
|
|
; VI-NEXT: ; implicit-def: $sgpr72
|
|
; VI-NEXT: ; implicit-def: $sgpr8
|
|
; VI-NEXT: ; implicit-def: $sgpr63
|
|
; VI-NEXT: ; implicit-def: $sgpr62
|
|
; VI-NEXT: ; implicit-def: $sgpr61
|
|
; VI-NEXT: ; implicit-def: $sgpr60
|
|
; VI-NEXT: ; implicit-def: $sgpr59
|
|
; VI-NEXT: ; implicit-def: $sgpr6
|
|
; VI-NEXT: ; implicit-def: $sgpr58
|
|
; VI-NEXT: ; implicit-def: $sgpr57
|
|
; VI-NEXT: ; implicit-def: $sgpr56
|
|
; VI-NEXT: s_branch .LBB69_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v8i64_to_v64i8_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v4, s34, 0
|
|
; GFX9-NEXT: v_writelane_b32 v4, s35, 1
|
|
; GFX9-NEXT: v_writelane_b32 v4, s36, 2
|
|
; GFX9-NEXT: v_writelane_b32 v4, s37, 3
|
|
; GFX9-NEXT: v_writelane_b32 v4, s38, 4
|
|
; GFX9-NEXT: v_writelane_b32 v4, s39, 5
|
|
; GFX9-NEXT: v_writelane_b32 v4, s48, 6
|
|
; GFX9-NEXT: v_writelane_b32 v4, s49, 7
|
|
; GFX9-NEXT: v_writelane_b32 v4, s50, 8
|
|
; GFX9-NEXT: v_writelane_b32 v4, s51, 9
|
|
; GFX9-NEXT: v_writelane_b32 v4, s52, 10
|
|
; GFX9-NEXT: v_writelane_b32 v4, s53, 11
|
|
; GFX9-NEXT: v_writelane_b32 v4, s54, 12
|
|
; GFX9-NEXT: v_writelane_b32 v4, s55, 13
|
|
; GFX9-NEXT: v_writelane_b32 v4, s30, 14
|
|
; GFX9-NEXT: v_writelane_b32 v4, s31, 15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB69_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s57, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s58, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s59, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s60, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s61, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s62, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s63, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s72, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s74, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s75, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s76, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s77, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s78, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s79, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s88, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s89, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s90, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s91, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s92, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s93, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s94, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s95, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s30, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s35, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s36, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s37, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s38, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s39, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s48, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s49, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s50, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s52, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s53, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB69_3
|
|
; GFX9-NEXT: .LBB69_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX9-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX9-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX9-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX9-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX9-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX9-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX9-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX9-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX9-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX9-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX9-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX9-NEXT: s_add_u32 s28, s28, 3
|
|
; GFX9-NEXT: s_addc_u32 s29, s29, 0
|
|
; GFX9-NEXT: s_add_u32 s4, s4, 3
|
|
; GFX9-NEXT: s_addc_u32 s5, s5, 0
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s57, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s58, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s59, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s60, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s61, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s62, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s63, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s72, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s74, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s75, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s76, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s77, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s78, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s79, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s88, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s89, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s90, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s91, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s92, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s93, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s94, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s95, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s30, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s35, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s36, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s37, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s38, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s39, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s48, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s49, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s50, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s52, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s53, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
|
|
; GFX9-NEXT: .LBB69_3: ; %end
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s44
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s55
|
|
; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s51
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s53
|
|
; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s42
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s50
|
|
; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s38
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s48
|
|
; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s40
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s37
|
|
; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s31
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s35
|
|
; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s14
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s30
|
|
; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s92
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s94
|
|
; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s12
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s91
|
|
; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s79
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s89
|
|
; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s10
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s78
|
|
; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s74
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s76
|
|
; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s8
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s73
|
|
; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s61
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s63
|
|
; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s6
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s60
|
|
; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
|
|
; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s58
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s56
|
|
; GFX9-NEXT: v_perm_b32 v1, s5, v1, v2
|
|
; GFX9-NEXT: v_perm_b32 v2, s57, v3, v2
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: v_readlane_b32 s30, v4, 14
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: v_readlane_b32 s31, v4, 15
|
|
; GFX9-NEXT: v_readlane_b32 s55, v4, 13
|
|
; GFX9-NEXT: v_readlane_b32 s54, v4, 12
|
|
; GFX9-NEXT: v_readlane_b32 s53, v4, 11
|
|
; GFX9-NEXT: v_readlane_b32 s52, v4, 10
|
|
; GFX9-NEXT: v_readlane_b32 s51, v4, 9
|
|
; GFX9-NEXT: v_readlane_b32 s50, v4, 8
|
|
; GFX9-NEXT: v_readlane_b32 s49, v4, 7
|
|
; GFX9-NEXT: v_readlane_b32 s48, v4, 6
|
|
; GFX9-NEXT: v_readlane_b32 s39, v4, 5
|
|
; GFX9-NEXT: v_readlane_b32 s38, v4, 4
|
|
; GFX9-NEXT: v_readlane_b32 s37, v4, 3
|
|
; GFX9-NEXT: v_readlane_b32 s36, v4, 2
|
|
; GFX9-NEXT: v_readlane_b32 s35, v4, 1
|
|
; GFX9-NEXT: v_readlane_b32 s34, v4, 0
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB69_4:
|
|
; GFX9-NEXT: ; implicit-def: $sgpr55
|
|
; GFX9-NEXT: ; implicit-def: $sgpr54
|
|
; GFX9-NEXT: ; implicit-def: $sgpr44
|
|
; GFX9-NEXT: ; implicit-def: $sgpr53
|
|
; GFX9-NEXT: ; implicit-def: $sgpr52
|
|
; GFX9-NEXT: ; implicit-def: $sgpr51
|
|
; GFX9-NEXT: ; implicit-def: $sgpr50
|
|
; GFX9-NEXT: ; implicit-def: $sgpr49
|
|
; GFX9-NEXT: ; implicit-def: $sgpr42
|
|
; GFX9-NEXT: ; implicit-def: $sgpr48
|
|
; GFX9-NEXT: ; implicit-def: $sgpr39
|
|
; GFX9-NEXT: ; implicit-def: $sgpr38
|
|
; GFX9-NEXT: ; implicit-def: $sgpr37
|
|
; GFX9-NEXT: ; implicit-def: $sgpr36
|
|
; GFX9-NEXT: ; implicit-def: $sgpr40
|
|
; GFX9-NEXT: ; implicit-def: $sgpr35
|
|
; GFX9-NEXT: ; implicit-def: $sgpr34
|
|
; GFX9-NEXT: ; implicit-def: $sgpr31
|
|
; GFX9-NEXT: ; implicit-def: $sgpr30
|
|
; GFX9-NEXT: ; implicit-def: $sgpr95
|
|
; GFX9-NEXT: ; implicit-def: $sgpr14
|
|
; GFX9-NEXT: ; implicit-def: $sgpr94
|
|
; GFX9-NEXT: ; implicit-def: $sgpr93
|
|
; GFX9-NEXT: ; implicit-def: $sgpr92
|
|
; GFX9-NEXT: ; implicit-def: $sgpr91
|
|
; GFX9-NEXT: ; implicit-def: $sgpr90
|
|
; GFX9-NEXT: ; implicit-def: $sgpr12
|
|
; GFX9-NEXT: ; implicit-def: $sgpr89
|
|
; GFX9-NEXT: ; implicit-def: $sgpr88
|
|
; GFX9-NEXT: ; implicit-def: $sgpr79
|
|
; GFX9-NEXT: ; implicit-def: $sgpr78
|
|
; GFX9-NEXT: ; implicit-def: $sgpr77
|
|
; GFX9-NEXT: ; implicit-def: $sgpr10
|
|
; GFX9-NEXT: ; implicit-def: $sgpr76
|
|
; GFX9-NEXT: ; implicit-def: $sgpr75
|
|
; GFX9-NEXT: ; implicit-def: $sgpr74
|
|
; GFX9-NEXT: ; implicit-def: $sgpr73
|
|
; GFX9-NEXT: ; implicit-def: $sgpr72
|
|
; GFX9-NEXT: ; implicit-def: $sgpr8
|
|
; GFX9-NEXT: ; implicit-def: $sgpr63
|
|
; GFX9-NEXT: ; implicit-def: $sgpr62
|
|
; GFX9-NEXT: ; implicit-def: $sgpr61
|
|
; GFX9-NEXT: ; implicit-def: $sgpr60
|
|
; GFX9-NEXT: ; implicit-def: $sgpr59
|
|
; GFX9-NEXT: ; implicit-def: $sgpr6
|
|
; GFX9-NEXT: ; implicit-def: $sgpr58
|
|
; GFX9-NEXT: ; implicit-def: $sgpr57
|
|
; GFX9-NEXT: ; implicit-def: $sgpr56
|
|
; GFX9-NEXT: s_branch .LBB69_2
|
|
;
|
|
; GFX11-LABEL: bitcast_v8i64_to_v64i8_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_xor_saveexec_b32 s4, -1
|
|
; GFX11-NEXT: scratch_store_b32 off, v23, s32 ; 4-byte Folded Spill
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s4
|
|
; GFX11-NEXT: v_writelane_b32 v23, s34, 0
|
|
; GFX11-NEXT: v_writelane_b32 v23, s35, 1
|
|
; GFX11-NEXT: v_writelane_b32 v23, s36, 2
|
|
; GFX11-NEXT: v_writelane_b32 v23, s37, 3
|
|
; GFX11-NEXT: v_writelane_b32 v23, s38, 4
|
|
; GFX11-NEXT: v_writelane_b32 v23, s39, 5
|
|
; GFX11-NEXT: v_writelane_b32 v23, s48, 6
|
|
; GFX11-NEXT: v_writelane_b32 v23, s30, 7
|
|
; GFX11-NEXT: v_writelane_b32 v23, s31, 8
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 vcc_lo, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB69_4
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
|
|
; GFX11-NEXT: s_lshr_b32 s44, s27, 16
|
|
; GFX11-NEXT: s_lshr_b32 s43, s27, 8
|
|
; GFX11-NEXT: s_lshr_b32 s46, s26, 16
|
|
; GFX11-NEXT: s_lshr_b32 s45, s26, 8
|
|
; GFX11-NEXT: s_lshr_b32 s56, s25, 24
|
|
; GFX11-NEXT: s_lshr_b32 s57, s25, 16
|
|
; GFX11-NEXT: s_lshr_b32 s47, s25, 8
|
|
; GFX11-NEXT: s_lshr_b32 s59, s24, 16
|
|
; GFX11-NEXT: s_lshr_b32 s58, s24, 8
|
|
; GFX11-NEXT: s_lshr_b32 s61, s23, 24
|
|
; GFX11-NEXT: s_lshr_b32 s62, s23, 16
|
|
; GFX11-NEXT: s_lshr_b32 s60, s23, 8
|
|
; GFX11-NEXT: s_lshr_b32 s72, s22, 16
|
|
; GFX11-NEXT: s_lshr_b32 s63, s22, 8
|
|
; GFX11-NEXT: s_lshr_b32 s74, s21, 24
|
|
; GFX11-NEXT: s_lshr_b32 s75, s21, 16
|
|
; GFX11-NEXT: s_lshr_b32 s73, s21, 8
|
|
; GFX11-NEXT: s_lshr_b32 s77, s20, 16
|
|
; GFX11-NEXT: s_lshr_b32 s76, s20, 8
|
|
; GFX11-NEXT: s_lshr_b32 s78, s19, 24
|
|
; GFX11-NEXT: s_lshr_b32 s88, s19, 16
|
|
; GFX11-NEXT: s_lshr_b32 s79, s19, 8
|
|
; GFX11-NEXT: s_lshr_b32 s90, s18, 16
|
|
; GFX11-NEXT: s_lshr_b32 s89, s18, 8
|
|
; GFX11-NEXT: s_lshr_b32 s92, s17, 24
|
|
; GFX11-NEXT: s_lshr_b32 s93, s17, 16
|
|
; GFX11-NEXT: s_lshr_b32 s91, s17, 8
|
|
; GFX11-NEXT: s_lshr_b32 s95, s16, 16
|
|
; GFX11-NEXT: s_lshr_b32 s94, s16, 8
|
|
; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 24
|
|
; GFX11-NEXT: s_lshr_b32 s30, s3, 16
|
|
; GFX11-NEXT: s_lshr_b32 s31, s3, 8
|
|
; GFX11-NEXT: s_lshr_b32 s34, s2, 16
|
|
; GFX11-NEXT: s_lshr_b32 s35, s2, 8
|
|
; GFX11-NEXT: s_lshr_b32 s36, s1, 24
|
|
; GFX11-NEXT: s_lshr_b32 s37, s1, 16
|
|
; GFX11-NEXT: s_lshr_b32 s38, s1, 8
|
|
; GFX11-NEXT: s_lshr_b32 s39, s0, 16
|
|
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
|
|
; GFX11-NEXT: s_lshr_b64 s[4:5], s[26:27], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[6:7], s[24:25], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[8:9], s[22:23], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[12:13], s[18:19], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[14:15], s[16:17], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[28:29], s[2:3], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[40:41], s[0:1], 24
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB69_3
|
|
; GFX11-NEXT: .LBB69_2: ; %cmp.true
|
|
; GFX11-NEXT: s_add_u32 s0, s0, 3
|
|
; GFX11-NEXT: s_addc_u32 s1, s1, 0
|
|
; GFX11-NEXT: s_add_u32 s2, s2, 3
|
|
; GFX11-NEXT: s_addc_u32 s3, s3, 0
|
|
; GFX11-NEXT: s_add_u32 s16, s16, 3
|
|
; GFX11-NEXT: s_addc_u32 s17, s17, 0
|
|
; GFX11-NEXT: s_add_u32 s18, s18, 3
|
|
; GFX11-NEXT: s_addc_u32 s19, s19, 0
|
|
; GFX11-NEXT: s_add_u32 s20, s20, 3
|
|
; GFX11-NEXT: s_addc_u32 s21, s21, 0
|
|
; GFX11-NEXT: s_add_u32 s22, s22, 3
|
|
; GFX11-NEXT: s_addc_u32 s23, s23, 0
|
|
; GFX11-NEXT: s_add_u32 s24, s24, 3
|
|
; GFX11-NEXT: s_addc_u32 s25, s25, 0
|
|
; GFX11-NEXT: s_add_u32 s26, s26, 3
|
|
; GFX11-NEXT: s_addc_u32 s27, s27, 0
|
|
; GFX11-NEXT: s_lshr_b64 s[6:7], s[24:25], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[4:5], s[26:27], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[8:9], s[22:23], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[12:13], s[18:19], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[14:15], s[16:17], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[28:29], s[2:3], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[40:41], s[0:1], 24
|
|
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
|
|
; GFX11-NEXT: s_lshr_b32 s44, s27, 16
|
|
; GFX11-NEXT: s_lshr_b32 s43, s27, 8
|
|
; GFX11-NEXT: s_lshr_b32 s46, s26, 16
|
|
; GFX11-NEXT: s_lshr_b32 s45, s26, 8
|
|
; GFX11-NEXT: s_lshr_b32 s56, s25, 24
|
|
; GFX11-NEXT: s_lshr_b32 s57, s25, 16
|
|
; GFX11-NEXT: s_lshr_b32 s47, s25, 8
|
|
; GFX11-NEXT: s_lshr_b32 s59, s24, 16
|
|
; GFX11-NEXT: s_lshr_b32 s58, s24, 8
|
|
; GFX11-NEXT: s_lshr_b32 s61, s23, 24
|
|
; GFX11-NEXT: s_lshr_b32 s62, s23, 16
|
|
; GFX11-NEXT: s_lshr_b32 s60, s23, 8
|
|
; GFX11-NEXT: s_lshr_b32 s72, s22, 16
|
|
; GFX11-NEXT: s_lshr_b32 s63, s22, 8
|
|
; GFX11-NEXT: s_lshr_b32 s74, s21, 24
|
|
; GFX11-NEXT: s_lshr_b32 s75, s21, 16
|
|
; GFX11-NEXT: s_lshr_b32 s73, s21, 8
|
|
; GFX11-NEXT: s_lshr_b32 s77, s20, 16
|
|
; GFX11-NEXT: s_lshr_b32 s76, s20, 8
|
|
; GFX11-NEXT: s_lshr_b32 s78, s19, 24
|
|
; GFX11-NEXT: s_lshr_b32 s88, s19, 16
|
|
; GFX11-NEXT: s_lshr_b32 s79, s19, 8
|
|
; GFX11-NEXT: s_lshr_b32 s90, s18, 16
|
|
; GFX11-NEXT: s_lshr_b32 s89, s18, 8
|
|
; GFX11-NEXT: s_lshr_b32 s92, s17, 24
|
|
; GFX11-NEXT: s_lshr_b32 s93, s17, 16
|
|
; GFX11-NEXT: s_lshr_b32 s91, s17, 8
|
|
; GFX11-NEXT: s_lshr_b32 s95, s16, 16
|
|
; GFX11-NEXT: s_lshr_b32 s94, s16, 8
|
|
; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 24
|
|
; GFX11-NEXT: s_lshr_b32 s30, s3, 16
|
|
; GFX11-NEXT: s_lshr_b32 s31, s3, 8
|
|
; GFX11-NEXT: s_lshr_b32 s34, s2, 16
|
|
; GFX11-NEXT: s_lshr_b32 s35, s2, 8
|
|
; GFX11-NEXT: s_lshr_b32 s36, s1, 24
|
|
; GFX11-NEXT: s_lshr_b32 s37, s1, 16
|
|
; GFX11-NEXT: s_lshr_b32 s38, s1, 8
|
|
; GFX11-NEXT: s_lshr_b32 s39, s0, 16
|
|
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
|
|
; GFX11-NEXT: .LBB69_3: ; %end
|
|
; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
|
|
; GFX11-NEXT: v_readlane_b32 s34, v23, 0
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
|
|
; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
|
|
; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
|
|
; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
|
|
; GFX11-NEXT: v_perm_b32 v6, s2, s35, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
|
|
; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
|
|
; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
|
|
; GFX11-NEXT: v_or_b32_e32 v3, v6, v5
|
|
; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
|
|
; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
|
|
; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
|
|
; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
|
|
; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-NEXT: v_or_b32_e32 v5, v6, v9
|
|
; GFX11-NEXT: v_perm_b32 v9, s88, s78, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
|
|
; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
|
|
; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
|
|
; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
|
|
; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
|
|
; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-NEXT: v_perm_b32 v13, s20, s76, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-NEXT: v_perm_b32 v15, s21, s73, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-NEXT: v_perm_b32 v16, s22, s63, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX11-NEXT: v_or_b32_e32 v9, v13, v10
|
|
; GFX11-NEXT: v_perm_b32 v13, s62, s61, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v10, v15, v11
|
|
; GFX11-NEXT: v_or_b32_e32 v11, v16, v14
|
|
; GFX11-NEXT: v_perm_b32 v14, s59, s6, v12
|
|
; GFX11-NEXT: v_perm_b32 v17, s57, s56, v12
|
|
; GFX11-NEXT: v_perm_b32 v18, s46, s4, v12
|
|
; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
|
|
; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX11-NEXT: v_perm_b32 v21, s26, s45, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_perm_b32 v22, s27, s43, v12
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-NEXT: v_or_b32_e32 v13, v16, v14
|
|
; GFX11-NEXT: v_or_b32_e32 v14, v19, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v15, v21, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v16, v22, v20
|
|
; GFX11-NEXT: v_readlane_b32 s30, v23, 7
|
|
; GFX11-NEXT: s_clause 0x3
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-NEXT: v_readlane_b32 s31, v23, 8
|
|
; GFX11-NEXT: v_readlane_b32 s48, v23, 6
|
|
; GFX11-NEXT: v_readlane_b32 s39, v23, 5
|
|
; GFX11-NEXT: v_readlane_b32 s38, v23, 4
|
|
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
|
|
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
|
|
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
|
|
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
|
|
; GFX11-NEXT: scratch_load_b32 v23, off, s32 ; 4-byte Folded Reload
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s0
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB69_4:
|
|
; GFX11-NEXT: ; implicit-def: $sgpr48
|
|
; GFX11-NEXT: ; implicit-def: $sgpr39
|
|
; GFX11-NEXT: ; implicit-def: $sgpr40
|
|
; GFX11-NEXT: ; implicit-def: $sgpr38
|
|
; GFX11-NEXT: ; implicit-def: $sgpr37
|
|
; GFX11-NEXT: ; implicit-def: $sgpr36
|
|
; GFX11-NEXT: ; implicit-def: $sgpr35
|
|
; GFX11-NEXT: ; implicit-def: $sgpr34
|
|
; GFX11-NEXT: ; implicit-def: $sgpr28
|
|
; GFX11-NEXT: ; implicit-def: $sgpr31
|
|
; GFX11-NEXT: ; implicit-def: $sgpr30
|
|
; GFX11-NEXT: ; implicit-def: $vcc_hi
|
|
; GFX11-NEXT: ; implicit-def: $sgpr94
|
|
; GFX11-NEXT: ; implicit-def: $sgpr95
|
|
; GFX11-NEXT: ; implicit-def: $sgpr14
|
|
; GFX11-NEXT: ; implicit-def: $sgpr91
|
|
; GFX11-NEXT: ; implicit-def: $sgpr93
|
|
; GFX11-NEXT: ; implicit-def: $sgpr92
|
|
; GFX11-NEXT: ; implicit-def: $sgpr89
|
|
; GFX11-NEXT: ; implicit-def: $sgpr90
|
|
; GFX11-NEXT: ; implicit-def: $sgpr12
|
|
; GFX11-NEXT: ; implicit-def: $sgpr79
|
|
; GFX11-NEXT: ; implicit-def: $sgpr88
|
|
; GFX11-NEXT: ; implicit-def: $sgpr78
|
|
; GFX11-NEXT: ; implicit-def: $sgpr76
|
|
; GFX11-NEXT: ; implicit-def: $sgpr77
|
|
; GFX11-NEXT: ; implicit-def: $sgpr10
|
|
; GFX11-NEXT: ; implicit-def: $sgpr73
|
|
; GFX11-NEXT: ; implicit-def: $sgpr75
|
|
; GFX11-NEXT: ; implicit-def: $sgpr74
|
|
; GFX11-NEXT: ; implicit-def: $sgpr63
|
|
; GFX11-NEXT: ; implicit-def: $sgpr72
|
|
; GFX11-NEXT: ; implicit-def: $sgpr8
|
|
; GFX11-NEXT: ; implicit-def: $sgpr60
|
|
; GFX11-NEXT: ; implicit-def: $sgpr62
|
|
; GFX11-NEXT: ; implicit-def: $sgpr61
|
|
; GFX11-NEXT: ; implicit-def: $sgpr58
|
|
; GFX11-NEXT: ; implicit-def: $sgpr59
|
|
; GFX11-NEXT: ; implicit-def: $sgpr6
|
|
; GFX11-NEXT: ; implicit-def: $sgpr47
|
|
; GFX11-NEXT: ; implicit-def: $sgpr57
|
|
; GFX11-NEXT: ; implicit-def: $sgpr56
|
|
; GFX11-NEXT: ; implicit-def: $sgpr45
|
|
; GFX11-NEXT: ; implicit-def: $sgpr46
|
|
; GFX11-NEXT: ; implicit-def: $sgpr4
|
|
; GFX11-NEXT: ; implicit-def: $sgpr43
|
|
; GFX11-NEXT: ; implicit-def: $sgpr44
|
|
; GFX11-NEXT: ; implicit-def: $sgpr42
|
|
; GFX11-NEXT: s_branch .LBB69_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <8 x i64> %a, splat (i64 3)
|
|
%a2 = bitcast <8 x i64> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x i64> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v8i64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v34, v6
|
|
; SI-NEXT: v_mov_b32_e32 v33, v4
|
|
; SI-NEXT: v_mov_b32_e32 v32, v2
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:80
|
|
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:88
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:96
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:104
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:112
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:120
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:128
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 8, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v17
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v8
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v10
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v12
|
|
; SI-NEXT: s_waitcnt vmcnt(10)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v50
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v51
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v52
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v53
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v55
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v40
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v42
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v44
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v58
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v47
|
|
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100
|
|
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB70_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v49
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v1, v48, v1
|
|
; SI-NEXT: v_or_b32_e32 v3, v35, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v57
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v62, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v56, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v52
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v43, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v54, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v44
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v21, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v53
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v27, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v37, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v20, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v24, v6
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v28, v7
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v38
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v17, v8
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v18
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v30
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v63
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v45
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v59
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v46
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v41
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v47
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v51
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v19
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v25
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v50, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: .LBB70_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB70_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
|
|
; SI-NEXT: v_or_b32_e32 v0, v49, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v48, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
|
|
; SI-NEXT: v_or_b32_e32 v1, v39, v1
|
|
; SI-NEXT: s_movk_i32 s6, 0x300
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v35, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v57
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v62, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v42
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v56, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v43, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v54, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v44
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v21, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v27, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: s_mov_b32 s7, 0x3000000
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v36, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v37, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v20, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v24, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v28, v7
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v38, v3
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v17, v8
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v18, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v22, v5
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v26, v6
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v30, v7
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v60
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v63, v8
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v59, v9
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v46, v10
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v41, v11
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v47
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v51, v12
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v19, v13
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v23
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v25, v14
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x300, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v50, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
|
|
; SI-NEXT: .LBB70_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v8i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v53, v1
|
|
; VI-NEXT: v_mov_b32_e32 v54, v0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:128
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:88
|
|
; VI-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; VI-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:80
|
|
; VI-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: v_mov_b32_e32 v31, v15
|
|
; VI-NEXT: v_mov_b32_e32 v32, v14
|
|
; VI-NEXT: v_mov_b32_e32 v33, v13
|
|
; VI-NEXT: v_mov_b32_e32 v34, v12
|
|
; VI-NEXT: v_mov_b32_e32 v35, v11
|
|
; VI-NEXT: v_mov_b32_e32 v36, v10
|
|
; VI-NEXT: v_mov_b32_e32 v37, v9
|
|
; VI-NEXT: v_mov_b32_e32 v38, v8
|
|
; VI-NEXT: v_mov_b32_e32 v39, v7
|
|
; VI-NEXT: v_mov_b32_e32 v48, v6
|
|
; VI-NEXT: v_mov_b32_e32 v49, v5
|
|
; VI-NEXT: v_mov_b32_e32 v50, v4
|
|
; VI-NEXT: v_mov_b32_e32 v51, v3
|
|
; VI-NEXT: v_mov_b32_e32 v52, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:124
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:120
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:116
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:112
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:108
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:104
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:100
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:96
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:92
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB70_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
|
|
; VI-NEXT: v_perm_b32 v3, v48, v39, s6
|
|
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
|
|
; VI-NEXT: v_perm_b32 v2, v50, v49, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
|
|
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v16, v25, v16, s6
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: .LBB70_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB70_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v54
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v53
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v52
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v51
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v50
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v49
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v48
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v39
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_mov_b32_e32 v15, 0x300
|
|
; VI-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; VI-NEXT: v_add_u16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v38
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v37
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v36
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v35
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v33
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v32
|
|
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v31
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; VI-NEXT: v_add_u16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v16
|
|
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v17
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v18
|
|
; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v19
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v4, 0x300, v4
|
|
; VI-NEXT: v_add_u16_sdwa v5, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v20
|
|
; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v21
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v22
|
|
; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v23
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v5, 0x300, v5
|
|
; VI-NEXT: v_add_u16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v30
|
|
; VI-NEXT: v_lshlrev_b16_e32 v10, 8, v27
|
|
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29
|
|
; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v42
|
|
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v63
|
|
; VI-NEXT: v_lshlrev_b16_e32 v14, 8, v59
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(5)
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v7
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v6, 0x300, v6
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; VI-NEXT: s_waitcnt vmcnt(3)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v18, 8, v18
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v7, 0x300, v7
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v57
|
|
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v56
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v26
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
|
|
; VI-NEXT: v_add_u16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v47
|
|
; VI-NEXT: v_lshlrev_b16_e32 v10, 8, v46
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v28
|
|
; VI-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v9, 0x300, v9
|
|
; VI-NEXT: v_add_u16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v45
|
|
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v44
|
|
; VI-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v43
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v10, 0x300, v10
|
|
; VI-NEXT: v_add_u16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v41
|
|
; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v40
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v55
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v11, 0x300, v11
|
|
; VI-NEXT: v_add_u16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v62
|
|
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v61
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v60
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v12, 0x300, v12
|
|
; VI-NEXT: v_add_u16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v58
|
|
; VI-NEXT: v_lshlrev_b16_e32 v14, 8, v24
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v13, 0x300, v13
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: v_or_b32_sdwa v14, v16, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v14, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; VI-NEXT: v_or_b32_sdwa v14, v16, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v16
|
|
; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v16, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v16
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v17, 3, v25
|
|
; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v16
|
|
; VI-NEXT: v_add_u16_sdwa v15, v17, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: .LBB70_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v8i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:128
|
|
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
|
|
; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:80
|
|
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, v15
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, v14
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, v13
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, v12
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, v11
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, v2
|
|
; GFX9-NEXT: s_waitcnt vmcnt(24)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(22)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:124
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:120
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:116
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:112
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:108
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:104
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:100
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:96
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:92
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB70_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v0, v54, v53, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v52, v51, s6
|
|
; GFX9-NEXT: v_perm_b32 v2, v50, v49, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v48, v39, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v2, v38, v37, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v36, v35, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v3, v34, v33, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v32, v31, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v9, v47, v46, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v45, v44, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v42, v30, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v55, v63, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v60, v59, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr22
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v43, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
|
|
; GFX9-NEXT: v_perm_b32 v8, v24, v25, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
|
|
; GFX9-NEXT: v_perm_b32 v9, v26, v27, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
|
|
; GFX9-NEXT: v_perm_b32 v10, v28, v29, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
|
|
; GFX9-NEXT: v_perm_b32 v11, v41, v40, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, v62, v61, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
|
|
; GFX9-NEXT: v_perm_b32 v13, v58, v57, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v16, v56, v16, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: .LBB70_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB70_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v54
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v53
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 3, v52
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v51
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v50
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v49
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v48
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v39
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x300
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v36
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 3, v32
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 3, v18
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 3, v22
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v46
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v44
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v30
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v63
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v59
|
|
; GFX9-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 3, v24
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v25
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
|
|
; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 3, v26
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v27
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 3, v45
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
|
|
; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 3, v28
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 3, v42
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
|
|
; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 3, v41
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v40
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 3, v55
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
|
|
; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 3, v62
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v61
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 3, v60
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
|
|
; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 3, v58
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v57
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v16, 3, v56
|
|
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
|
|
; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX9-NEXT: .LBB70_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v8i64:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1f
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:128
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:124
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:116
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:112
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:108
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:104
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:100
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:96
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:92
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:88
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:84
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:80
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:76
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:72
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:68
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v128, off, s32 offset:132
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v14.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v13.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v12.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v11.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v9.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v7.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v6.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v5.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v4.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v0.l
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v128
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB70_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB70_4
|
|
; GFX11-TRUE16-NEXT: .LBB70_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB70_3: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v119, v118, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v117, v116, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v114, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v113, v112, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v101, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v102, v100, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v99, v98, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v16, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v96, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v30, v87, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v86, v85, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v84, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v81, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v71, v69, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v68, v67, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v65, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v54, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB70_2
|
|
; GFX11-TRUE16-NEXT: .LBB70_4: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v117.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v118.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v116.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v115.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v113.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v114.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v112.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v103.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v102.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v100.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v99.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v101.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v17.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v4.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v97.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v96.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v20.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v4.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v22.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v26.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v27.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v3.h, v4.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v5.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v19.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v21.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v28.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v30.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v23.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v24.l, 3
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v86.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v82.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v81.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v6.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v6.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v25.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v80.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v71.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v68.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v8.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v29.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v87.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v65.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v55.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v54.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v9.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v85.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v84.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v12.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v13.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v52.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v9.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v83.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v51.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v50.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v49.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v70.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v69.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v12.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v13.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v10.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, v37.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v67.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v66.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v35.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v33.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v36.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v64.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v15.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v34.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v32.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v11.h, v11.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v53.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v31.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v17.l, v15.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v17.h, v15.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v12.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v48.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v12.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v13.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v13.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, v38.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v14.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v14.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v39.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v13.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v3.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v4.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v14.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v4.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v18.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v5.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v5.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v6.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v6.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v7.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v8.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v8.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v10.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v10.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v11.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v14.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v14.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v15.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v15.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v16.l
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v8i64:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1f
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:128
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:124
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:120
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:116
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:112
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:108
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:104
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:96
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:92
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:88
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:84
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:80
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:76
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:72
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:68
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:64
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v14
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v34, v12
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB70_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB70_4
|
|
; GFX11-FAKE16-NEXT: .LBB70_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB70_3: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v36, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v119, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v118, v117, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v115, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v112, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v113, v103, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v102, v100, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v101, v99, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v96, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v97, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v83, v81, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v70, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v71, v68, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v65, v55, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB70_2
|
|
; GFX11-FAKE16-NEXT: .LBB70_4: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v36, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v37
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v34, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v35
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v31
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v16, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v22, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v24, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v119
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v118, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v98, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v83, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v84
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v82
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v81
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v80, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v71, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v69, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v67, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v65, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v18, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v70
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v68
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v66
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v64
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v55
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v23, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v25, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v8i64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v28
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s11, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v24
|
|
; SI-NEXT: v_readfirstlane_b32 s13, v23
|
|
; SI-NEXT: v_readfirstlane_b32 s14, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s15, v21
|
|
; SI-NEXT: v_readfirstlane_b32 s40, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s41, v19
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s43, v17
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s45, v15
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s47, v13
|
|
; SI-NEXT: v_readfirstlane_b32 s56, v12
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v30
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s59, v9
|
|
; SI-NEXT: v_readfirstlane_b32 s60, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s61, v7
|
|
; SI-NEXT: v_readfirstlane_b32 s62, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s63, v5
|
|
; SI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s73, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s74, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s75, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s76, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
|
|
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v22
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v24
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v25
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v35
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v37
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
|
|
; SI-NEXT: s_cbranch_scc0 .LBB71_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, s4, v34
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s18, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s77, s19, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s77, s5
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s77, s21, 8
|
|
; SI-NEXT: s_or_b32 s5, s5, s77
|
|
; SI-NEXT: s_and_b32 s77, s22, 0xff
|
|
; SI-NEXT: s_lshl_b32 s77, s77, 16
|
|
; SI-NEXT: s_lshl_b32 s78, s23, 24
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s77, s78, s77
|
|
; SI-NEXT: s_or_b32 s5, s5, s77
|
|
; SI-NEXT: s_and_b32 s77, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s78, s25, 8
|
|
; SI-NEXT: s_or_b32 s77, s77, s78
|
|
; SI-NEXT: s_and_b32 s78, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s78, s78, 16
|
|
; SI-NEXT: s_lshl_b32 s79, s27, 24
|
|
; SI-NEXT: s_and_b32 s77, s77, 0xffff
|
|
; SI-NEXT: s_or_b32 s78, s79, s78
|
|
; SI-NEXT: s_or_b32 s77, s77, s78
|
|
; SI-NEXT: s_and_b32 s78, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s79, s29, 8
|
|
; SI-NEXT: s_or_b32 s78, s78, s79
|
|
; SI-NEXT: s_and_b32 s79, s76, 0xff
|
|
; SI-NEXT: s_lshl_b32 s79, s79, 16
|
|
; SI-NEXT: s_lshl_b32 s88, s75, 24
|
|
; SI-NEXT: s_and_b32 s78, s78, 0xffff
|
|
; SI-NEXT: s_or_b32 s79, s88, s79
|
|
; SI-NEXT: s_or_b32 s78, s78, s79
|
|
; SI-NEXT: s_and_b32 s79, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s88, s73, 8
|
|
; SI-NEXT: s_or_b32 s79, s79, s88
|
|
; SI-NEXT: s_and_b32 s88, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s88, s88, 16
|
|
; SI-NEXT: s_lshl_b32 s89, s63, 24
|
|
; SI-NEXT: s_and_b32 s79, s79, 0xffff
|
|
; SI-NEXT: s_or_b32 s88, s89, s88
|
|
; SI-NEXT: s_or_b32 s79, s79, s88
|
|
; SI-NEXT: s_and_b32 s88, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s89, s61, 8
|
|
; SI-NEXT: s_or_b32 s88, s88, s89
|
|
; SI-NEXT: s_and_b32 s89, s60, 0xff
|
|
; SI-NEXT: s_lshl_b32 s89, s89, 16
|
|
; SI-NEXT: s_lshl_b32 s90, s59, 24
|
|
; SI-NEXT: s_and_b32 s88, s88, 0xffff
|
|
; SI-NEXT: s_or_b32 s89, s90, s89
|
|
; SI-NEXT: s_or_b32 s88, s88, s89
|
|
; SI-NEXT: s_and_b32 s89, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s90, s57, 8
|
|
; SI-NEXT: s_or_b32 s89, s89, s90
|
|
; SI-NEXT: s_and_b32 s90, s56, 0xff
|
|
; SI-NEXT: s_lshl_b32 s90, s90, 16
|
|
; SI-NEXT: s_lshl_b32 s91, s47, 24
|
|
; SI-NEXT: s_and_b32 s89, s89, 0xffff
|
|
; SI-NEXT: s_or_b32 s90, s91, s90
|
|
; SI-NEXT: s_or_b32 s89, s89, s90
|
|
; SI-NEXT: s_and_b32 s90, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s91, s45, 8
|
|
; SI-NEXT: s_or_b32 s90, s90, s91
|
|
; SI-NEXT: s_and_b32 s91, s44, 0xff
|
|
; SI-NEXT: s_lshl_b32 s91, s91, 16
|
|
; SI-NEXT: s_lshl_b32 s92, s43, 24
|
|
; SI-NEXT: s_and_b32 s90, s90, 0xffff
|
|
; SI-NEXT: s_or_b32 s91, s92, s91
|
|
; SI-NEXT: s_or_b32 s90, s90, s91
|
|
; SI-NEXT: s_and_b32 s91, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s92, s41, 8
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v20
|
|
; SI-NEXT: s_or_b32 s91, s91, s92
|
|
; SI-NEXT: s_and_b32 s92, s40, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_lshl_b32 s92, s92, 16
|
|
; SI-NEXT: s_lshl_b32 s93, s15, 24
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v33, v1
|
|
; SI-NEXT: s_and_b32 s91, s91, 0xffff
|
|
; SI-NEXT: s_or_b32 s92, s93, s92
|
|
; SI-NEXT: v_or_b32_e32 v11, v0, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v21
|
|
; SI-NEXT: s_or_b32 s91, s91, s92
|
|
; SI-NEXT: s_and_b32 s92, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s93, s13, 8
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s92, s92, s93
|
|
; SI-NEXT: s_and_b32 s93, s12, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v29, v1
|
|
; SI-NEXT: s_lshl_b32 s93, s93, 16
|
|
; SI-NEXT: s_lshl_b32 s94, s11, 24
|
|
; SI-NEXT: v_or_b32_e32 v13, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v19
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
|
|
; SI-NEXT: s_and_b32 s92, s92, 0xffff
|
|
; SI-NEXT: s_or_b32 s93, s94, s93
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s92, s92, s93
|
|
; SI-NEXT: s_and_b32 s93, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s94, s9, 8
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v25, v1
|
|
; SI-NEXT: s_or_b32 s93, s93, s94
|
|
; SI-NEXT: s_and_b32 s94, s8, 0xff
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v28
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v26
|
|
; SI-NEXT: v_or_b32_e32 v14, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
|
|
; SI-NEXT: s_lshl_b32 s94, s94, 16
|
|
; SI-NEXT: s_lshl_b32 s95, s7, 24
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_and_b32 s93, s93, 0xffff
|
|
; SI-NEXT: s_or_b32 s94, s95, s94
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v31, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v22, v1
|
|
; SI-NEXT: s_or_b32 s93, s93, s94
|
|
; SI-NEXT: v_or_b32_e32 v12, v2, v3
|
|
; SI-NEXT: v_or_b32_e32 v15, v0, v1
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
; SI-NEXT: v_mov_b32_e32 v2, s77
|
|
; SI-NEXT: v_mov_b32_e32 v3, s78
|
|
; SI-NEXT: v_mov_b32_e32 v4, s79
|
|
; SI-NEXT: v_mov_b32_e32 v5, s88
|
|
; SI-NEXT: v_mov_b32_e32 v6, s89
|
|
; SI-NEXT: v_mov_b32_e32 v7, s90
|
|
; SI-NEXT: v_mov_b32_e32 v8, s91
|
|
; SI-NEXT: v_mov_b32_e32 v9, s92
|
|
; SI-NEXT: v_mov_b32_e32 v10, s93
|
|
; SI-NEXT: s_cbranch_execnz .LBB71_3
|
|
; SI-NEXT: .LBB71_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s16, s18, 0xff
|
|
; SI-NEXT: s_addk_i32 s4, 0x300
|
|
; SI-NEXT: s_lshl_b32 s5, s19, 24
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s5, s16
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s16, s21, 8
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_or_b32 s5, s16, s5
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xff
|
|
; SI-NEXT: s_addk_i32 s5, 0x300
|
|
; SI-NEXT: s_lshl_b32 s16, s23, 24
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_or_b32 s5, s16, s5
|
|
; SI-NEXT: s_and_b32 s16, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s25, 8
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s6, s6, 3
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s18, s26, 0xff
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
|
|
; SI-NEXT: s_addk_i32 s16, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s27, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, s6, v34
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s17, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s18, s29, 8
|
|
; SI-NEXT: s_add_i32 s76, s76, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v33, v1
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_and_b32 s19, s76, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_addk_i32 s17, 0x300
|
|
; SI-NEXT: s_lshl_b32 s18, s75, 24
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v28
|
|
; SI-NEXT: s_and_b32 s17, s17, 0xffff
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_add_i32 s74, s74, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_and_b32 s18, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s19, s73, 8
|
|
; SI-NEXT: s_add_i32 s72, s72, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v32, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_and_b32 s20, s72, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_addk_i32 s18, 0x300
|
|
; SI-NEXT: s_lshl_b32 s19, s63, 24
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v31, v1
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xffff
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_add_i32 s62, s62, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_and_b32 s19, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s20, s61, 8
|
|
; SI-NEXT: s_add_i32 s60, s60, 3
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v23
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s21, s60, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v21
|
|
; SI-NEXT: s_addk_i32 s19, 0x300
|
|
; SI-NEXT: s_lshl_b32 s20, s59, 24
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, v30, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s19, s19, 0xffff
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_add_i32 s58, s58, 3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s20, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s21, s57, 8
|
|
; SI-NEXT: s_add_i32 s56, s56, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v29, v1
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s22, s56, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_addk_i32 s20, 0x300
|
|
; SI-NEXT: s_lshl_b32 s21, s47, 24
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
|
|
; SI-NEXT: s_and_b32 s20, s20, 0xffff
|
|
; SI-NEXT: s_or_b32 s21, s21, s22
|
|
; SI-NEXT: s_add_i32 s46, s46, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s21, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s22, s45, 8
|
|
; SI-NEXT: s_add_i32 s44, s44, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v27, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_or_b32 s21, s22, s21
|
|
; SI-NEXT: s_and_b32 s23, s44, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_addk_i32 s21, 0x300
|
|
; SI-NEXT: s_lshl_b32 s22, s43, 24
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v25, v1
|
|
; SI-NEXT: s_and_b32 s21, s21, 0xffff
|
|
; SI-NEXT: s_or_b32 s22, s22, s23
|
|
; SI-NEXT: s_add_i32 s42, s42, 3
|
|
; SI-NEXT: s_add_i32 s14, s14, 3
|
|
; SI-NEXT: s_add_i32 s10, s10, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_or_b32 s21, s22, s21
|
|
; SI-NEXT: s_and_b32 s22, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s23, s41, 8
|
|
; SI-NEXT: s_add_i32 s40, s40, 3
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 8
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 8
|
|
; SI-NEXT: s_add_i32 s8, s8, 3
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
|
|
; SI-NEXT: s_or_b32 s22, s23, s22
|
|
; SI-NEXT: s_and_b32 s23, s40, 0xff
|
|
; SI-NEXT: s_or_b32 s13, s13, s14
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xff
|
|
; SI-NEXT: s_or_b32 s9, s9, s10
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
|
|
; SI-NEXT: s_addk_i32 s22, 0x300
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 24
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_addk_i32 s13, 0x300
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 24
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_addk_i32 s9, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 24
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, v24, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s22, s22, 0xffff
|
|
; SI-NEXT: s_or_b32 s15, s15, s23
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_or_b32 s11, s11, s12
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s8
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s15, s15, s22
|
|
; SI-NEXT: s_or_b32 s11, s11, s13
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v22, v1
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
|
|
; SI-NEXT: s_add_i32 s16, s16, 0x3000000
|
|
; SI-NEXT: s_add_i32 s17, s17, 0x3000000
|
|
; SI-NEXT: s_add_i32 s18, s18, 0x3000000
|
|
; SI-NEXT: s_add_i32 s19, s19, 0x3000000
|
|
; SI-NEXT: s_add_i32 s20, s20, 0x3000000
|
|
; SI-NEXT: s_add_i32 s21, s21, 0x3000000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
; SI-NEXT: v_mov_b32_e32 v2, s16
|
|
; SI-NEXT: v_mov_b32_e32 v3, s17
|
|
; SI-NEXT: v_mov_b32_e32 v4, s18
|
|
; SI-NEXT: v_mov_b32_e32 v5, s19
|
|
; SI-NEXT: v_mov_b32_e32 v6, s20
|
|
; SI-NEXT: v_mov_b32_e32 v7, s21
|
|
; SI-NEXT: v_mov_b32_e32 v8, s15
|
|
; SI-NEXT: v_mov_b32_e32 v9, s11
|
|
; SI-NEXT: v_mov_b32_e32 v10, s7
|
|
; SI-NEXT: .LBB71_3: ; %end
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB71_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_branch .LBB71_2
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v8i64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v30
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v29
|
|
; VI-NEXT: v_readfirstlane_b32 s8, v28
|
|
; VI-NEXT: v_readfirstlane_b32 s9, v27
|
|
; VI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; VI-NEXT: v_readfirstlane_b32 s11, v25
|
|
; VI-NEXT: v_readfirstlane_b32 s12, v24
|
|
; VI-NEXT: v_readfirstlane_b32 s13, v23
|
|
; VI-NEXT: v_readfirstlane_b32 s14, v22
|
|
; VI-NEXT: v_readfirstlane_b32 s15, v21
|
|
; VI-NEXT: v_readfirstlane_b32 s40, v20
|
|
; VI-NEXT: v_readfirstlane_b32 s41, v19
|
|
; VI-NEXT: v_readfirstlane_b32 s42, v18
|
|
; VI-NEXT: v_readfirstlane_b32 s43, v17
|
|
; VI-NEXT: v_readfirstlane_b32 s44, v16
|
|
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: v_readfirstlane_b32 s45, v15
|
|
; VI-NEXT: v_readfirstlane_b32 s46, v14
|
|
; VI-NEXT: v_readfirstlane_b32 s47, v13
|
|
; VI-NEXT: v_readfirstlane_b32 s56, v12
|
|
; VI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; VI-NEXT: v_readfirstlane_b32 s58, v10
|
|
; VI-NEXT: v_readfirstlane_b32 s59, v9
|
|
; VI-NEXT: v_readfirstlane_b32 s60, v8
|
|
; VI-NEXT: v_readfirstlane_b32 s61, v7
|
|
; VI-NEXT: v_readfirstlane_b32 s62, v6
|
|
; VI-NEXT: v_readfirstlane_b32 s63, v5
|
|
; VI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; VI-NEXT: v_readfirstlane_b32 s73, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s74, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s75, v1
|
|
; VI-NEXT: v_readfirstlane_b32 s76, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; VI-NEXT: s_cbranch_scc0 .LBB71_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_mov_b32_e32 v3, s23
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_mov_b32_e32 v2, s21
|
|
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s75
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_mov_b32_e32 v5, s63
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_mov_b32_e32 v4, s73
|
|
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_mov_b32_e32 v5, s61
|
|
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_mov_b32_e32 v7, s47
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_mov_b32_e32 v6, s57
|
|
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_mov_b32_e32 v8, s43
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_mov_b32_e32 v7, s45
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_mov_b32_e32 v9, s15
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_mov_b32_e32 v8, s41
|
|
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_mov_b32_e32 v10, s11
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_mov_b32_e32 v9, s13
|
|
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_mov_b32_e32 v12, s7
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_mov_b32_e32 v10, s9
|
|
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; VI-NEXT: v_perm_b32 v12, v24, v22, s4
|
|
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
|
|
; VI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
|
|
; VI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
|
|
; VI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
|
|
; VI-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; VI-NEXT: s_cbranch_execnz .LBB71_3
|
|
; VI-NEXT: .LBB71_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x300, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s21
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: v_mov_b32_e32 v2, s23
|
|
; VI-NEXT: v_perm_b32 v1, s20, v1, v11
|
|
; VI-NEXT: v_perm_b32 v2, s22, v2, v11
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x300, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x300, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: s_add_i32 s76, s76, 3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s75
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x300, v3
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s74, s74, 3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s73
|
|
; VI-NEXT: s_add_i32 s72, s72, 3
|
|
; VI-NEXT: v_mov_b32_e32 v5, s63
|
|
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x300, v4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s62, s62, 3
|
|
; VI-NEXT: v_mov_b32_e32 v5, s61
|
|
; VI-NEXT: s_add_i32 s60, s60, 3
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x300, v5
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s58, s58, 3
|
|
; VI-NEXT: v_mov_b32_e32 v6, s57
|
|
; VI-NEXT: s_add_i32 s56, s56, 3
|
|
; VI-NEXT: v_mov_b32_e32 v7, s47
|
|
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x300, v6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s46, s46, 3
|
|
; VI-NEXT: v_mov_b32_e32 v7, s45
|
|
; VI-NEXT: s_add_i32 s44, s44, 3
|
|
; VI-NEXT: v_mov_b32_e32 v8, s43
|
|
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x300, v7
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s42, s42, 3
|
|
; VI-NEXT: v_mov_b32_e32 v8, s41
|
|
; VI-NEXT: s_add_i32 s40, s40, 3
|
|
; VI-NEXT: v_mov_b32_e32 v9, s15
|
|
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x300, v8
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s14, s14, 3
|
|
; VI-NEXT: v_mov_b32_e32 v9, s13
|
|
; VI-NEXT: s_add_i32 s12, s12, 3
|
|
; VI-NEXT: v_mov_b32_e32 v10, s11
|
|
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x300, v9
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s10, s10, 3
|
|
; VI-NEXT: v_mov_b32_e32 v10, s9
|
|
; VI-NEXT: s_add_i32 s8, s8, 3
|
|
; VI-NEXT: v_mov_b32_e32 v12, s7
|
|
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x300, v10
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_sdwa v10, v12, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v24
|
|
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
|
|
; VI-NEXT: v_perm_b32 v12, v12, v22, s4
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x300, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v34
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v32
|
|
; VI-NEXT: v_perm_b32 v12, v12, v33, s4
|
|
; VI-NEXT: v_perm_b32 v13, v13, v31, s4
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x300, v12
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v30
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v28
|
|
; VI-NEXT: v_perm_b32 v13, v13, v29, s4
|
|
; VI-NEXT: v_perm_b32 v14, v14, v27, s4
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x300, v13
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v25
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v21
|
|
; VI-NEXT: v_perm_b32 v14, v14, v23, s4
|
|
; VI-NEXT: v_perm_b32 v15, v15, v20, s4
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x300, v14
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v19
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
|
|
; VI-NEXT: v_perm_b32 v15, v15, v18, s4
|
|
; VI-NEXT: v_perm_b32 v16, v17, v16, s4
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x300, v15
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x3000000, v3
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x3000000, v4
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x3000000, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x3000000, v6
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x3000000, v10
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x3000000, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x3000000, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x3000000, v13
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x3000000, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x3000000, v15
|
|
; VI-NEXT: .LBB71_3: ; %end
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB71_4:
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_branch .LBB71_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v8i64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v30
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v29
|
|
; GFX9-NEXT: v_readfirstlane_b32 s8, v28
|
|
; GFX9-NEXT: v_readfirstlane_b32 s9, v27
|
|
; GFX9-NEXT: v_readfirstlane_b32 s10, v26
|
|
; GFX9-NEXT: v_readfirstlane_b32 s11, v25
|
|
; GFX9-NEXT: v_readfirstlane_b32 s12, v24
|
|
; GFX9-NEXT: v_readfirstlane_b32 s13, v23
|
|
; GFX9-NEXT: v_readfirstlane_b32 s14, v22
|
|
; GFX9-NEXT: v_readfirstlane_b32 s15, v21
|
|
; GFX9-NEXT: v_readfirstlane_b32 s40, v20
|
|
; GFX9-NEXT: v_readfirstlane_b32 s41, v19
|
|
; GFX9-NEXT: v_readfirstlane_b32 s42, v18
|
|
; GFX9-NEXT: v_readfirstlane_b32 s43, v17
|
|
; GFX9-NEXT: v_readfirstlane_b32 s44, v16
|
|
; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s46, v14
|
|
; GFX9-NEXT: v_readfirstlane_b32 s47, v13
|
|
; GFX9-NEXT: v_readfirstlane_b32 s56, v12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s57, v11
|
|
; GFX9-NEXT: v_readfirstlane_b32 s58, v10
|
|
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
|
|
; GFX9-NEXT: v_readfirstlane_b32 s60, v8
|
|
; GFX9-NEXT: v_readfirstlane_b32 s61, v7
|
|
; GFX9-NEXT: v_readfirstlane_b32 s62, v6
|
|
; GFX9-NEXT: v_readfirstlane_b32 s63, v5
|
|
; GFX9-NEXT: v_readfirstlane_b32 s72, v4
|
|
; GFX9-NEXT: v_readfirstlane_b32 s73, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s74, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s75, v1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s76, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s75
|
|
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s63
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s73
|
|
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s59
|
|
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s61
|
|
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s47
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s57
|
|
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s43
|
|
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s45
|
|
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s15
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s41
|
|
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s11
|
|
; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s13
|
|
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s7
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s9
|
|
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
|
|
; GFX9-NEXT: .LBB71_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; GFX9-NEXT: s_movk_i32 s4, 0x300
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_add_u32_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u32_sdwa v3, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u32_sdwa v3, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: s_add_i32 s76, s76, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s75
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_add_u32_sdwa v4, v4, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s73
|
|
; GFX9-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s63
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_add_u32_sdwa v5, v5, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s61
|
|
; GFX9-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s59
|
|
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_add_u32_sdwa v6, v6, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s57
|
|
; GFX9-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s47
|
|
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_add_u32_sdwa v7, v7, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s45
|
|
; GFX9-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s43
|
|
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_add_u32_sdwa v8, v8, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s41
|
|
; GFX9-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s15
|
|
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 0x300, v8
|
|
; GFX9-NEXT: v_add_u32_sdwa v9, v9, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s13
|
|
; GFX9-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s11
|
|
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 0x300, v9
|
|
; GFX9-NEXT: v_add_u32_sdwa v10, v10, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s9
|
|
; GFX9-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s7
|
|
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
|
|
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v23
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v21, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v11
|
|
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v34
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v32
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v33, s5
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v31, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v12
|
|
; GFX9-NEXT: v_add_u32_sdwa v13, v13, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v30
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v28
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v29, s5
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v27, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v26
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v22
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v24, s5
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v20, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v14
|
|
; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v18, s5
|
|
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v15
|
|
; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: .LBB71_3: ; %end
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB71_4:
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_branch .LBB71_2
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v8i64_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0xf
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB71_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB71_3
|
|
; GFX11-TRUE16-NEXT: .LBB71_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s24, s25, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s28, s29, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s74, s73, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s62, s61, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s58, s57, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s46, s45, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s42, s41, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s14, s13, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s12, s11, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s10, s9, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v13
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v14, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-TRUE16-NEXT: .LBB71_3: ; %end
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB71_4:
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB71_2
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v8i64_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_clause 0xf
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v30
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v29
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v28
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v27
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v26
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v25
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v24
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v23
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v22
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v21
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v19
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v18
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v16
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v15
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v14
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v13
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v12
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v11
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v10
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v9
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v8
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v7
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v6
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v5
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v4
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v3
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v2
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB71_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB71_3
|
|
; GFX11-FAKE16-NEXT: .LBB71_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s24, s25, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s26, s27, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s28, s29, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s74, s73, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s62, s61, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s58, s57, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s46, s45, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s42, s41, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s13, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s12, s11, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s10, s9, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v13
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v14, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v51
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s8, s7, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s6, s5, v11
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s4, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-FAKE16-NEXT: .LBB71_3: ; %end
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB71_4:
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB71_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <8 x i64>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <8 x i64>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x i64> %phi
|
|
}
|
|
|
|
define <32 x i16> @bitcast_v8f64_to_v32i16(<8 x double> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v32i16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB72_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v28, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB72_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB72_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v28, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB72_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v28
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v25
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v27
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v28
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v32i16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB72_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: .LBB72_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v32i16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB72_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX9-NEXT: .LBB72_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v32i16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB72_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: .LBB72_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define inreg <32 x i16> @bitcast_v8f64_to_v32i16_scalar(<8 x double> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v32i16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB73_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s63, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB73_4
|
|
; SI-NEXT: .LBB73_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[14:15], s[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[16:17], v[14:15], 16
|
|
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[17:18], v[12:13], 16
|
|
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[18:19], v[10:11], 16
|
|
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[19:20], v[8:9], 16
|
|
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[20:21], v[6:7], 16
|
|
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[21:22], v[4:5], 16
|
|
; SI-NEXT: v_lshr_b64 v[22:23], v[2:3], 16
|
|
; SI-NEXT: v_lshr_b64 v[23:24], v[0:1], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
|
|
; SI-NEXT: s_branch .LBB73_5
|
|
; SI-NEXT: .LBB73_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: s_branch .LBB73_2
|
|
; SI-NEXT: .LBB73_4:
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v25, s63
|
|
; SI-NEXT: v_mov_b32_e32 v26, s62
|
|
; SI-NEXT: v_mov_b32_e32 v27, s61
|
|
; SI-NEXT: v_mov_b32_e32 v28, s60
|
|
; SI-NEXT: v_mov_b32_e32 v29, s59
|
|
; SI-NEXT: v_mov_b32_e32 v30, s58
|
|
; SI-NEXT: v_mov_b32_e32 v31, s57
|
|
; SI-NEXT: v_mov_b32_e32 v32, s56
|
|
; SI-NEXT: v_mov_b32_e32 v23, s44
|
|
; SI-NEXT: v_mov_b32_e32 v22, s42
|
|
; SI-NEXT: v_mov_b32_e32 v21, s40
|
|
; SI-NEXT: v_mov_b32_e32 v20, s14
|
|
; SI-NEXT: v_mov_b32_e32 v19, s12
|
|
; SI-NEXT: v_mov_b32_e32 v18, s10
|
|
; SI-NEXT: v_mov_b32_e32 v17, s8
|
|
; SI-NEXT: v_mov_b32_e32 v16, s6
|
|
; SI-NEXT: .LBB73_5: ; %end
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v32
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v22
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v21
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v23
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v22
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v21
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v32i16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB73_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB73_4
|
|
; VI-NEXT: .LBB73_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; VI-NEXT: s_branch .LBB73_5
|
|
; VI-NEXT: .LBB73_3:
|
|
; VI-NEXT: s_branch .LBB73_2
|
|
; VI-NEXT: .LBB73_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB73_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v32i16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB73_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB73_4
|
|
; GFX9-NEXT: .LBB73_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; GFX9-NEXT: s_branch .LBB73_5
|
|
; GFX9-NEXT: .LBB73_3:
|
|
; GFX9-NEXT: s_branch .LBB73_2
|
|
; GFX9-NEXT: .LBB73_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB73_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v32i16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB73_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB73_4
|
|
; GFX11-NEXT: .LBB73_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], s[26:27], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB73_3:
|
|
; GFX11-NEXT: s_branch .LBB73_2
|
|
; GFX11-NEXT: .LBB73_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define <8 x double> @bitcast_v32i16_to_v8f64(<32 x i16> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v8f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v32, v15
|
|
; SI-NEXT: v_mov_b32_e32 v17, v14
|
|
; SI-NEXT: v_mov_b32_e32 v18, v13
|
|
; SI-NEXT: v_mov_b32_e32 v19, v12
|
|
; SI-NEXT: v_mov_b32_e32 v20, v11
|
|
; SI-NEXT: v_mov_b32_e32 v21, v10
|
|
; SI-NEXT: v_mov_b32_e32 v22, v9
|
|
; SI-NEXT: v_mov_b32_e32 v23, v8
|
|
; SI-NEXT: v_mov_b32_e32 v24, v7
|
|
; SI-NEXT: v_mov_b32_e32 v25, v6
|
|
; SI-NEXT: v_mov_b32_e32 v26, v5
|
|
; SI-NEXT: v_mov_b32_e32 v27, v4
|
|
; SI-NEXT: v_mov_b32_e32 v28, v3
|
|
; SI-NEXT: v_mov_b32_e32 v29, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v31
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB74_3
|
|
; SI-NEXT: ; %bb.1: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB74_4
|
|
; SI-NEXT: .LBB74_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB74_3: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v30
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v55
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v54
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v53
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v51
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v50
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v49
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v39
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v38
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v36
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v35
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v34
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v33
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB74_2
|
|
; SI-NEXT: .LBB74_4: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v30
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v29
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v28
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v27
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v26
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v25
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v24
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v23
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v22
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v21
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v20
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v19
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v18
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v17
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v32
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_or_b32_e32 v0, v55, v0
|
|
; SI-NEXT: s_mov_b32 s6, 0x30000
|
|
; SI-NEXT: v_or_b32_e32 v1, v54, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v53, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v52, v3
|
|
; SI-NEXT: v_or_b32_e32 v4, v51, v4
|
|
; SI-NEXT: v_or_b32_e32 v5, v50, v5
|
|
; SI-NEXT: v_or_b32_e32 v6, v49, v6
|
|
; SI-NEXT: v_or_b32_e32 v7, v48, v7
|
|
; SI-NEXT: v_or_b32_e32 v8, v39, v8
|
|
; SI-NEXT: v_or_b32_e32 v9, v38, v9
|
|
; SI-NEXT: v_or_b32_e32 v10, v37, v10
|
|
; SI-NEXT: v_or_b32_e32 v11, v36, v11
|
|
; SI-NEXT: v_or_b32_e32 v12, v35, v12
|
|
; SI-NEXT: v_or_b32_e32 v13, v34, v13
|
|
; SI-NEXT: v_or_b32_e32 v14, v33, v14
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x30000, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x30000, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v8f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB74_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v17, 3
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v15
|
|
; VI-NEXT: v_add_u16_sdwa v15, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v14
|
|
; VI-NEXT: v_add_u16_sdwa v14, v14, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v16, v14
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v13
|
|
; VI-NEXT: v_add_u16_sdwa v13, v13, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v16, v13
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v12
|
|
; VI-NEXT: v_add_u16_sdwa v12, v12, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v11
|
|
; VI-NEXT: v_add_u16_sdwa v11, v11, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v16, v11
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v10
|
|
; VI-NEXT: v_add_u16_sdwa v10, v10, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v16, v10
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v9
|
|
; VI-NEXT: v_add_u16_sdwa v9, v9, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v16, v9
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v8
|
|
; VI-NEXT: v_add_u16_sdwa v8, v8, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v16, v8
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v7
|
|
; VI-NEXT: v_add_u16_sdwa v7, v7, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v16, v7
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v6
|
|
; VI-NEXT: v_add_u16_sdwa v6, v6, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v16, v6
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v5
|
|
; VI-NEXT: v_add_u16_sdwa v5, v5, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v16, v5
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v4
|
|
; VI-NEXT: v_add_u16_sdwa v4, v4, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v3
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v3, v16, v3
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v2
|
|
; VI-NEXT: v_add_u16_sdwa v2, v2, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v16, v2
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v1
|
|
; VI-NEXT: v_add_u16_sdwa v1, v1, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v16, v0
|
|
; VI-NEXT: .LBB74_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v8f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB74_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB74_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v8f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB74_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: .LBB74_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define inreg <8 x double> @bitcast_v32i16_to_v8f64_scalar(<32 x i16> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v8f64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s36, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s37, 1
|
|
; SI-NEXT: v_writelane_b32 v16, s38, 2
|
|
; SI-NEXT: v_writelane_b32 v16, s39, 3
|
|
; SI-NEXT: v_writelane_b32 v16, s48, 4
|
|
; SI-NEXT: v_writelane_b32 v16, s49, 5
|
|
; SI-NEXT: v_writelane_b32 v16, s50, 6
|
|
; SI-NEXT: v_writelane_b32 v16, s51, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v0
|
|
; SI-NEXT: s_lshr_b32 s6, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s8, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s9, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s12, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB75_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s36, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s37, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s38, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s39, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s44, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s45, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s46, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s47, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 16
|
|
; SI-NEXT: s_or_b32 s48, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 16
|
|
; SI-NEXT: s_or_b32 s49, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s50, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s51, s4, s5
|
|
; SI-NEXT: s_cbranch_execnz .LBB75_3
|
|
; SI-NEXT: .LBB75_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s36, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_add_i32 s37, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s38, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_add_i32 s39, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_add_i32 s40, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s41, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_add_i32 s42, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s43, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s44, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s45, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s46, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s47, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s8, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s48, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_add_i32 s49, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s9, s9, 3
|
|
; SI-NEXT: s_add_i32 s50, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s51, s4, 0x30000
|
|
; SI-NEXT: .LBB75_3: ; %end
|
|
; SI-NEXT: v_mov_b32_e32 v0, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s39
|
|
; SI-NEXT: v_mov_b32_e32 v4, s40
|
|
; SI-NEXT: v_mov_b32_e32 v5, s41
|
|
; SI-NEXT: v_mov_b32_e32 v6, s42
|
|
; SI-NEXT: v_mov_b32_e32 v7, s43
|
|
; SI-NEXT: v_mov_b32_e32 v8, s44
|
|
; SI-NEXT: v_mov_b32_e32 v9, s45
|
|
; SI-NEXT: v_mov_b32_e32 v10, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s47
|
|
; SI-NEXT: v_mov_b32_e32 v12, s48
|
|
; SI-NEXT: v_mov_b32_e32 v13, s49
|
|
; SI-NEXT: v_mov_b32_e32 v14, s50
|
|
; SI-NEXT: v_mov_b32_e32 v15, s51
|
|
; SI-NEXT: v_readlane_b32 s51, v16, 7
|
|
; SI-NEXT: v_readlane_b32 s50, v16, 6
|
|
; SI-NEXT: v_readlane_b32 s49, v16, 5
|
|
; SI-NEXT: v_readlane_b32 s48, v16, 4
|
|
; SI-NEXT: v_readlane_b32 s39, v16, 3
|
|
; SI-NEXT: v_readlane_b32 s38, v16, 2
|
|
; SI-NEXT: v_readlane_b32 s37, v16, 1
|
|
; SI-NEXT: v_readlane_b32 s36, v16, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB75_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
|
|
; SI-NEXT: s_branch .LBB75_2
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v8f64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB75_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB75_3
|
|
; VI-NEXT: .LBB75_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s5, s6, 3
|
|
; VI-NEXT: s_and_b32 s4, s6, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s7, 3
|
|
; VI-NEXT: s_add_i32 s6, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s7, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s29, 3
|
|
; VI-NEXT: s_add_i32 s7, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s28, 3
|
|
; VI-NEXT: s_add_i32 s29, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s27, 3
|
|
; VI-NEXT: s_add_i32 s28, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s26, 3
|
|
; VI-NEXT: s_add_i32 s27, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s25, 3
|
|
; VI-NEXT: s_add_i32 s26, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s24, 3
|
|
; VI-NEXT: s_add_i32 s25, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s23, 3
|
|
; VI-NEXT: s_add_i32 s24, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s22, 3
|
|
; VI-NEXT: s_add_i32 s23, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s21, 3
|
|
; VI-NEXT: s_add_i32 s22, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s20, 3
|
|
; VI-NEXT: s_add_i32 s21, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s19, 3
|
|
; VI-NEXT: s_add_i32 s20, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s18, 3
|
|
; VI-NEXT: s_add_i32 s19, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s17, 3
|
|
; VI-NEXT: s_add_i32 s18, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s5, s16, 3
|
|
; VI-NEXT: s_add_i32 s17, s4, 0x30000
|
|
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s16, s4, 0x30000
|
|
; VI-NEXT: .LBB75_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB75_4:
|
|
; VI-NEXT: s_branch .LBB75_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v8f64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB75_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB75_4
|
|
; GFX9-NEXT: .LBB75_2: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, s31, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, s30, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB75_5
|
|
; GFX9-NEXT: .LBB75_3:
|
|
; GFX9-NEXT: s_branch .LBB75_2
|
|
; GFX9-NEXT: .LBB75_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB75_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v8f64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB75_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB75_4
|
|
; GFX11-NEXT: .LBB75_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB75_3:
|
|
; GFX11-NEXT: s_branch .LBB75_2
|
|
; GFX11-NEXT: .LBB75_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define <32 x half> @bitcast_v8f64_to_v32f16(<8 x double> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v32f16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB76_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v28, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB76_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB76_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v14, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v13, v12, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v11, v10, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v8, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v6, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v5, v4, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v3, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v28, v1, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: .LBB76_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v28
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v25
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v27
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v28
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v32f16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB76_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: .LBB76_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v32f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB76_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX9-NEXT: .LBB76_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v32f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB76_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: .LBB76_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define inreg <32 x half> @bitcast_v8f64_to_v32f16_scalar(<8 x double> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v32f16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB77_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s63, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s17, 16
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[16:17], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB77_4
|
|
; SI-NEXT: .LBB77_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[14:15], s[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[16:17], v[14:15], 16
|
|
; SI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[17:18], v[12:13], 16
|
|
; SI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[18:19], v[10:11], 16
|
|
; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[19:20], v[8:9], 16
|
|
; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[20:21], v[6:7], 16
|
|
; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[21:22], v[4:5], 16
|
|
; SI-NEXT: v_lshr_b64 v[22:23], v[2:3], 16
|
|
; SI-NEXT: v_lshr_b64 v[23:24], v[0:1], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v1
|
|
; SI-NEXT: s_branch .LBB77_5
|
|
; SI-NEXT: .LBB77_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: s_branch .LBB77_2
|
|
; SI-NEXT: .LBB77_4:
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v4, s20
|
|
; SI-NEXT: v_mov_b32_e32 v6, s22
|
|
; SI-NEXT: v_mov_b32_e32 v8, s24
|
|
; SI-NEXT: v_mov_b32_e32 v10, s26
|
|
; SI-NEXT: v_mov_b32_e32 v12, s28
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v25, s63
|
|
; SI-NEXT: v_mov_b32_e32 v26, s62
|
|
; SI-NEXT: v_mov_b32_e32 v27, s61
|
|
; SI-NEXT: v_mov_b32_e32 v28, s60
|
|
; SI-NEXT: v_mov_b32_e32 v29, s59
|
|
; SI-NEXT: v_mov_b32_e32 v30, s58
|
|
; SI-NEXT: v_mov_b32_e32 v31, s57
|
|
; SI-NEXT: v_mov_b32_e32 v32, s56
|
|
; SI-NEXT: v_mov_b32_e32 v23, s44
|
|
; SI-NEXT: v_mov_b32_e32 v22, s42
|
|
; SI-NEXT: v_mov_b32_e32 v21, s40
|
|
; SI-NEXT: v_mov_b32_e32 v20, s14
|
|
; SI-NEXT: v_mov_b32_e32 v19, s12
|
|
; SI-NEXT: v_mov_b32_e32 v18, s10
|
|
; SI-NEXT: v_mov_b32_e32 v17, s8
|
|
; SI-NEXT: v_mov_b32_e32 v16, s6
|
|
; SI-NEXT: .LBB77_5: ; %end
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v32
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v22
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v21
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v20
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v18
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v27
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v23
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v22
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v21
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v32f16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB77_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB77_4
|
|
; VI-NEXT: .LBB77_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; VI-NEXT: s_branch .LBB77_5
|
|
; VI-NEXT: .LBB77_3:
|
|
; VI-NEXT: s_branch .LBB77_2
|
|
; VI-NEXT: .LBB77_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB77_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v32f16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB77_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB77_4
|
|
; GFX9-NEXT: .LBB77_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; GFX9-NEXT: s_branch .LBB77_5
|
|
; GFX9-NEXT: .LBB77_3:
|
|
; GFX9-NEXT: s_branch .LBB77_2
|
|
; GFX9-NEXT: .LBB77_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB77_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v32f16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB77_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB77_4
|
|
; GFX11-NEXT: .LBB77_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], s[26:27], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB77_3:
|
|
; GFX11-NEXT: s_branch .LBB77_2
|
|
; GFX11-NEXT: .LBB77_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define <8 x double> @bitcast_v32f16_to_v8f64(<32 x half> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v8f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v32, v15
|
|
; SI-NEXT: v_mov_b32_e32 v17, v14
|
|
; SI-NEXT: v_mov_b32_e32 v18, v13
|
|
; SI-NEXT: v_mov_b32_e32 v19, v12
|
|
; SI-NEXT: v_mov_b32_e32 v20, v11
|
|
; SI-NEXT: v_mov_b32_e32 v21, v10
|
|
; SI-NEXT: v_mov_b32_e32 v22, v9
|
|
; SI-NEXT: v_mov_b32_e32 v23, v8
|
|
; SI-NEXT: v_mov_b32_e32 v24, v7
|
|
; SI-NEXT: v_mov_b32_e32 v25, v6
|
|
; SI-NEXT: v_mov_b32_e32 v26, v5
|
|
; SI-NEXT: v_mov_b32_e32 v27, v4
|
|
; SI-NEXT: v_mov_b32_e32 v28, v3
|
|
; SI-NEXT: v_mov_b32_e32 v29, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v30
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v31
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB78_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v31
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v40
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v55
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v54
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v51
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v50
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v36
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v35
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v34
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: .LBB78_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB78_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v40
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v55
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v31
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v30
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v54
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v29
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v53
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v28
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v27
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v52
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v26
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v50
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v49
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v24
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v48
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v23
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v39
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v22
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v38
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v21
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_or_b32_e32 v9, v11, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v37
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v20
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v36
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v35
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v18
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_or_b32_e32 v12, v14, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v33
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v32
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; SI-NEXT: .LBB78_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v8f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB78_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x200
|
|
; VI-NEXT: v_add_f16_sdwa v17, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v13, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v12, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v11, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v10, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v9, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v8, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v7, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v6, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v5, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v4, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v3, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v17
|
|
; VI-NEXT: v_add_f16_sdwa v17, v1, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
|
|
; VI-NEXT: v_add_f16_sdwa v16, v0, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v17
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: .LBB78_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v8f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB78_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB78_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v8f64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB78_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: .LBB78_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define inreg <8 x double> @bitcast_v32f16_to_v8f64_scalar(<32 x half> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v8f64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v18, s36, 0
|
|
; SI-NEXT: v_writelane_b32 v18, s37, 1
|
|
; SI-NEXT: v_writelane_b32 v18, s38, 2
|
|
; SI-NEXT: v_writelane_b32 v18, s39, 3
|
|
; SI-NEXT: v_writelane_b32 v18, s48, 4
|
|
; SI-NEXT: v_writelane_b32 v18, s49, 5
|
|
; SI-NEXT: v_writelane_b32 v18, s50, 6
|
|
; SI-NEXT: v_writelane_b32 v18, s51, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v0
|
|
; SI-NEXT: s_lshr_b32 s9, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s12, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s58, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s62, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s6, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s8, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB79_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s63, 16
|
|
; SI-NEXT: s_or_b32 s36, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s62, 16
|
|
; SI-NEXT: s_or_b32 s37, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s61, 16
|
|
; SI-NEXT: s_or_b32 s38, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s60, 16
|
|
; SI-NEXT: s_or_b32 s39, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s59, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s58, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s57, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s15, 16
|
|
; SI-NEXT: s_or_b32 s44, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s14, 16
|
|
; SI-NEXT: s_or_b32 s45, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s13, 16
|
|
; SI-NEXT: s_or_b32 s46, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s12, 16
|
|
; SI-NEXT: s_or_b32 s47, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s11, 16
|
|
; SI-NEXT: s_or_b32 s48, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s9, 16
|
|
; SI-NEXT: s_or_b32 s49, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s8, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s10, 16
|
|
; SI-NEXT: s_or_b32 s50, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s7, 16
|
|
; SI-NEXT: s_or_b32 s51, s4, s5
|
|
; SI-NEXT: s_cbranch_execnz .LBB79_4
|
|
; SI-NEXT: .LBB79_2: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s63
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s62
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s17
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s61
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s18
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s60
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s19
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s59
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s21
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s57
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s22
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s56
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s23
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s24
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s14
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s25
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s26
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_or_b32_e32 v9, v11, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s27
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s11
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s28
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_or_b32_e32 v12, v14, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, s7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, s6
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; SI-NEXT: s_branch .LBB79_5
|
|
; SI-NEXT: .LBB79_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43_sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51
|
|
; SI-NEXT: s_branch .LBB79_2
|
|
; SI-NEXT: .LBB79_4:
|
|
; SI-NEXT: v_mov_b32_e32 v0, s36
|
|
; SI-NEXT: v_mov_b32_e32 v1, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s39
|
|
; SI-NEXT: v_mov_b32_e32 v4, s40
|
|
; SI-NEXT: v_mov_b32_e32 v5, s41
|
|
; SI-NEXT: v_mov_b32_e32 v6, s42
|
|
; SI-NEXT: v_mov_b32_e32 v7, s43
|
|
; SI-NEXT: v_mov_b32_e32 v8, s44
|
|
; SI-NEXT: v_mov_b32_e32 v9, s45
|
|
; SI-NEXT: v_mov_b32_e32 v10, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s47
|
|
; SI-NEXT: v_mov_b32_e32 v12, s48
|
|
; SI-NEXT: v_mov_b32_e32 v13, s49
|
|
; SI-NEXT: v_mov_b32_e32 v14, s50
|
|
; SI-NEXT: v_mov_b32_e32 v15, s51
|
|
; SI-NEXT: .LBB79_5: ; %end
|
|
; SI-NEXT: v_readlane_b32 s51, v18, 7
|
|
; SI-NEXT: v_readlane_b32 s50, v18, 6
|
|
; SI-NEXT: v_readlane_b32 s49, v18, 5
|
|
; SI-NEXT: v_readlane_b32 s48, v18, 4
|
|
; SI-NEXT: v_readlane_b32 s39, v18, 3
|
|
; SI-NEXT: v_readlane_b32 s38, v18, 2
|
|
; SI-NEXT: v_readlane_b32 s37, v18, 1
|
|
; SI-NEXT: v_readlane_b32 s36, v18, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v8f64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v17, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v17, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB79_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB79_4
|
|
; VI-NEXT: .LBB79_2: ; %cmp.true
|
|
; VI-NEXT: s_lshr_b32 s4, s31, 16
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s31, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s30, 16
|
|
; VI-NEXT: v_or_b32_e32 v15, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s30, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s29, 16
|
|
; VI-NEXT: v_or_b32_e32 v14, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s29, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s28, 16
|
|
; VI-NEXT: v_or_b32_e32 v13, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s28, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s27, 16
|
|
; VI-NEXT: v_or_b32_e32 v12, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s27, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s26, 16
|
|
; VI-NEXT: v_or_b32_e32 v11, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s26, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s25, 16
|
|
; VI-NEXT: v_or_b32_e32 v10, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s25, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s24, 16
|
|
; VI-NEXT: v_or_b32_e32 v9, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s24, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s23, 16
|
|
; VI-NEXT: v_or_b32_e32 v8, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s23, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s22, 16
|
|
; VI-NEXT: v_or_b32_e32 v7, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s22, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s21, 16
|
|
; VI-NEXT: v_or_b32_e32 v6, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s21, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s20, 16
|
|
; VI-NEXT: v_or_b32_e32 v5, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s20, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s19, 16
|
|
; VI-NEXT: v_or_b32_e32 v4, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s19, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s18, 16
|
|
; VI-NEXT: v_or_b32_e32 v3, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s18, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s17, 16
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v1
|
|
; VI-NEXT: v_mov_b32_e32 v1, s4
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v16, s17, v0
|
|
; VI-NEXT: s_lshr_b32 s4, s16, 16
|
|
; VI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; VI-NEXT: v_mov_b32_e32 v16, s4
|
|
; VI-NEXT: v_add_f16_sdwa v16, v16, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v0, s16, v0
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: s_branch .LBB79_5
|
|
; VI-NEXT: .LBB79_3:
|
|
; VI-NEXT: s_branch .LBB79_2
|
|
; VI-NEXT: .LBB79_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB79_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v17, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v17, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v8f64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB79_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB79_4
|
|
; GFX9-NEXT: .LBB79_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, s31, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, s30, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB79_5
|
|
; GFX9-NEXT: .LBB79_3:
|
|
; GFX9-NEXT: s_branch .LBB79_2
|
|
; GFX9-NEXT: .LBB79_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB79_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v8f64_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB79_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB79_4
|
|
; GFX11-NEXT: .LBB79_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB79_3:
|
|
; GFX11-NEXT: s_branch .LBB79_2
|
|
; GFX11-NEXT: .LBB79_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define <32 x bfloat> @bitcast_v8f64_to_v32bf16(<8 x double> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v32bf16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB80_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: .LBB80_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB80_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; SI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v33, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v49, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v51, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v55, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: .LBB80_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v54
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v53
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v52
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v51
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v48
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v38
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v36
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v35
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v34
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v32
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v28
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v26
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v24
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v22
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v20
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v18
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v32bf16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB80_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; VI-NEXT: .LBB80_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v32bf16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB80_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX9-NEXT: .LBB80_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v32bf16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB80_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], v[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], v[12:13], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], v[10:11], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], v[8:9], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], v[6:7], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0
|
|
; GFX11-NEXT: .LBB80_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define inreg <32 x bfloat> @bitcast_v8f64_to_v32bf16_scalar(<8 x double> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v32bf16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB81_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s79, s5, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s78, s5, 16
|
|
; SI-NEXT: s_and_b32 s77, s4, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s76, s4, 16
|
|
; SI-NEXT: s_and_b32 s75, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s74, s29, 16
|
|
; SI-NEXT: s_and_b32 s73, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s72, s28, 16
|
|
; SI-NEXT: s_and_b32 s63, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s62, s27, 16
|
|
; SI-NEXT: s_and_b32 s61, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s60, s26, 16
|
|
; SI-NEXT: s_and_b32 s59, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s58, s25, 16
|
|
; SI-NEXT: s_and_b32 s57, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s56, s24, 16
|
|
; SI-NEXT: s_and_b32 s47, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s46, s23, 16
|
|
; SI-NEXT: s_and_b32 s45, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s22, 16
|
|
; SI-NEXT: s_and_b32 s43, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s21, 16
|
|
; SI-NEXT: s_and_b32 s41, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s40, s20, 16
|
|
; SI-NEXT: s_and_b32 s15, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s14, s19, 16
|
|
; SI-NEXT: s_and_b32 s13, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s12, s18, 16
|
|
; SI-NEXT: s_and_b32 s11, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s10, s17, 16
|
|
; SI-NEXT: s_and_b32 s9, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s8, s16, 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB81_4
|
|
; SI-NEXT: .LBB81_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[19:20], s[22:23], 1.0
|
|
; SI-NEXT: v_add_f64 v[14:15], s[24:25], 1.0
|
|
; SI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; SI-NEXT: v_add_f64 v[2:3], s[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[6:7], s[28:29], 1.0
|
|
; SI-NEXT: v_add_f64 v[23:24], s[20:21], 1.0
|
|
; SI-NEXT: v_add_f64 v[27:28], s[18:19], 1.0
|
|
; SI-NEXT: v_add_f64 v[30:31], s[16:17], 1.0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v28
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v31
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v31
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
|
|
; SI-NEXT: s_branch .LBB81_5
|
|
; SI-NEXT: .LBB81_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr9
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr11
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr13
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr15
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr41
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr43
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr79
|
|
; SI-NEXT: s_branch .LBB81_2
|
|
; SI-NEXT: .LBB81_4:
|
|
; SI-NEXT: v_mov_b32_e32 v1, s79
|
|
; SI-NEXT: v_mov_b32_e32 v0, s78
|
|
; SI-NEXT: v_mov_b32_e32 v3, s77
|
|
; SI-NEXT: v_mov_b32_e32 v2, s76
|
|
; SI-NEXT: v_mov_b32_e32 v5, s75
|
|
; SI-NEXT: v_mov_b32_e32 v4, s74
|
|
; SI-NEXT: v_mov_b32_e32 v7, s73
|
|
; SI-NEXT: v_mov_b32_e32 v6, s72
|
|
; SI-NEXT: v_mov_b32_e32 v9, s63
|
|
; SI-NEXT: v_mov_b32_e32 v8, s62
|
|
; SI-NEXT: v_mov_b32_e32 v11, s61
|
|
; SI-NEXT: v_mov_b32_e32 v10, s60
|
|
; SI-NEXT: v_mov_b32_e32 v13, s59
|
|
; SI-NEXT: v_mov_b32_e32 v12, s58
|
|
; SI-NEXT: v_mov_b32_e32 v15, s57
|
|
; SI-NEXT: v_mov_b32_e32 v14, s56
|
|
; SI-NEXT: v_mov_b32_e32 v17, s47
|
|
; SI-NEXT: v_mov_b32_e32 v16, s46
|
|
; SI-NEXT: v_mov_b32_e32 v18, s45
|
|
; SI-NEXT: v_mov_b32_e32 v19, s44
|
|
; SI-NEXT: v_mov_b32_e32 v21, s43
|
|
; SI-NEXT: v_mov_b32_e32 v20, s42
|
|
; SI-NEXT: v_mov_b32_e32 v22, s41
|
|
; SI-NEXT: v_mov_b32_e32 v23, s40
|
|
; SI-NEXT: v_mov_b32_e32 v25, s15
|
|
; SI-NEXT: v_mov_b32_e32 v24, s14
|
|
; SI-NEXT: v_mov_b32_e32 v26, s13
|
|
; SI-NEXT: v_mov_b32_e32 v27, s12
|
|
; SI-NEXT: v_mov_b32_e32 v29, s11
|
|
; SI-NEXT: v_mov_b32_e32 v28, s10
|
|
; SI-NEXT: v_mov_b32_e32 v31, s9
|
|
; SI-NEXT: v_mov_b32_e32 v30, s8
|
|
; SI-NEXT: .LBB81_5: ; %end
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
|
|
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v0
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[30:31], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v26
|
|
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v27
|
|
; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v2
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[28:29], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
|
|
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[32:33], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v22
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v23
|
|
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v4
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[24:25], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[26:27], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v18
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v19
|
|
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v6
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[20:21], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[22:23], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v8
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[16:17], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v9
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[14:15], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v10
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[12:13], 16
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[18:19], 16
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[34:35], 16
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[36:37], 16
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[38:39], 16
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[48:49], 16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[50:51], 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v32bf16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v16, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v16, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB81_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB81_4
|
|
; VI-NEXT: .LBB81_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; VI-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; VI-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; VI-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; VI-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; VI-NEXT: s_branch .LBB81_5
|
|
; VI-NEXT: .LBB81_3:
|
|
; VI-NEXT: s_branch .LBB81_2
|
|
; VI-NEXT: .LBB81_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB81_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v16, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v16, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v32bf16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB81_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB81_4
|
|
; GFX9-NEXT: .LBB81_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[14:15], s[30:31], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[12:13], s[28:29], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[10:11], s[26:27], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[8:9], s[24:25], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[6:7], s[22:23], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.0
|
|
; GFX9-NEXT: s_branch .LBB81_5
|
|
; GFX9-NEXT: .LBB81_3:
|
|
; GFX9-NEXT: s_branch .LBB81_2
|
|
; GFX9-NEXT: .LBB81_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB81_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v32bf16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB81_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB81_4
|
|
; GFX11-NEXT: .LBB81_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[14:15], s[26:27], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[12:13], s[24:25], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[10:11], s[22:23], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[8:9], s[20:21], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[6:7], s[18:19], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[4:5], s[16:17], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[2:3], s[14:15], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[0:1], s[12:13], 1.0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB81_3:
|
|
; GFX11-NEXT: s_branch .LBB81_2
|
|
; GFX11-NEXT: .LBB81_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define <8 x double> @bitcast_v32bf16_to_v8f64(<32 x bfloat> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v8f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_mul_f32_e32 v54, 1.0, v32
|
|
; SI-NEXT: v_mul_f32_e32 v55, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v52, 1.0, v31
|
|
; SI-NEXT: v_mul_f32_e32 v53, 1.0, v1
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v51, 1.0, v2
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v49, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v39, 1.0, v4
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
|
|
; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v35, 1.0, v6
|
|
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v8
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v23
|
|
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v10
|
|
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v25, 1.0, v11
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v23, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v19
|
|
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
|
|
; SI-NEXT: v_mul_f32_e32 v19, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB82_3
|
|
; SI-NEXT: ; %bb.1: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execnz .LBB82_4
|
|
; SI-NEXT: .LBB82_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB82_3: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v54
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v52
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v48
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v38
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v16
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v55, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v53, 16
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v51, 16
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v49, 16
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v39, 16
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v37, 16
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v35, 16
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v33, 16
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v31, 16
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v29, 16
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v27, 16
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v25, 16
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v23, 16
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v21, 16
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v19, 16
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v17, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB82_2
|
|
; SI-NEXT: .LBB82_4: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v52
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v53
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v3, v2, 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v50
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v51
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v48
|
|
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v49
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v38
|
|
; SI-NEXT: v_alignbit_b32 v3, v4, v3, 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v36
|
|
; SI-NEXT: v_alignbit_b32 v4, v5, v4, 16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v34
|
|
; SI-NEXT: v_alignbit_b32 v5, v6, v5, 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v32
|
|
; SI-NEXT: v_alignbit_b32 v6, v7, v6, 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v30
|
|
; SI-NEXT: v_alignbit_b32 v7, v8, v7, 16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v28
|
|
; SI-NEXT: v_alignbit_b32 v8, v9, v8, 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
|
|
; SI-NEXT: v_alignbit_b32 v9, v10, v9, 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v24
|
|
; SI-NEXT: v_alignbit_b32 v10, v11, v10, 16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v22
|
|
; SI-NEXT: v_alignbit_b32 v11, v12, v11, 16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v20
|
|
; SI-NEXT: v_alignbit_b32 v12, v13, v12, 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v18
|
|
; SI-NEXT: v_alignbit_b32 v13, v14, v13, 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_alignbit_b32 v14, v15, v14, 16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_alignbit_b32 v15, v16, v15, 16
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v8f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB82_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v15, 16, 1
|
|
; VI-NEXT: s_movk_i32 s6, 0x7fff
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v15
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v14
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v14
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_alignbit_b32 v14, v14, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_alignbit_b32 v13, v13, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v12
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v12, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v12
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v12
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_alignbit_b32 v12, v12, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_alignbit_b32 v11, v11, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v10
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v10, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v10
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v10
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_alignbit_b32 v10, v10, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v9
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_alignbit_b32 v9, v9, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v8
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v8
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_alignbit_b32 v8, v8, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v7
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_alignbit_b32 v7, v7, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v6
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v6
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v6
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_alignbit_b32 v6, v6, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v5
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_alignbit_b32 v5, v5, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v4
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v4, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v4
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_alignbit_b32 v4, v4, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v3
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_alignbit_b32 v3, v3, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v2
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_alignbit_b32 v2, v2, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v1
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_alignbit_b32 v1, v1, v16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
|
|
; VI-NEXT: .LBB82_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v8f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB82_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v15, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v15, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v15
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v18, vcc
|
|
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v14, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v14, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v13, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v13, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v12, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v12, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v12
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v12, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v11, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v10, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v10, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v10
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v10, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v10, v10, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v9, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v9
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v9, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v8, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v8, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v8
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v8, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v7, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v7
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v7, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v6, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v6
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v6, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v6, v6, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v5, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v5, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v4, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v4, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v4, v4, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v3, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v3, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v2, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v1, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v16, s7
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v0, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; GFX9-NEXT: v_perm_b32 v0, v0, v16, s7
|
|
; GFX9-NEXT: .LBB82_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v8f64:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v30, v14
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, v13 :: v_dual_mov_b32 v28, v12
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, v11 :: v_dual_mov_b32 v26, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, v9 :: v_dual_mov_b32 v24, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, v7 :: v_dual_mov_b32 v22, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, v5 :: v_dual_mov_b32 v20, v4
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, v3 :: v_dual_mov_b32 v18, v2
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, v1 :: v_dual_mov_b32 v16, v0
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0
|
|
; GFX11-TRUE16-NEXT: .LBB82_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB82_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_and_b32 v15, 0xffff0000, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v15 :: v_dual_lshlrev_b32 v14, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v23, v17, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v31, v20, v21
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v24, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v22, v25, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v15, 0x40c00000, v18 :: v_dual_cndmask_b32 v30, v19, v16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v18, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v16, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v14, 0x40c00000, v14 :: v_dual_cndmask_b32 v29, v17, v19
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v11
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_lshlrev_b32 v11, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v16, v16, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v15, v17, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v16, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v15, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v14, v16 :: v_dual_and_b32 v12, 0xffff0000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v12, 0x40c00000, v12 :: v_dual_cndmask_b32 v27, v15, v17
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v9
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v13, v15, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v14, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v13, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v12, v14 :: v_dual_and_b32 v10, 0xffff0000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_cndmask_b32 v25, v13, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v7
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_lshlrev_b32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v11, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v11, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v10, v12 :: v_dual_and_b32 v8, 0xffff0000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v8, 0x40c00000, v8 :: v_dual_cndmask_b32 v23, v11, v13
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v5
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v9, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v9, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v10, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v9, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v9 :: v_dual_add_f32 v4, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_cndmask_b32 v4, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v4, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v3, 0x40c00000, v3 :: v_dual_cndmask_b32 v2, v4, v5
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v9, v0, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v4, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v5.h
|
|
; GFX11-TRUE16-NEXT: .LBB82_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v16 :: v_dual_mov_b32 v1, v17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v18 :: v_dual_mov_b32 v3, v19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v20 :: v_dual_mov_b32 v5, v21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v22 :: v_dual_mov_b32 v7, v23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v24 :: v_dual_mov_b32 v9, v25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v26 :: v_dual_mov_b32 v11, v27
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v28 :: v_dual_mov_b32 v13, v29
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v30 :: v_dual_mov_b32 v15, v31
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v8f64:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB82_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v16, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v23, v14, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v15, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v20, v22 :: v_dual_lshlrev_b32 v20, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v21, v18 :: v_dual_add_f32 v18, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_cndmask_b32 v16, v16, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v13, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v12, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v18, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v11, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v10, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v19, v22 :: v_dual_lshlrev_b32 v21, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_lshlrev_b32 v19, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v19, 0x40c00000, v19 :: v_dual_add_f32 v8, 0x40c00000, v8
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v9, 0x40c00000, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v8, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v9, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v18, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v18 :: v_dual_add_f32 v19, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v20 :: v_dual_add_f32 v7, 0x40c00000, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v6, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v17, v7, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v17, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v17, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v18, 0x40c00000, v21 :: v_dual_cndmask_b32 v17, v17, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v19, v22 :: v_dual_lshlrev_b32 v19, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v17, 0x40c00000, v19
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v16, v5, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v16, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v16, v22, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v18, v18, v4, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v20 :: v_dual_lshlrev_b32 v20, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v3, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v2, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v22
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v2, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v20, v21 :: v_dual_lshlrev_b32 v23, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v23
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v19, v21, v22 :: v_dual_add_f32 v0, 0x40c00000, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v20, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v1, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v22, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v21, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
|
|
; GFX11-FAKE16-NEXT: .LBB82_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define inreg <8 x double> @bitcast_v32bf16_to_v8f64_scalar(<32 x bfloat> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v8f64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v0
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s5, s29, 16
|
|
; SI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s28, 16
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s9, s27, 16
|
|
; SI-NEXT: s_and_b32 s10, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s26, 16
|
|
; SI-NEXT: s_and_b32 s12, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s25, 16
|
|
; SI-NEXT: s_and_b32 s14, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s24, 16
|
|
; SI-NEXT: s_and_b32 s24, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_and_b32 s25, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: s_and_b32 s26, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s27, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s28, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: s_and_b32 s29, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s40, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s41, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s43, s42, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s42, 16
|
|
; SI-NEXT: s_and_b32 s45, s44, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s46, 0
|
|
; SI-NEXT: v_mul_f32_e64 v41, 1.0, s41
|
|
; SI-NEXT: v_mul_f32_e64 v52, 1.0, s16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v63, 1.0, s40
|
|
; SI-NEXT: v_mul_f32_e64 v48, 1.0, s17
|
|
; SI-NEXT: v_mul_f32_e64 v62, 1.0, s29
|
|
; SI-NEXT: v_mul_f32_e64 v61, 1.0, s28
|
|
; SI-NEXT: v_mul_f32_e64 v60, 1.0, s27
|
|
; SI-NEXT: v_mul_f32_e64 v59, 1.0, s26
|
|
; SI-NEXT: v_mul_f32_e64 v58, 1.0, s25
|
|
; SI-NEXT: v_mul_f32_e64 v57, 1.0, s24
|
|
; SI-NEXT: v_mul_f32_e64 v56, 1.0, s14
|
|
; SI-NEXT: v_mul_f32_e64 v47, 1.0, s12
|
|
; SI-NEXT: v_mul_f32_e64 v46, 1.0, s10
|
|
; SI-NEXT: v_mul_f32_e64 v45, 1.0, s8
|
|
; SI-NEXT: v_mul_f32_e64 v44, 1.0, s6
|
|
; SI-NEXT: v_mul_f32_e64 v43, 1.0, s4
|
|
; SI-NEXT: v_mul_f32_e64 v42, 1.0, s45
|
|
; SI-NEXT: v_mul_f32_e64 v16, 1.0, s43
|
|
; SI-NEXT: v_mul_f32_e64 v39, 1.0, s18
|
|
; SI-NEXT: v_mul_f32_e64 v54, 1.0, s19
|
|
; SI-NEXT: v_mul_f32_e64 v50, 1.0, s20
|
|
; SI-NEXT: v_mul_f32_e64 v37, 1.0, s21
|
|
; SI-NEXT: v_mul_f32_e64 v35, 1.0, s22
|
|
; SI-NEXT: v_mul_f32_e64 v33, 1.0, s23
|
|
; SI-NEXT: v_mul_f32_e64 v31, 1.0, s15
|
|
; SI-NEXT: v_mul_f32_e64 v29, 1.0, s13
|
|
; SI-NEXT: v_mul_f32_e64 v27, 1.0, s11
|
|
; SI-NEXT: v_mul_f32_e64 v25, 1.0, s9
|
|
; SI-NEXT: v_mul_f32_e64 v23, 1.0, s7
|
|
; SI-NEXT: v_mul_f32_e64 v21, 1.0, s5
|
|
; SI-NEXT: v_mul_f32_e64 v19, 1.0, s44
|
|
; SI-NEXT: v_mul_f32_e64 v17, 1.0, s42
|
|
; SI-NEXT: s_cbranch_scc0 .LBB83_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v63
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[52:53], 16
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v62
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[39:40], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 16, v61
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[54:55], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v60
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[50:51], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v59
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[37:38], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v58
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[35:36], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 16, v57
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[33:34], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v56
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[31:32], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v47
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[29:30], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v46
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[27:28], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v45
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[25:26], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v44
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[23:24], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v43
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[21:22], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v42
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[19:20], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v16
|
|
; SI-NEXT: v_mov_b32_e32 v20, v16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[17:18], 16
|
|
; SI-NEXT: v_mov_b32_e32 v16, v20
|
|
; SI-NEXT: s_cbranch_execnz .LBB83_3
|
|
; SI-NEXT: .LBB83_2: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v52
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v63
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v48
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[2:3], 16
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v62
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v61
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v54
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v60
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v50
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v59
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v58
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v57
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v56
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v47
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v46
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v45
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v25
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v44
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v43
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v42
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
|
|
; SI-NEXT: .LBB83_3: ; %end
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB83_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_branch .LBB83_2
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v8f64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v20, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v20, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB83_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB83_4
|
|
; VI-NEXT: .LBB83_2: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
|
|
; VI-NEXT: s_lshl_b32 s4, s30, 16
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
|
|
; VI-NEXT: v_add_f32_e32 v1, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s28, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; VI-NEXT: v_add_f32_e32 v2, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[0:1]
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v3, v4, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: s_and_b32 s5, s26, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s26, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s24, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s24, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s22, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s22, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s20, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s20, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s18, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s5, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: s_lshl_b32 s4, s18, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
|
|
; VI-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v0
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s16, 16
|
|
; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v0, v0
|
|
; VI-NEXT: v_add_f32_e32 v0, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s17, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v1, v3, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s19, 16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v1, v5, s[4:5]
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v9, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v3
|
|
; VI-NEXT: s_lshl_b32 s6, s21, 16
|
|
; VI-NEXT: v_mov_b32_e32 v1, v17
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v5, v7, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v16
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v9, v11, vcc
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v5, v5
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v3
|
|
; VI-NEXT: v_bfe_u32 v11, v5, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v5
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: s_lshl_b32 s6, s23, 16
|
|
; VI-NEXT: v_mov_b32_e32 v3, v17
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v7, v9, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v11, v13, vcc
|
|
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v7, v7
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v13, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v7
|
|
; VI-NEXT: s_lshl_b32 s6, s25, 16
|
|
; VI-NEXT: v_mov_b32_e32 v5, v17
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v9, v11, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v16
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v13, v15, vcc
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v9, v9
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
|
|
; VI-NEXT: v_bfe_u32 v15, v9, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v9
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v7, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v15, v17, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s27, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v11, v13, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v11, v11
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v16
|
|
; VI-NEXT: v_mov_b32_e32 v9, v17
|
|
; VI-NEXT: v_bfe_u32 v17, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v11
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: s_and_b32 s7, s31, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
|
|
; VI-NEXT: v_cndmask_b32_e64 v17, v13, v15, s[4:5]
|
|
; VI-NEXT: v_add_f32_e32 v13, s7, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: s_lshl_b32 s6, s31, 16
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v11, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: s_lshl_b32 s4, s29, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
|
|
; VI-NEXT: v_add_f32_e32 v15, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[17:18]
|
|
; VI-NEXT: v_mov_b32_e32 v13, v15
|
|
; VI-NEXT: v_mov_b32_e32 v15, v16
|
|
; VI-NEXT: s_branch .LBB83_5
|
|
; VI-NEXT: .LBB83_3:
|
|
; VI-NEXT: s_branch .LBB83_2
|
|
; VI-NEXT: .LBB83_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB83_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v20, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v20, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v8f64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB83_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB83_4
|
|
; GFX9-NEXT: .LBB83_2: ; %cmp.true
|
|
; GFX9-NEXT: s_and_b32 s4, s31, 0xffff0000
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s31, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v3, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: s_lshl_b32 s4, s30, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v4, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, 0xffff
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v1, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v3
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s29, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s28, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s27, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s26, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s25, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s24, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s23, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s22, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s21, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s20, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s19, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s18, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v17, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s17, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v17, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: s_lshl_b32 s4, s16, 16
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v0, s4, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v0, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v0
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_and_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v16
|
|
; GFX9-NEXT: s_branch .LBB83_5
|
|
; GFX9-NEXT: .LBB83_3:
|
|
; GFX9-NEXT: s_branch .LBB83_2
|
|
; GFX9-NEXT: .LBB83_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB83_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v20, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v8f64_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB83_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB83_4
|
|
; GFX11-TRUE16-NEXT: .LBB83_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s27, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s26, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v7, v7, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v9, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v5, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v2, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v8, v5
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_add_nc_u32 v0, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v7, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v5, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v17, v5
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v17 :: v_dual_add_nc_u32 v3, v3, v4
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, v5, v16
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s15, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v19, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s12, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v16, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v17, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v16, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v18, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v0, v18, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v16, v20, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v19
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, v0, v18
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v16, v19, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s12, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v0, v19 :: v_dual_add_nc_u32 v19, v21, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, v22, v17
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v20, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v21, v22, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v1.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v23, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v24, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v17.l
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB83_3:
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB83_2
|
|
; GFX11-TRUE16-NEXT: .LBB83_4:
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v8f64_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB83_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB83_4
|
|
; GFX11-FAKE16-NEXT: .LBB83_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s26, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s25, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s25, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s24, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v9, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v4, v7 :: v_dual_add_nc_u32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s23, 16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s22, 16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s20, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v8, v7
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v6, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s18, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s17, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v6, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v7, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v17, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v19, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v18, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v16, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v17, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v0, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v6, v16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x7fff, v0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s15, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v17
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v17, v18 :: v_dual_add_nc_u32 v17, v19, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s12, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v17, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s12, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v24
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v23, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v2, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v21, v24, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v18, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v16, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v20, 16, v17
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB83_3:
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB83_2
|
|
; GFX11-FAKE16-NEXT: .LBB83_4:
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v64i8:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; kill: killed $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB84_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_alignbit_b32 v17, v16, v15, 24
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v15, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v16, v15, 8
|
|
; SI-NEXT: v_alignbit_b32 v20, v14, v13, 24
|
|
; SI-NEXT: v_alignbit_b32 v21, v14, v13, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v14, v13, 8
|
|
; SI-NEXT: v_alignbit_b32 v23, v12, v11, 24
|
|
; SI-NEXT: v_alignbit_b32 v24, v12, v11, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v12, v11, 8
|
|
; SI-NEXT: v_alignbit_b32 v28, v10, v9, 24
|
|
; SI-NEXT: v_alignbit_b32 v30, v10, v9, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v10, v9, 8
|
|
; SI-NEXT: v_alignbit_b32 v35, v8, v7, 24
|
|
; SI-NEXT: v_alignbit_b32 v36, v8, v7, 16
|
|
; SI-NEXT: v_alignbit_b32 v37, v8, v7, 8
|
|
; SI-NEXT: v_alignbit_b32 v49, v6, v5, 24
|
|
; SI-NEXT: v_alignbit_b32 v50, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v51, v6, v5, 8
|
|
; SI-NEXT: v_alignbit_b32 v55, v4, v3, 24
|
|
; SI-NEXT: v_alignbit_b32 v40, v4, v3, 16
|
|
; SI-NEXT: v_alignbit_b32 v43, v4, v3, 8
|
|
; SI-NEXT: v_alignbit_b32 v47, v2, v1, 24
|
|
; SI-NEXT: v_alignbit_b32 v57, v2, v1, 16
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_alignbit_b32 v58, v2, v1, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 24, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v41, 24, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v56, 8, v6
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v4
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v4
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v2
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
|
|
; SI-NEXT: .LBB84_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB84_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0
|
|
; SI-NEXT: v_add_f64 v[1:2], v[1:2], 1.0
|
|
; SI-NEXT: v_add_f64 v[3:4], v[3:4], 1.0
|
|
; SI-NEXT: v_add_f64 v[5:6], v[5:6], 1.0
|
|
; SI-NEXT: v_add_f64 v[7:8], v[7:8], 1.0
|
|
; SI-NEXT: v_add_f64 v[9:10], v[9:10], 1.0
|
|
; SI-NEXT: v_add_f64 v[11:12], v[11:12], 1.0
|
|
; SI-NEXT: v_add_f64 v[13:14], v[13:14], 1.0
|
|
; SI-NEXT: v_alignbit_b32 v17, v16, v15, 24
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v15, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v16, v15, 8
|
|
; SI-NEXT: v_alignbit_b32 v20, v14, v13, 24
|
|
; SI-NEXT: v_alignbit_b32 v21, v14, v13, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v14, v13, 8
|
|
; SI-NEXT: v_alignbit_b32 v23, v12, v11, 24
|
|
; SI-NEXT: v_alignbit_b32 v24, v12, v11, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v12, v11, 8
|
|
; SI-NEXT: v_alignbit_b32 v28, v10, v9, 24
|
|
; SI-NEXT: v_alignbit_b32 v30, v10, v9, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v10, v9, 8
|
|
; SI-NEXT: v_alignbit_b32 v35, v8, v7, 24
|
|
; SI-NEXT: v_alignbit_b32 v36, v8, v7, 16
|
|
; SI-NEXT: v_alignbit_b32 v37, v8, v7, 8
|
|
; SI-NEXT: v_alignbit_b32 v49, v6, v5, 24
|
|
; SI-NEXT: v_alignbit_b32 v50, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v51, v6, v5, 8
|
|
; SI-NEXT: v_alignbit_b32 v55, v4, v3, 24
|
|
; SI-NEXT: v_alignbit_b32 v40, v4, v3, 16
|
|
; SI-NEXT: v_alignbit_b32 v43, v4, v3, 8
|
|
; SI-NEXT: v_alignbit_b32 v47, v2, v1, 24
|
|
; SI-NEXT: v_alignbit_b32 v57, v2, v1, 16
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_alignbit_b32 v58, v2, v1, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 8, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 24, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 8, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v41, 24, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 8, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v56, 8, v6
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 24, v4
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v4
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v4
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v2
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 8, v2
|
|
; SI-NEXT: .LBB84_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v58, 8, v58
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_and_b32_e32 v57, 0xff, v57
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v57
|
|
; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v47
|
|
; SI-NEXT: v_or_b32_e32 v47, v47, v57
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v47
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v17
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v63
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v62
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v17, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v40
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v55
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v61
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v60
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v59
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v51
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v50
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v49
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v56
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v46
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v45
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v37
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v35
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v44
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v41
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v31
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v28
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v54
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v53
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v52
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v25
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v48
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v38
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v22
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v20
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v34
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v32
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v19
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v29
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v26
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v64i8:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB84_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: v_mov_b32_e32 v27, v21
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: .LBB84_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB84_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[15:16], v[15:16], 1.0
|
|
; VI-NEXT: v_add_f64 v[13:14], v[13:14], 1.0
|
|
; VI-NEXT: v_add_f64 v[11:12], v[11:12], 1.0
|
|
; VI-NEXT: v_add_f64 v[3:4], v[3:4], 1.0
|
|
; VI-NEXT: v_add_f64 v[7:8], v[7:8], 1.0
|
|
; VI-NEXT: v_add_f64 v[9:10], v[9:10], 1.0
|
|
; VI-NEXT: v_add_f64 v[1:2], v[1:2], 1.0
|
|
; VI-NEXT: v_add_f64 v[5:6], v[5:6], 1.0
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: .LBB84_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v21
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; VI-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
|
|
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
|
|
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
|
|
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v64i8:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB84_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v16
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, v22
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: .LBB84_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB84_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[15:16], v[15:16], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[13:14], v[13:14], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[11:12], v[11:12], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[9:10], v[9:10], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[3:4], v[3:4], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[7:8], v[7:8], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[1:2], v[1:2], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[5:6], v[5:6], 1.0
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: .LBB84_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v22, v30, v24, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v22, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v21, v62, v21, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v61, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v21, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v43, v23, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v54, v20, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v27, v25, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v8f64_to_v64i8:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB84_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB84_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB84_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_f64 v[15:16], v[15:16], 1.0
|
|
; GFX11-TRUE16-NEXT: v_add_f64 v[13:14], v[13:14], 1.0
|
|
; GFX11-TRUE16-NEXT: v_add_f64 v[11:12], v[11:12], 1.0
|
|
; GFX11-TRUE16-NEXT: v_add_f64 v[9:10], v[9:10], 1.0
|
|
; GFX11-TRUE16-NEXT: v_add_f64 v[7:8], v[7:8], 1.0
|
|
; GFX11-TRUE16-NEXT: v_add_f64 v[5:6], v[5:6], 1.0
|
|
; GFX11-TRUE16-NEXT: v_add_f64 v[3:4], v[3:4], 1.0
|
|
; GFX11-TRUE16-NEXT: v_add_f64 v[1:2], v[1:2], 1.0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB84_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
|
|
; GFX11-TRUE16-NEXT: s_clause 0x3
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v8f64_to_v64i8:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB84_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB84_2: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB84_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_f64 v[15:16], v[15:16], 1.0
|
|
; GFX11-FAKE16-NEXT: v_add_f64 v[13:14], v[13:14], 1.0
|
|
; GFX11-FAKE16-NEXT: v_add_f64 v[11:12], v[11:12], 1.0
|
|
; GFX11-FAKE16-NEXT: v_add_f64 v[9:10], v[9:10], 1.0
|
|
; GFX11-FAKE16-NEXT: v_add_f64 v[7:8], v[7:8], 1.0
|
|
; GFX11-FAKE16-NEXT: v_add_f64 v[5:6], v[5:6], 1.0
|
|
; GFX11-FAKE16-NEXT: v_add_f64 v[3:4], v[3:4], 1.0
|
|
; GFX11-FAKE16-NEXT: v_add_f64 v[1:2], v[1:2], 1.0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB84_4: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
|
|
; GFX11-FAKE16-NEXT: s_clause 0x3
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v8f64_to_v64i8_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v40, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v40, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v40, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v40, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v40, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v40, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v40, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v40, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v40, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v40, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v40, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v40, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v40, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v40, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v40, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v40, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v40, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v40, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v40, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v40, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v40, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v40, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v40, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v40, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v40, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v40, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v40, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v40, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v40, s86, 28
|
|
; SI-NEXT: v_writelane_b32 v40, s87, 29
|
|
; SI-NEXT: v_writelane_b32 v40, s30, 30
|
|
; SI-NEXT: v_writelane_b32 v40, s31, 31
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; SI-NEXT: s_cbranch_scc0 .LBB85_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshr_b32 s48, s5, 24
|
|
; SI-NEXT: s_lshr_b32 s49, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s50, s5, 8
|
|
; SI-NEXT: s_lshr_b32 s51, s29, 24
|
|
; SI-NEXT: s_lshr_b32 s52, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s53, s29, 8
|
|
; SI-NEXT: s_lshr_b32 s54, s27, 24
|
|
; SI-NEXT: s_lshr_b32 s55, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s64, s27, 8
|
|
; SI-NEXT: s_lshr_b32 s65, s25, 24
|
|
; SI-NEXT: s_lshr_b32 s66, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s67, s25, 8
|
|
; SI-NEXT: s_lshr_b32 s68, s23, 24
|
|
; SI-NEXT: s_lshr_b32 s69, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s70, s23, 8
|
|
; SI-NEXT: s_lshr_b32 s71, s21, 24
|
|
; SI-NEXT: s_lshr_b32 s80, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s81, s21, 8
|
|
; SI-NEXT: s_lshr_b32 s82, s19, 24
|
|
; SI-NEXT: s_lshr_b32 s83, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s84, s19, 8
|
|
; SI-NEXT: s_lshr_b32 s85, s17, 24
|
|
; SI-NEXT: s_lshr_b32 s86, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s87, s17, 8
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[10:11], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[4:5], 8
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[28:29], 24
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[28:29], 16
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[28:29], 8
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[24:25], 24
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[24:25], 8
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[22:23], 24
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[22:23], 16
|
|
; SI-NEXT: s_lshr_b64 s[38:39], s[22:23], 8
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[40:41], s[20:21], 8
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[18:19], 8
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[16:17], 8
|
|
; SI-NEXT: s_cbranch_execnz .LBB85_4
|
|
; SI-NEXT: .LBB85_2: ; %cmp.true
|
|
; SI-NEXT: v_add_f64 v[28:29], s[18:19], 1.0
|
|
; SI-NEXT: v_add_f64 v[5:6], s[26:27], 1.0
|
|
; SI-NEXT: v_add_f64 v[13:14], s[22:23], 1.0
|
|
; SI-NEXT: v_add_f64 v[3:4], s[28:29], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[48:49], v[28:29], 24
|
|
; SI-NEXT: v_add_f64 v[1:2], s[4:5], 1.0
|
|
; SI-NEXT: v_add_f64 v[7:8], s[24:25], 1.0
|
|
; SI-NEXT: v_add_f64 v[20:21], s[20:21], 1.0
|
|
; SI-NEXT: v_add_f64 v[32:33], s[16:17], 1.0
|
|
; SI-NEXT: v_lshr_b64 v[22:23], v[5:6], 16
|
|
; SI-NEXT: v_lshr_b64 v[34:35], v[13:14], 16
|
|
; SI-NEXT: v_lshr_b64 v[49:50], v[28:29], 16
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[3:4], 24
|
|
; SI-NEXT: v_lshr_b64 v[23:24], v[5:6], 8
|
|
; SI-NEXT: v_lshr_b64 v[35:36], v[13:14], 8
|
|
; SI-NEXT: v_lshr_b64 v[50:51], v[28:29], 8
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[1:2], 24
|
|
; SI-NEXT: v_lshr_b64 v[16:17], v[3:4], 16
|
|
; SI-NEXT: v_lshr_b64 v[24:25], v[7:8], 24
|
|
; SI-NEXT: v_lshr_b64 v[36:37], v[20:21], 24
|
|
; SI-NEXT: v_lshr_b64 v[51:52], v[32:33], 24
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[1:2], 16
|
|
; SI-NEXT: v_lshr_b64 v[17:18], v[3:4], 8
|
|
; SI-NEXT: v_lshr_b64 v[25:26], v[7:8], 16
|
|
; SI-NEXT: v_lshr_b64 v[37:38], v[20:21], 16
|
|
; SI-NEXT: v_lshr_b64 v[52:53], v[32:33], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s17, v33
|
|
; SI-NEXT: v_readfirstlane_b32 s19, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s21, v21
|
|
; SI-NEXT: v_readfirstlane_b32 s23, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s25, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s27, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s29, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[1:2], 8
|
|
; SI-NEXT: v_lshr_b64 v[18:19], v[5:6], 24
|
|
; SI-NEXT: v_lshr_b64 v[26:27], v[7:8], 8
|
|
; SI-NEXT: v_lshr_b64 v[30:31], v[13:14], 24
|
|
; SI-NEXT: v_lshr_b64 v[38:39], v[20:21], 8
|
|
; SI-NEXT: v_lshr_b64 v[53:54], v[32:33], 8
|
|
; SI-NEXT: s_lshr_b32 s48, s5, 24
|
|
; SI-NEXT: s_lshr_b32 s49, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s50, s5, 8
|
|
; SI-NEXT: s_lshr_b32 s51, s29, 24
|
|
; SI-NEXT: s_lshr_b32 s52, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s53, s29, 8
|
|
; SI-NEXT: s_lshr_b32 s54, s27, 24
|
|
; SI-NEXT: s_lshr_b32 s55, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s64, s27, 8
|
|
; SI-NEXT: s_lshr_b32 s65, s25, 24
|
|
; SI-NEXT: s_lshr_b32 s66, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s67, s25, 8
|
|
; SI-NEXT: s_lshr_b32 s68, s23, 24
|
|
; SI-NEXT: s_lshr_b32 s69, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s70, s23, 8
|
|
; SI-NEXT: s_lshr_b32 s71, s21, 24
|
|
; SI-NEXT: s_lshr_b32 s80, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s81, s21, 8
|
|
; SI-NEXT: s_lshr_b32 s82, s19, 24
|
|
; SI-NEXT: s_lshr_b32 s83, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s84, s19, 8
|
|
; SI-NEXT: s_lshr_b32 s85, s17, 24
|
|
; SI-NEXT: s_lshr_b32 s86, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s87, s17, 8
|
|
; SI-NEXT: s_branch .LBB85_5
|
|
; SI-NEXT: .LBB85_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr87
|
|
; SI-NEXT: ; implicit-def: $sgpr86
|
|
; SI-NEXT: ; implicit-def: $sgpr85
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr84
|
|
; SI-NEXT: ; implicit-def: $sgpr83
|
|
; SI-NEXT: ; implicit-def: $sgpr82
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr81
|
|
; SI-NEXT: ; implicit-def: $sgpr80
|
|
; SI-NEXT: ; implicit-def: $sgpr71
|
|
; SI-NEXT: ; implicit-def: $sgpr70
|
|
; SI-NEXT: ; implicit-def: $sgpr69
|
|
; SI-NEXT: ; implicit-def: $sgpr68
|
|
; SI-NEXT: ; implicit-def: $sgpr67
|
|
; SI-NEXT: ; implicit-def: $sgpr66
|
|
; SI-NEXT: ; implicit-def: $sgpr65
|
|
; SI-NEXT: ; implicit-def: $sgpr64
|
|
; SI-NEXT: ; implicit-def: $sgpr55
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr53
|
|
; SI-NEXT: ; implicit-def: $sgpr52
|
|
; SI-NEXT: ; implicit-def: $sgpr51
|
|
; SI-NEXT: ; implicit-def: $sgpr50
|
|
; SI-NEXT: ; implicit-def: $sgpr49
|
|
; SI-NEXT: ; implicit-def: $sgpr48
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr36
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: s_branch .LBB85_2
|
|
; SI-NEXT: .LBB85_4:
|
|
; SI-NEXT: v_mov_b32_e32 v32, s16
|
|
; SI-NEXT: v_mov_b32_e32 v28, s18
|
|
; SI-NEXT: v_mov_b32_e32 v20, s20
|
|
; SI-NEXT: v_mov_b32_e32 v13, s22
|
|
; SI-NEXT: v_mov_b32_e32 v7, s24
|
|
; SI-NEXT: v_mov_b32_e32 v5, s26
|
|
; SI-NEXT: v_mov_b32_e32 v3, s28
|
|
; SI-NEXT: v_mov_b32_e32 v1, s4
|
|
; SI-NEXT: v_mov_b32_e32 v53, s74
|
|
; SI-NEXT: v_mov_b32_e32 v52, s62
|
|
; SI-NEXT: v_mov_b32_e32 v51, s58
|
|
; SI-NEXT: v_mov_b32_e32 v50, s56
|
|
; SI-NEXT: v_mov_b32_e32 v49, s44
|
|
; SI-NEXT: v_mov_b32_e32 v48, s42
|
|
; SI-NEXT: v_mov_b32_e32 v38, s40
|
|
; SI-NEXT: v_mov_b32_e32 v37, s12
|
|
; SI-NEXT: v_mov_b32_e32 v36, s8
|
|
; SI-NEXT: v_mov_b32_e32 v35, s38
|
|
; SI-NEXT: v_mov_b32_e32 v34, s36
|
|
; SI-NEXT: v_mov_b32_e32 v30, s34
|
|
; SI-NEXT: v_mov_b32_e32 v26, s30
|
|
; SI-NEXT: v_mov_b32_e32 v25, s94
|
|
; SI-NEXT: v_mov_b32_e32 v24, s92
|
|
; SI-NEXT: v_mov_b32_e32 v23, s88
|
|
; SI-NEXT: v_mov_b32_e32 v22, s78
|
|
; SI-NEXT: v_mov_b32_e32 v18, s76
|
|
; SI-NEXT: v_mov_b32_e32 v17, s72
|
|
; SI-NEXT: v_mov_b32_e32 v16, s60
|
|
; SI-NEXT: v_mov_b32_e32 v15, s46
|
|
; SI-NEXT: v_mov_b32_e32 v11, s14
|
|
; SI-NEXT: v_mov_b32_e32 v10, s10
|
|
; SI-NEXT: v_mov_b32_e32 v9, s6
|
|
; SI-NEXT: .LBB85_5: ; %end
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v53
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s87, 8
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v52
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s86, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s85, 24
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
|
; SI-NEXT: v_mov_b32_e32 v4, s4
|
|
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v28
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v50
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s84, 8
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v49
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s83, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v48
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s82, 24
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 8, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
|
|
; SI-NEXT: v_mov_b32_e32 v4, s4
|
|
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v20
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v38
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s81, 8
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v37
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s80, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s71, 24
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 16, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
|
|
; SI-NEXT: v_mov_b32_e32 v4, s4
|
|
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v13
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v35
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s70, 8
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v34
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s69, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s68, 24
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 24, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
|
|
; SI-NEXT: v_mov_b32_e32 v4, s4
|
|
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v7
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v26
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s67, 8
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v25
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s66, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v24
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s65, 24
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 32, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
|
|
; SI-NEXT: v_mov_b32_e32 v4, s4
|
|
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v5
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v23
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s64, 8
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v22
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s55, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v18
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s54, 24
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 40, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
|
|
; SI-NEXT: v_mov_b32_e32 v4, s4
|
|
; SI-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v17
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s53, 8
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v16
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s52, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v15
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s51, 24
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
|
|
; SI-NEXT: v_mov_b32_e32 v3, s4
|
|
; SI-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v11
|
|
; SI-NEXT: s_and_b32 s4, s5, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s50, 8
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v10
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s49, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v9
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s48, 24
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v1, s4
|
|
; SI-NEXT: v_readlane_b32 s30, v40, 30
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: v_readlane_b32 s31, v40, 31
|
|
; SI-NEXT: v_readlane_b32 s87, v40, 29
|
|
; SI-NEXT: v_readlane_b32 s86, v40, 28
|
|
; SI-NEXT: v_readlane_b32 s85, v40, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v40, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v40, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v40, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v40, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v40, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v40, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v40, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v40, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v40, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v40, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v40, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v40, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v40, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v40, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v40, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v40, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v40, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v40, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v40, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v40, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v40, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v40, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v40, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v40, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v40, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v40, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v40, 0
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v8f64_to_v64i8_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_writelane_b32 v63, s34, 0
|
|
; VI-NEXT: v_writelane_b32 v63, s35, 1
|
|
; VI-NEXT: v_writelane_b32 v63, s36, 2
|
|
; VI-NEXT: v_writelane_b32 v63, s37, 3
|
|
; VI-NEXT: v_writelane_b32 v63, s38, 4
|
|
; VI-NEXT: v_writelane_b32 v63, s39, 5
|
|
; VI-NEXT: v_writelane_b32 v63, s48, 6
|
|
; VI-NEXT: v_writelane_b32 v63, s49, 7
|
|
; VI-NEXT: v_writelane_b32 v63, s50, 8
|
|
; VI-NEXT: v_writelane_b32 v63, s51, 9
|
|
; VI-NEXT: v_writelane_b32 v63, s52, 10
|
|
; VI-NEXT: v_writelane_b32 v63, s53, 11
|
|
; VI-NEXT: v_writelane_b32 v63, s54, 12
|
|
; VI-NEXT: v_writelane_b32 v63, s55, 13
|
|
; VI-NEXT: v_writelane_b32 v63, s64, 14
|
|
; VI-NEXT: v_writelane_b32 v63, s65, 15
|
|
; VI-NEXT: v_writelane_b32 v63, s66, 16
|
|
; VI-NEXT: v_writelane_b32 v63, s67, 17
|
|
; VI-NEXT: v_writelane_b32 v63, s30, 18
|
|
; VI-NEXT: v_writelane_b32 v63, s31, 19
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; VI-NEXT: s_cbranch_scc0 .LBB85_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_lshr_b32 s35, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s34, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s31, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s36, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s91, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s90, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s39, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s38, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s89, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s79, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s49, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s48, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s78, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s77, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s76, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s51, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s50, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s75, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s74, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s53, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s52, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s72, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s63, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s62, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s54, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s61, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s60, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s59, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s65, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s64, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s58, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s56, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s66, s16, 8
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; VI-NEXT: s_cbranch_execnz .LBB85_4
|
|
; VI-NEXT: .LBB85_2: ; %cmp.true
|
|
; VI-NEXT: v_add_f64 v[9:10], s[4:5], 1.0
|
|
; VI-NEXT: v_add_f64 v[1:2], s[28:29], 1.0
|
|
; VI-NEXT: v_add_f64 v[5:6], s[24:25], 1.0
|
|
; VI-NEXT: v_add_f64 v[7:8], s[22:23], 1.0
|
|
; VI-NEXT: v_add_f64 v[11:12], s[20:21], 1.0
|
|
; VI-NEXT: v_add_f64 v[3:4], s[26:27], 1.0
|
|
; VI-NEXT: v_add_f64 v[13:14], s[18:19], 1.0
|
|
; VI-NEXT: v_add_f64 v[15:16], s[16:17], 1.0
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v10
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v25, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v19, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v15
|
|
; VI-NEXT: s_branch .LBB85_5
|
|
; VI-NEXT: .LBB85_3:
|
|
; VI-NEXT: ; implicit-def: $sgpr66
|
|
; VI-NEXT: ; implicit-def: $sgpr67
|
|
; VI-NEXT: ; implicit-def: $sgpr6
|
|
; VI-NEXT: ; implicit-def: $sgpr56
|
|
; VI-NEXT: ; implicit-def: $sgpr57
|
|
; VI-NEXT: ; implicit-def: $sgpr58
|
|
; VI-NEXT: ; implicit-def: $sgpr64
|
|
; VI-NEXT: ; implicit-def: $sgpr65
|
|
; VI-NEXT: ; implicit-def: $sgpr8
|
|
; VI-NEXT: ; implicit-def: $sgpr59
|
|
; VI-NEXT: ; implicit-def: $sgpr60
|
|
; VI-NEXT: ; implicit-def: $sgpr61
|
|
; VI-NEXT: ; implicit-def: $sgpr54
|
|
; VI-NEXT: ; implicit-def: $sgpr55
|
|
; VI-NEXT: ; implicit-def: $sgpr10
|
|
; VI-NEXT: ; implicit-def: $sgpr62
|
|
; VI-NEXT: ; implicit-def: $sgpr63
|
|
; VI-NEXT: ; implicit-def: $sgpr72
|
|
; VI-NEXT: ; implicit-def: $sgpr52
|
|
; VI-NEXT: ; implicit-def: $sgpr53
|
|
; VI-NEXT: ; implicit-def: $sgpr12
|
|
; VI-NEXT: ; implicit-def: $sgpr73
|
|
; VI-NEXT: ; implicit-def: $sgpr74
|
|
; VI-NEXT: ; implicit-def: $sgpr75
|
|
; VI-NEXT: ; implicit-def: $sgpr50
|
|
; VI-NEXT: ; implicit-def: $sgpr51
|
|
; VI-NEXT: ; implicit-def: $sgpr14
|
|
; VI-NEXT: ; implicit-def: $sgpr76
|
|
; VI-NEXT: ; implicit-def: $sgpr77
|
|
; VI-NEXT: ; implicit-def: $sgpr78
|
|
; VI-NEXT: ; implicit-def: $sgpr48
|
|
; VI-NEXT: ; implicit-def: $sgpr49
|
|
; VI-NEXT: ; implicit-def: $sgpr40
|
|
; VI-NEXT: ; implicit-def: $sgpr79
|
|
; VI-NEXT: ; implicit-def: $sgpr88
|
|
; VI-NEXT: ; implicit-def: $sgpr89
|
|
; VI-NEXT: ; implicit-def: $sgpr38
|
|
; VI-NEXT: ; implicit-def: $sgpr39
|
|
; VI-NEXT: ; implicit-def: $sgpr42
|
|
; VI-NEXT: ; implicit-def: $sgpr90
|
|
; VI-NEXT: ; implicit-def: $sgpr91
|
|
; VI-NEXT: ; implicit-def: $sgpr30
|
|
; VI-NEXT: ; implicit-def: $sgpr36
|
|
; VI-NEXT: ; implicit-def: $sgpr37
|
|
; VI-NEXT: ; implicit-def: $sgpr44
|
|
; VI-NEXT: ; implicit-def: $sgpr31
|
|
; VI-NEXT: ; implicit-def: $sgpr34
|
|
; VI-NEXT: ; implicit-def: $sgpr35
|
|
; VI-NEXT: s_branch .LBB85_2
|
|
; VI-NEXT: .LBB85_4:
|
|
; VI-NEXT: v_mov_b32_e32 v26, s35
|
|
; VI-NEXT: v_mov_b32_e32 v25, s40
|
|
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v25, s42
|
|
; VI-NEXT: v_mov_b32_e32 v15, s16
|
|
; VI-NEXT: v_mov_b32_e32 v13, s18
|
|
; VI-NEXT: v_mov_b32_e32 v11, s20
|
|
; VI-NEXT: v_mov_b32_e32 v7, s22
|
|
; VI-NEXT: v_mov_b32_e32 v5, s24
|
|
; VI-NEXT: v_mov_b32_e32 v3, s26
|
|
; VI-NEXT: v_mov_b32_e32 v1, s28
|
|
; VI-NEXT: v_mov_b32_e32 v9, s4
|
|
; VI-NEXT: v_mov_b32_e32 v10, s5
|
|
; VI-NEXT: v_mov_b32_e32 v2, s29
|
|
; VI-NEXT: v_mov_b32_e32 v4, s27
|
|
; VI-NEXT: v_mov_b32_e32 v6, s25
|
|
; VI-NEXT: v_mov_b32_e32 v8, s23
|
|
; VI-NEXT: v_mov_b32_e32 v12, s21
|
|
; VI-NEXT: v_mov_b32_e32 v14, s19
|
|
; VI-NEXT: v_mov_b32_e32 v16, s17
|
|
; VI-NEXT: v_mov_b32_e32 v57, s67
|
|
; VI-NEXT: v_mov_b32_e32 v58, s66
|
|
; VI-NEXT: v_mov_b32_e32 v44, s65
|
|
; VI-NEXT: v_mov_b32_e32 v45, s64
|
|
; VI-NEXT: v_mov_b32_e32 v55, s55
|
|
; VI-NEXT: v_mov_b32_e32 v40, s54
|
|
; VI-NEXT: v_mov_b32_e32 v50, s53
|
|
; VI-NEXT: v_mov_b32_e32 v52, s52
|
|
; VI-NEXT: v_mov_b32_e32 v39, s51
|
|
; VI-NEXT: v_mov_b32_e32 v49, s50
|
|
; VI-NEXT: v_mov_b32_e32 v35, s49
|
|
; VI-NEXT: v_mov_b32_e32 v36, s48
|
|
; VI-NEXT: v_mov_b32_e32 v30, s39
|
|
; VI-NEXT: v_mov_b32_e32 v31, s38
|
|
; VI-NEXT: v_mov_b32_e32 v19, s37
|
|
; VI-NEXT: v_mov_b32_e32 v28, s36
|
|
; VI-NEXT: v_mov_b32_e32 v27, s34
|
|
; VI-NEXT: v_mov_b32_e32 v29, s31
|
|
; VI-NEXT: v_mov_b32_e32 v32, s30
|
|
; VI-NEXT: v_mov_b32_e32 v33, s91
|
|
; VI-NEXT: v_mov_b32_e32 v34, s90
|
|
; VI-NEXT: v_mov_b32_e32 v37, s89
|
|
; VI-NEXT: v_mov_b32_e32 v38, s88
|
|
; VI-NEXT: v_mov_b32_e32 v48, s79
|
|
; VI-NEXT: v_mov_b32_e32 v51, s78
|
|
; VI-NEXT: v_mov_b32_e32 v53, s77
|
|
; VI-NEXT: v_mov_b32_e32 v54, s76
|
|
; VI-NEXT: v_mov_b32_e32 v41, s75
|
|
; VI-NEXT: v_mov_b32_e32 v42, s74
|
|
; VI-NEXT: v_mov_b32_e32 v43, s73
|
|
; VI-NEXT: v_mov_b32_e32 v46, s72
|
|
; VI-NEXT: v_mov_b32_e32 v47, s63
|
|
; VI-NEXT: v_mov_b32_e32 v56, s62
|
|
; VI-NEXT: v_mov_b32_e32 v59, s61
|
|
; VI-NEXT: v_mov_b32_e32 v60, s60
|
|
; VI-NEXT: v_mov_b32_e32 v61, s59
|
|
; VI-NEXT: v_mov_b32_e32 v62, s58
|
|
; VI-NEXT: v_mov_b32_e32 v17, s57
|
|
; VI-NEXT: v_mov_b32_e32 v18, s56
|
|
; VI-NEXT: v_mov_b32_e32 v24, s6
|
|
; VI-NEXT: v_mov_b32_e32 v23, s8
|
|
; VI-NEXT: v_mov_b32_e32 v22, s10
|
|
; VI-NEXT: v_mov_b32_e32 v21, s12
|
|
; VI-NEXT: v_mov_b32_e32 v20, s14
|
|
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v25, s44
|
|
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v25, s35
|
|
; VI-NEXT: .LBB85_5: ; %end
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v24, v57, v24, s4
|
|
; VI-NEXT: v_perm_b32 v15, v15, v58, s4
|
|
; VI-NEXT: v_perm_b32 v16, v16, v18, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v18
|
|
; VI-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v15, v17, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v15, v44, v23, s4
|
|
; VI-NEXT: v_perm_b32 v13, v13, v45, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v15
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v13, v14, v61, s4
|
|
; VI-NEXT: v_perm_b32 v14, v60, v59, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v13, v55, v22, s4
|
|
; VI-NEXT: v_perm_b32 v11, v11, v40, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v13
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v11, v12, v56, s4
|
|
; VI-NEXT: v_perm_b32 v12, v47, v46, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v11, v50, v21, s4
|
|
; VI-NEXT: v_perm_b32 v7, v7, v52, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v11
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v7, v11, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v7, v8, v43, s4
|
|
; VI-NEXT: v_perm_b32 v8, v42, v41, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v7, v39, v20, s4
|
|
; VI-NEXT: v_perm_b32 v5, v5, v49, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v5, v6, v54, s4
|
|
; VI-NEXT: v_perm_b32 v6, v53, v51, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v3, v3, v36, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; VI-NEXT: v_readlane_b32 s30, v63, 18
|
|
; VI-NEXT: v_readlane_b32 s31, v63, 19
|
|
; VI-NEXT: v_readlane_b32 s67, v63, 17
|
|
; VI-NEXT: v_readlane_b32 s66, v63, 16
|
|
; VI-NEXT: v_readlane_b32 s65, v63, 15
|
|
; VI-NEXT: v_readlane_b32 s64, v63, 14
|
|
; VI-NEXT: v_readlane_b32 s55, v63, 13
|
|
; VI-NEXT: v_readlane_b32 s54, v63, 12
|
|
; VI-NEXT: v_readlane_b32 s53, v63, 11
|
|
; VI-NEXT: v_readlane_b32 s52, v63, 10
|
|
; VI-NEXT: v_readlane_b32 s51, v63, 9
|
|
; VI-NEXT: v_readlane_b32 s50, v63, 8
|
|
; VI-NEXT: v_readlane_b32 s49, v63, 7
|
|
; VI-NEXT: v_readlane_b32 s48, v63, 6
|
|
; VI-NEXT: v_readlane_b32 s39, v63, 5
|
|
; VI-NEXT: v_readlane_b32 s38, v63, 4
|
|
; VI-NEXT: v_readlane_b32 s37, v63, 3
|
|
; VI-NEXT: v_readlane_b32 s36, v63, 2
|
|
; VI-NEXT: v_readlane_b32 s35, v63, 1
|
|
; VI-NEXT: v_readlane_b32 s34, v63, 0
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v5, v35, v5, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v3, v4, v48, s4
|
|
; VI-NEXT: v_perm_b32 v4, v38, v37, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v3, v30, v3, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v2, v34, s4
|
|
; VI-NEXT: v_perm_b32 v2, v33, v32, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v1, v9, v28, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v27, v25, s4
|
|
; VI-NEXT: v_perm_b32 v1, v10, v29, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v8f64_to_v64i8_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
|
|
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
|
|
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
|
|
; GFX9-NEXT: v_writelane_b32 v63, s37, 3
|
|
; GFX9-NEXT: v_writelane_b32 v63, s38, 4
|
|
; GFX9-NEXT: v_writelane_b32 v63, s39, 5
|
|
; GFX9-NEXT: v_writelane_b32 v63, s48, 6
|
|
; GFX9-NEXT: v_writelane_b32 v63, s49, 7
|
|
; GFX9-NEXT: v_writelane_b32 v63, s50, 8
|
|
; GFX9-NEXT: v_writelane_b32 v63, s51, 9
|
|
; GFX9-NEXT: v_writelane_b32 v63, s52, 10
|
|
; GFX9-NEXT: v_writelane_b32 v63, s53, 11
|
|
; GFX9-NEXT: v_writelane_b32 v63, s54, 12
|
|
; GFX9-NEXT: v_writelane_b32 v63, s55, 13
|
|
; GFX9-NEXT: v_writelane_b32 v63, s30, 14
|
|
; GFX9-NEXT: v_writelane_b32 v63, s31, 15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB85_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_lshr_b32 s95, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s94, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s93, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s30, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s92, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s91, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s90, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s35, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s34, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s89, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s88, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s79, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s37, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s36, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s78, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s77, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s76, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s39, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s38, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s75, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s74, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s49, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s48, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s72, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s63, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s62, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s50, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s61, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s60, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s59, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s53, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s52, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s58, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s57, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s56, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s55, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s54, s16, 8
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB85_4
|
|
; GFX9-NEXT: .LBB85_2: ; %cmp.true
|
|
; GFX9-NEXT: v_add_f64 v[11:12], s[4:5], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[1:2], s[28:29], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[5:6], s[24:25], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[7:8], s[22:23], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[9:10], s[20:21], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[3:4], s[26:27], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[13:14], s[18:19], 1.0
|
|
; GFX9-NEXT: v_add_f64 v[15:16], s[16:17], 1.0
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 24, v12
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 24, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 8, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 8, v15
|
|
; GFX9-NEXT: s_branch .LBB85_5
|
|
; GFX9-NEXT: .LBB85_3:
|
|
; GFX9-NEXT: ; implicit-def: $sgpr54
|
|
; GFX9-NEXT: ; implicit-def: $sgpr55
|
|
; GFX9-NEXT: ; implicit-def: $sgpr6
|
|
; GFX9-NEXT: ; implicit-def: $sgpr56
|
|
; GFX9-NEXT: ; implicit-def: $sgpr57
|
|
; GFX9-NEXT: ; implicit-def: $sgpr58
|
|
; GFX9-NEXT: ; implicit-def: $sgpr52
|
|
; GFX9-NEXT: ; implicit-def: $sgpr53
|
|
; GFX9-NEXT: ; implicit-def: $sgpr8
|
|
; GFX9-NEXT: ; implicit-def: $sgpr59
|
|
; GFX9-NEXT: ; implicit-def: $sgpr60
|
|
; GFX9-NEXT: ; implicit-def: $sgpr61
|
|
; GFX9-NEXT: ; implicit-def: $sgpr50
|
|
; GFX9-NEXT: ; implicit-def: $sgpr51
|
|
; GFX9-NEXT: ; implicit-def: $sgpr10
|
|
; GFX9-NEXT: ; implicit-def: $sgpr62
|
|
; GFX9-NEXT: ; implicit-def: $sgpr63
|
|
; GFX9-NEXT: ; implicit-def: $sgpr72
|
|
; GFX9-NEXT: ; implicit-def: $sgpr48
|
|
; GFX9-NEXT: ; implicit-def: $sgpr49
|
|
; GFX9-NEXT: ; implicit-def: $sgpr12
|
|
; GFX9-NEXT: ; implicit-def: $sgpr73
|
|
; GFX9-NEXT: ; implicit-def: $sgpr74
|
|
; GFX9-NEXT: ; implicit-def: $sgpr75
|
|
; GFX9-NEXT: ; implicit-def: $sgpr38
|
|
; GFX9-NEXT: ; implicit-def: $sgpr39
|
|
; GFX9-NEXT: ; implicit-def: $sgpr14
|
|
; GFX9-NEXT: ; implicit-def: $sgpr76
|
|
; GFX9-NEXT: ; implicit-def: $sgpr77
|
|
; GFX9-NEXT: ; implicit-def: $sgpr78
|
|
; GFX9-NEXT: ; implicit-def: $sgpr36
|
|
; GFX9-NEXT: ; implicit-def: $sgpr37
|
|
; GFX9-NEXT: ; implicit-def: $sgpr40
|
|
; GFX9-NEXT: ; implicit-def: $sgpr79
|
|
; GFX9-NEXT: ; implicit-def: $sgpr88
|
|
; GFX9-NEXT: ; implicit-def: $sgpr89
|
|
; GFX9-NEXT: ; implicit-def: $sgpr34
|
|
; GFX9-NEXT: ; implicit-def: $sgpr35
|
|
; GFX9-NEXT: ; implicit-def: $sgpr42
|
|
; GFX9-NEXT: ; implicit-def: $sgpr90
|
|
; GFX9-NEXT: ; implicit-def: $sgpr91
|
|
; GFX9-NEXT: ; implicit-def: $sgpr92
|
|
; GFX9-NEXT: ; implicit-def: $sgpr30
|
|
; GFX9-NEXT: ; implicit-def: $sgpr31
|
|
; GFX9-NEXT: ; implicit-def: $sgpr44
|
|
; GFX9-NEXT: ; implicit-def: $sgpr93
|
|
; GFX9-NEXT: ; implicit-def: $sgpr94
|
|
; GFX9-NEXT: ; implicit-def: $sgpr95
|
|
; GFX9-NEXT: s_branch .LBB85_2
|
|
; GFX9-NEXT: .LBB85_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v26, s31
|
|
; GFX9-NEXT: v_mov_b32_e32 v25, s40
|
|
; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v25, s42
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s5
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v57, s55
|
|
; GFX9-NEXT: v_mov_b32_e32 v59, s54
|
|
; GFX9-NEXT: v_mov_b32_e32 v56, s53
|
|
; GFX9-NEXT: v_mov_b32_e32 v47, s52
|
|
; GFX9-NEXT: v_mov_b32_e32 v42, s51
|
|
; GFX9-NEXT: v_mov_b32_e32 v43, s50
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, s49
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, s48
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, s39
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, s38
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, s37
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, s36
|
|
; GFX9-NEXT: v_mov_b32_e32 v30, s35
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, s34
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, s95
|
|
; GFX9-NEXT: v_mov_b32_e32 v28, s94
|
|
; GFX9-NEXT: v_mov_b32_e32 v29, s93
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, s92
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, s91
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, s90
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, s89
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, s88
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, s79
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, s78
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, s77
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, s76
|
|
; GFX9-NEXT: v_mov_b32_e32 v55, s75
|
|
; GFX9-NEXT: v_mov_b32_e32 v40, s74
|
|
; GFX9-NEXT: v_mov_b32_e32 v41, s73
|
|
; GFX9-NEXT: v_mov_b32_e32 v44, s72
|
|
; GFX9-NEXT: v_mov_b32_e32 v45, s63
|
|
; GFX9-NEXT: v_mov_b32_e32 v46, s62
|
|
; GFX9-NEXT: v_mov_b32_e32 v58, s61
|
|
; GFX9-NEXT: v_mov_b32_e32 v60, s60
|
|
; GFX9-NEXT: v_mov_b32_e32 v61, s59
|
|
; GFX9-NEXT: v_mov_b32_e32 v62, s58
|
|
; GFX9-NEXT: v_mov_b32_e32 v17, s57
|
|
; GFX9-NEXT: v_mov_b32_e32 v18, s56
|
|
; GFX9-NEXT: v_mov_b32_e32 v24, s6
|
|
; GFX9-NEXT: v_mov_b32_e32 v23, s8
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s10
|
|
; GFX9-NEXT: v_mov_b32_e32 v21, s12
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s14
|
|
; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v25, s44
|
|
; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: .LBB85_5: ; %end
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v24, v57, v24, s4
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v59, s4
|
|
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
|
|
; GFX9-NEXT: v_perm_b32 v18, v56, v23, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v24
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v15, v23
|
|
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v15, v17, v62, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v47, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
|
|
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v13, v14, v61, s4
|
|
; GFX9-NEXT: v_perm_b32 v14, v60, v58, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v13, v42, v22, s4
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v43, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v13
|
|
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v9, v10, v46, s4
|
|
; GFX9-NEXT: v_perm_b32 v10, v45, v44, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v9, v50, v21, s4
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v51, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
|
|
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v41, s4
|
|
; GFX9-NEXT: v_perm_b32 v8, v40, v55, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v48, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v5, v6, v54, s4
|
|
; GFX9-NEXT: v_perm_b32 v6, v53, v52, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v36, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; GFX9-NEXT: v_readlane_b32 s30, v63, 14
|
|
; GFX9-NEXT: v_readlane_b32 s31, v63, 15
|
|
; GFX9-NEXT: v_readlane_b32 s55, v63, 13
|
|
; GFX9-NEXT: v_readlane_b32 s54, v63, 12
|
|
; GFX9-NEXT: v_readlane_b32 s53, v63, 11
|
|
; GFX9-NEXT: v_readlane_b32 s52, v63, 10
|
|
; GFX9-NEXT: v_readlane_b32 s51, v63, 9
|
|
; GFX9-NEXT: v_readlane_b32 s50, v63, 8
|
|
; GFX9-NEXT: v_readlane_b32 s49, v63, 7
|
|
; GFX9-NEXT: v_readlane_b32 s48, v63, 6
|
|
; GFX9-NEXT: v_readlane_b32 s39, v63, 5
|
|
; GFX9-NEXT: v_readlane_b32 s38, v63, 4
|
|
; GFX9-NEXT: v_readlane_b32 s37, v63, 3
|
|
; GFX9-NEXT: v_readlane_b32 s36, v63, 2
|
|
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
|
|
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v5, v35, v5, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v49, s4
|
|
; GFX9-NEXT: v_perm_b32 v4, v39, v37, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v3, v30, v3, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v1, v2, v34, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v33, v32, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v11, v27, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v2, v26, v2, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: v_perm_b32 v2, v28, v19, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: v_perm_b32 v1, v12, v29, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v8f64_to_v64i8_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_or_saveexec_b32 s4, -1
|
|
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s4
|
|
; GFX11-NEXT: v_writelane_b32 v40, s34, 0
|
|
; GFX11-NEXT: v_writelane_b32 v40, s35, 1
|
|
; GFX11-NEXT: v_writelane_b32 v40, s36, 2
|
|
; GFX11-NEXT: v_writelane_b32 v40, s37, 3
|
|
; GFX11-NEXT: v_writelane_b32 v40, s38, 4
|
|
; GFX11-NEXT: v_writelane_b32 v40, s39, 5
|
|
; GFX11-NEXT: v_writelane_b32 v40, s48, 6
|
|
; GFX11-NEXT: v_writelane_b32 v40, s49, 7
|
|
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
|
|
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s42, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB85_3
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-NEXT: s_lshr_b32 s90, s27, 24
|
|
; GFX11-NEXT: s_lshr_b32 s89, s27, 16
|
|
; GFX11-NEXT: s_lshr_b32 s88, s27, 8
|
|
; GFX11-NEXT: s_lshr_b32 s92, s26, 16
|
|
; GFX11-NEXT: s_lshr_b32 s91, s26, 8
|
|
; GFX11-NEXT: s_lshr_b32 s79, s25, 24
|
|
; GFX11-NEXT: s_lshr_b32 s78, s25, 16
|
|
; GFX11-NEXT: s_lshr_b32 s77, s25, 8
|
|
; GFX11-NEXT: s_lshr_b32 s94, s24, 16
|
|
; GFX11-NEXT: s_lshr_b32 s93, s24, 8
|
|
; GFX11-NEXT: s_lshr_b32 s76, s23, 24
|
|
; GFX11-NEXT: s_lshr_b32 s75, s23, 16
|
|
; GFX11-NEXT: s_lshr_b32 s74, s23, 8
|
|
; GFX11-NEXT: s_lshr_b32 vcc_hi, s22, 16
|
|
; GFX11-NEXT: s_lshr_b32 s95, s22, 8
|
|
; GFX11-NEXT: s_lshr_b32 s73, s21, 24
|
|
; GFX11-NEXT: s_lshr_b32 s72, s21, 16
|
|
; GFX11-NEXT: s_lshr_b32 s63, s21, 8
|
|
; GFX11-NEXT: s_lshr_b32 s31, s20, 16
|
|
; GFX11-NEXT: s_lshr_b32 s30, s20, 8
|
|
; GFX11-NEXT: s_lshr_b32 s62, s19, 24
|
|
; GFX11-NEXT: s_lshr_b32 s61, s19, 16
|
|
; GFX11-NEXT: s_lshr_b32 s60, s19, 8
|
|
; GFX11-NEXT: s_lshr_b32 s35, s18, 16
|
|
; GFX11-NEXT: s_lshr_b32 s34, s18, 8
|
|
; GFX11-NEXT: s_lshr_b32 s59, s17, 24
|
|
; GFX11-NEXT: s_lshr_b32 s58, s17, 16
|
|
; GFX11-NEXT: s_lshr_b32 s57, s17, 8
|
|
; GFX11-NEXT: s_lshr_b32 s37, s16, 16
|
|
; GFX11-NEXT: s_lshr_b32 s36, s16, 8
|
|
; GFX11-NEXT: s_lshr_b32 s56, s3, 24
|
|
; GFX11-NEXT: s_lshr_b32 s47, s3, 16
|
|
; GFX11-NEXT: s_lshr_b32 s46, s3, 8
|
|
; GFX11-NEXT: s_lshr_b32 s39, s2, 16
|
|
; GFX11-NEXT: s_lshr_b32 s38, s2, 8
|
|
; GFX11-NEXT: s_lshr_b32 s45, s1, 24
|
|
; GFX11-NEXT: s_lshr_b32 s44, s1, 16
|
|
; GFX11-NEXT: s_lshr_b32 s43, s1, 8
|
|
; GFX11-NEXT: s_lshr_b32 s49, s0, 16
|
|
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
|
|
; GFX11-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[28:29], s[24:25], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[12:13], s[20:21], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[10:11], s[18:19], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[8:9], s[16:17], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[6:7], s[2:3], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[4:5], s[0:1], 24
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB85_4
|
|
; GFX11-NEXT: .LBB85_2: ; %cmp.true
|
|
; GFX11-NEXT: v_add_f64 v[7:8], s[20:21], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[11:12], s[18:19], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[15:16], s[16:17], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[17:18], s[2:3], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[1:2], s[26:27], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[3:4], s[24:25], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[5:6], s[22:23], 1.0
|
|
; GFX11-NEXT: v_add_f64 v[21:22], s[0:1], 1.0
|
|
; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[11:12]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[15:16]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[26:27], 24, v[17:18]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[9:10], 24, v[1:2]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[13:14], 24, v[3:4]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[21:22]
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 16, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v10, 8, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v33, 24, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 24, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 8, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v5
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v5
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v50, 8, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v7
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v7
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v65, 24, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v67, 16, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v66, 8, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v71, 24, v16
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v16
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v70, 8, v16
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v15
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v15
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v84, 24, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v17
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v68, 8, v17
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v87, 24, v22
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v22
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v22
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v21
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v21
|
|
; GFX11-NEXT: s_branch .LBB85_5
|
|
; GFX11-NEXT: .LBB85_3:
|
|
; GFX11-NEXT: ; implicit-def: $sgpr48
|
|
; GFX11-NEXT: ; implicit-def: $sgpr49
|
|
; GFX11-NEXT: ; implicit-def: $sgpr4
|
|
; GFX11-NEXT: ; implicit-def: $sgpr43
|
|
; GFX11-NEXT: ; implicit-def: $sgpr44
|
|
; GFX11-NEXT: ; implicit-def: $sgpr45
|
|
; GFX11-NEXT: ; implicit-def: $sgpr38
|
|
; GFX11-NEXT: ; implicit-def: $sgpr39
|
|
; GFX11-NEXT: ; implicit-def: $sgpr6
|
|
; GFX11-NEXT: ; implicit-def: $sgpr46
|
|
; GFX11-NEXT: ; implicit-def: $sgpr47
|
|
; GFX11-NEXT: ; implicit-def: $sgpr56
|
|
; GFX11-NEXT: ; implicit-def: $sgpr36
|
|
; GFX11-NEXT: ; implicit-def: $sgpr37
|
|
; GFX11-NEXT: ; implicit-def: $sgpr8
|
|
; GFX11-NEXT: ; implicit-def: $sgpr57
|
|
; GFX11-NEXT: ; implicit-def: $sgpr58
|
|
; GFX11-NEXT: ; implicit-def: $sgpr59
|
|
; GFX11-NEXT: ; implicit-def: $sgpr34
|
|
; GFX11-NEXT: ; implicit-def: $sgpr35
|
|
; GFX11-NEXT: ; implicit-def: $sgpr10
|
|
; GFX11-NEXT: ; implicit-def: $sgpr60
|
|
; GFX11-NEXT: ; implicit-def: $sgpr61
|
|
; GFX11-NEXT: ; implicit-def: $sgpr62
|
|
; GFX11-NEXT: ; implicit-def: $sgpr30
|
|
; GFX11-NEXT: ; implicit-def: $sgpr31
|
|
; GFX11-NEXT: ; implicit-def: $sgpr12
|
|
; GFX11-NEXT: ; implicit-def: $sgpr63
|
|
; GFX11-NEXT: ; implicit-def: $sgpr72
|
|
; GFX11-NEXT: ; implicit-def: $sgpr73
|
|
; GFX11-NEXT: ; implicit-def: $sgpr95
|
|
; GFX11-NEXT: ; implicit-def: $vcc_hi
|
|
; GFX11-NEXT: ; implicit-def: $sgpr14
|
|
; GFX11-NEXT: ; implicit-def: $sgpr74
|
|
; GFX11-NEXT: ; implicit-def: $sgpr75
|
|
; GFX11-NEXT: ; implicit-def: $sgpr76
|
|
; GFX11-NEXT: ; implicit-def: $sgpr93
|
|
; GFX11-NEXT: ; implicit-def: $sgpr94
|
|
; GFX11-NEXT: ; implicit-def: $sgpr28
|
|
; GFX11-NEXT: ; implicit-def: $sgpr77
|
|
; GFX11-NEXT: ; implicit-def: $sgpr78
|
|
; GFX11-NEXT: ; implicit-def: $sgpr79
|
|
; GFX11-NEXT: ; implicit-def: $sgpr91
|
|
; GFX11-NEXT: ; implicit-def: $sgpr92
|
|
; GFX11-NEXT: ; implicit-def: $sgpr40
|
|
; GFX11-NEXT: ; implicit-def: $sgpr88
|
|
; GFX11-NEXT: ; implicit-def: $sgpr89
|
|
; GFX11-NEXT: ; implicit-def: $sgpr90
|
|
; GFX11-NEXT: s_branch .LBB85_2
|
|
; GFX11-NEXT: .LBB85_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v21, s0 :: v_dual_mov_b32 v2, s27
|
|
; GFX11-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v4, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v15, s16 :: v_dual_mov_b32 v6, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v11, s18 :: v_dual_mov_b32 v8, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v12, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v16, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v18, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v22, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v82, s49 :: v_dual_mov_b32 v81, s48
|
|
; GFX11-NEXT: v_dual_mov_b32 v69, s39 :: v_dual_mov_b32 v68, s38
|
|
; GFX11-NEXT: v_dual_mov_b32 v64, s37 :: v_dual_mov_b32 v55, s36
|
|
; GFX11-NEXT: v_dual_mov_b32 v54, s35 :: v_dual_mov_b32 v53, s34
|
|
; GFX11-NEXT: v_dual_mov_b32 v49, s31 :: v_dual_mov_b32 v30, s93
|
|
; GFX11-NEXT: v_dual_mov_b32 v39, s30 :: v_dual_mov_b32 v14, s92
|
|
; GFX11-NEXT: v_dual_mov_b32 v37, vcc_hi :: v_dual_mov_b32 v10, s91
|
|
; GFX11-NEXT: v_dual_mov_b32 v35, s95 :: v_dual_mov_b32 v26, s6
|
|
; GFX11-NEXT: v_dual_mov_b32 v31, s94 :: v_dual_mov_b32 v24, s10
|
|
; GFX11-NEXT: v_dual_mov_b32 v27, s4 :: v_dual_mov_b32 v28, s90
|
|
; GFX11-NEXT: v_dual_mov_b32 v25, s8 :: v_dual_mov_b32 v20, s88
|
|
; GFX11-NEXT: v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v34, s78
|
|
; GFX11-NEXT: v_dual_mov_b32 v19, s14 :: v_dual_mov_b32 v32, s77
|
|
; GFX11-NEXT: v_dual_mov_b32 v13, s28 :: v_dual_mov_b32 v38, s76
|
|
; GFX11-NEXT: v_dual_mov_b32 v9, s40 :: v_dual_mov_b32 v48, s75
|
|
; GFX11-NEXT: v_dual_mov_b32 v29, s89 :: v_dual_mov_b32 v36, s74
|
|
; GFX11-NEXT: v_dual_mov_b32 v33, s79 :: v_dual_mov_b32 v52, s72
|
|
; GFX11-NEXT: v_dual_mov_b32 v51, s73 :: v_dual_mov_b32 v50, s63
|
|
; GFX11-NEXT: v_dual_mov_b32 v65, s62 :: v_dual_mov_b32 v66, s60
|
|
; GFX11-NEXT: v_dual_mov_b32 v67, s61 :: v_dual_mov_b32 v80, s58
|
|
; GFX11-NEXT: v_dual_mov_b32 v71, s59 :: v_dual_mov_b32 v70, s57
|
|
; GFX11-NEXT: v_dual_mov_b32 v84, s56 :: v_dual_mov_b32 v85, s47
|
|
; GFX11-NEXT: v_dual_mov_b32 v83, s46 :: v_dual_mov_b32 v96, s44
|
|
; GFX11-NEXT: v_dual_mov_b32 v87, s45 :: v_dual_mov_b32 v86, s43
|
|
; GFX11-NEXT: .LBB85_5: ; %end
|
|
; GFX11-NEXT: v_perm_b32 v26, v69, v26, 0xc0c0004
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-NEXT: v_perm_b32 v27, v82, v27, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v82, v96, v87, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v17, v17, v68, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v21, v21, v81, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v26
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; GFX11-NEXT: v_perm_b32 v68, v85, v84, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v24, v54, v24, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v22, v22, v86, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v82
|
|
; GFX11-NEXT: v_or_b32_e32 v86, v17, v26
|
|
; GFX11-NEXT: v_perm_b32 v17, v18, v83, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v64, v25, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v84, v21, v27
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v68
|
|
; GFX11-NEXT: v_perm_b32 v11, v11, v53, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; GFX11-NEXT: v_or_b32_e32 v85, v22, v69
|
|
; GFX11-NEXT: v_perm_b32 v22, v80, v71, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v15, v15, v55, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v87, v17, v21
|
|
; GFX11-NEXT: v_or_b32_e32 v17, v11, v24
|
|
; GFX11-NEXT: v_perm_b32 v11, v12, v66, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v12, v49, v23, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v16, v16, v70, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
|
|
; GFX11-NEXT: v_perm_b32 v18, v67, v65, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v21, v52, v51, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v19, v37, v19, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v7, v7, v39, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-NEXT: v_or_b32_e32 v16, v16, v22
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_perm_b32 v8, v8, v50, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v21
|
|
; GFX11-NEXT: v_perm_b32 v5, v5, v35, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; GFX11-NEXT: v_or_b32_e32 v21, v7, v12
|
|
; GFX11-NEXT: v_perm_b32 v7, v48, v38, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v18, v11, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v22, v8, v22
|
|
; GFX11-NEXT: v_or_b32_e32 v23, v5, v19
|
|
; GFX11-NEXT: v_perm_b32 v5, v31, v13, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v8, v34, v33, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v9, v14, v9, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v11, v29, v28, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v6, v6, v36, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-NEXT: v_perm_b32 v3, v3, v30, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-NEXT: v_perm_b32 v4, v4, v32, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-NEXT: v_perm_b32 v10, v1, v10, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-NEXT: v_perm_b32 v12, v2, v20, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-NEXT: v_or_b32_e32 v24, v6, v7
|
|
; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
|
|
; GFX11-NEXT: v_or_b32_e32 v2, v4, v8
|
|
; GFX11-NEXT: v_or_b32_e32 v3, v10, v9
|
|
; GFX11-NEXT: v_or_b32_e32 v4, v12, v11
|
|
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
|
|
; GFX11-NEXT: s_clause 0x3
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[84:87], off
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[15:18], off offset:16
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[21:24], off offset:32
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
|
|
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
|
|
; GFX11-NEXT: v_readlane_b32 s49, v40, 7
|
|
; GFX11-NEXT: v_readlane_b32 s48, v40, 6
|
|
; GFX11-NEXT: v_readlane_b32 s39, v40, 5
|
|
; GFX11-NEXT: v_readlane_b32 s38, v40, 4
|
|
; GFX11-NEXT: v_readlane_b32 s37, v40, 3
|
|
; GFX11-NEXT: v_readlane_b32 s36, v40, 2
|
|
; GFX11-NEXT: v_readlane_b32 s35, v40, 1
|
|
; GFX11-NEXT: v_readlane_b32 s34, v40, 0
|
|
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
|
|
; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s0
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <8 x double> %a, splat (double 1.000000e+00)
|
|
%a2 = bitcast <8 x double> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <8 x double> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v8f64:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v34, v6
|
|
; SI-NEXT: v_mov_b32_e32 v33, v4
|
|
; SI-NEXT: v_mov_b32_e32 v32, v2
|
|
; SI-NEXT: v_mov_b32_e32 v31, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:80
|
|
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:88
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:96
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:104
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:112
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:120
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:128
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 8, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 24, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 24, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 8, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 8, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 24, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 8, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 24, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v17
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v63, 8, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 24, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 8, v8
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 24, v10
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 8, v12
|
|
; SI-NEXT: s_waitcnt vmcnt(10)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v43, 24, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v41, 8, v50
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v51
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v52
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v53
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v55
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v40
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 8, v42
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v44
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:116
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 24, v58
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v47
|
|
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:108
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:100
|
|
; SI-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:124
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB86_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v31
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v33
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v34
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v49
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v1, v48, v1
|
|
; SI-NEXT: v_or_b32_e32 v3, v35, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v57
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v62, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v56, v10
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v52
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v43, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v54, v12
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v44
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v21, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v53
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v27, v14
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v37, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v20, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v24, v6
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v28, v7
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v38
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v17, v8
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v18
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v30
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v60
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v63
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v45
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v59
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v55
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v46
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v61
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v41
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v47
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v51
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v40
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v19
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v23
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v25
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v50, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; kill: killed $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: .LBB86_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB86_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v31
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v32
|
|
; SI-NEXT: v_or_b32_e32 v0, v49, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v48, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v33
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v34
|
|
; SI-NEXT: v_or_b32_e32 v1, v39, v1
|
|
; SI-NEXT: s_movk_i32 s6, 0x300
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v35, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v57
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v62, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v42
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v56, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v52
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v43, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v58
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v54, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v44
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v21, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v53
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v27, v14
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v29
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: s_mov_b32 s7, 0x3000000
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v36, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v37, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v20, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v24, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v28, v7
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v38, v3
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v17, v8
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v18, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v22, v5
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v26, v6
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v30, v7
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v60
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v63, v8
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v45
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v59, v9
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v55
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v46, v10
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v61
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v41, v11
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v47
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v51, v12
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v40
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v19, v13
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v23
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v25, v14
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x300, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v50, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v15
|
|
; SI-NEXT: .LBB86_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v8f64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v53, v1
|
|
; VI-NEXT: v_mov_b32_e32 v54, v0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:128
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:88
|
|
; VI-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; VI-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:80
|
|
; VI-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: v_mov_b32_e32 v31, v15
|
|
; VI-NEXT: v_mov_b32_e32 v32, v14
|
|
; VI-NEXT: v_mov_b32_e32 v33, v13
|
|
; VI-NEXT: v_mov_b32_e32 v34, v12
|
|
; VI-NEXT: v_mov_b32_e32 v35, v11
|
|
; VI-NEXT: v_mov_b32_e32 v36, v10
|
|
; VI-NEXT: v_mov_b32_e32 v37, v9
|
|
; VI-NEXT: v_mov_b32_e32 v38, v8
|
|
; VI-NEXT: v_mov_b32_e32 v39, v7
|
|
; VI-NEXT: v_mov_b32_e32 v48, v6
|
|
; VI-NEXT: v_mov_b32_e32 v49, v5
|
|
; VI-NEXT: v_mov_b32_e32 v50, v4
|
|
; VI-NEXT: v_mov_b32_e32 v51, v3
|
|
; VI-NEXT: v_mov_b32_e32 v52, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:124
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:120
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:116
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:112
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:108
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:104
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:100
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:96
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:92
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB86_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
|
|
; VI-NEXT: v_perm_b32 v3, v48, v39, s6
|
|
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
|
|
; VI-NEXT: v_perm_b32 v2, v50, v49, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
|
|
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; kill: killed $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v16, v25, v16, s6
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: .LBB86_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB86_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v54
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v53
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v52
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v51
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v50
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v49
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v48
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v39
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_mov_b32_e32 v15, 0x300
|
|
; VI-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; VI-NEXT: v_add_u16_sdwa v1, v1, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v38
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v37
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v36
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v35
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; VI-NEXT: v_add_u16_sdwa v3, v3, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; VI-NEXT: v_lshlrev_b16_e32 v4, 8, v33
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v32
|
|
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v31
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; VI-NEXT: v_add_u16_sdwa v4, v4, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v16
|
|
; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v17
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v18
|
|
; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v19
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v4, 0x300, v4
|
|
; VI-NEXT: v_add_u16_sdwa v5, v5, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v20
|
|
; VI-NEXT: v_lshlrev_b16_e32 v6, 8, v21
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v22
|
|
; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v23
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v5, 0x300, v5
|
|
; VI-NEXT: v_add_u16_sdwa v6, v6, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v30
|
|
; VI-NEXT: v_lshlrev_b16_e32 v10, 8, v27
|
|
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v29
|
|
; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v42
|
|
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v63
|
|
; VI-NEXT: v_lshlrev_b16_e32 v14, 8, v59
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(5)
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v7, 8, v7
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v6, 0x300, v6
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; VI-NEXT: s_waitcnt vmcnt(3)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v18, 8, v18
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v7, v7, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v7, 0x300, v7
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v8, v8, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v57
|
|
; VI-NEXT: v_lshlrev_b16_e32 v9, 8, v56
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v26
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v8, 0x300, v8
|
|
; VI-NEXT: v_add_u16_sdwa v9, v9, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v47
|
|
; VI-NEXT: v_lshlrev_b16_e32 v10, 8, v46
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v28
|
|
; VI-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v9, 0x300, v9
|
|
; VI-NEXT: v_add_u16_sdwa v10, v10, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v45
|
|
; VI-NEXT: v_lshlrev_b16_e32 v11, 8, v44
|
|
; VI-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v43
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v10, 0x300, v10
|
|
; VI-NEXT: v_add_u16_sdwa v11, v11, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v41
|
|
; VI-NEXT: v_lshlrev_b16_e32 v12, 8, v40
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v55
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v11, 0x300, v11
|
|
; VI-NEXT: v_add_u16_sdwa v12, v12, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v62
|
|
; VI-NEXT: v_lshlrev_b16_e32 v13, 8, v61
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v60
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v12, 0x300, v12
|
|
; VI-NEXT: v_add_u16_sdwa v13, v13, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v58
|
|
; VI-NEXT: v_lshlrev_b16_e32 v14, 8, v24
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v13, 0x300, v13
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: v_or_b32_sdwa v14, v16, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v14, v14, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; VI-NEXT: v_or_b32_sdwa v14, v16, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v16
|
|
; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v16, v16, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v16, 3, v16
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; VI-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v17, 3, v25
|
|
; VI-NEXT: v_or_b32_sdwa v17, v18, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v16
|
|
; VI-NEXT: v_add_u16_sdwa v15, v17, v15 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; VI-NEXT: .LBB86_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v8f64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:128
|
|
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
|
|
; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:80
|
|
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, v15
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, v14
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, v13
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, v12
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, v11
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, v2
|
|
; GFX9-NEXT: s_waitcnt vmcnt(24)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(22)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:124
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:120
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:116
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:112
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:108
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:104
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:100
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:96
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:92
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB86_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v0, v54, v53, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v52, v51, s6
|
|
; GFX9-NEXT: v_perm_b32 v2, v50, v49, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v48, v39, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v2, v38, v37, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v36, v35, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v3, v34, v33, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v32, v31, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v9, v47, v46, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v45, v44, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v42, v30, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v55, v63, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v60, v59, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr22
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s6
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s6
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v43, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
|
|
; GFX9-NEXT: v_perm_b32 v8, v24, v25, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
|
|
; GFX9-NEXT: v_perm_b32 v9, v26, v27, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
|
|
; GFX9-NEXT: v_perm_b32 v10, v28, v29, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v11, 16, v10
|
|
; GFX9-NEXT: v_perm_b32 v11, v41, v40, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, v62, v61, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
|
|
; GFX9-NEXT: v_perm_b32 v13, v58, v57, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; kill: killed $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s6
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v15, v16, v15, s6
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v16, v56, v16, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: .LBB86_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB86_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v54
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v53
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 3, v52
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v2, 8, v51
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v50
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v49
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v48
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v39
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x300
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v38
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 8, v37
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v36
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v35
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u16_sdwa v3, v3, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 8, v33
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 3, v32
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v31
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_add_u16_sdwa v4, v4, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 3, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v5, 8, v17
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 3, v18
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v19
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_add_u16_sdwa v5, v5, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 3, v20
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v6, 8, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 3, v22
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v23
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_add_u16_sdwa v6, v6, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v43
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v46
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v44
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v30
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v63
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v59
|
|
; GFX9-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v7, 8, v7
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v17, 8, v17
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v7, v7, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v8, 8, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v8, v8, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 3, v24
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v9, 8, v25
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 3, v47
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v8
|
|
; GFX9-NEXT: v_add_u16_sdwa v9, v9, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 3, v26
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v10, 8, v27
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 3, v45
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v9
|
|
; GFX9-NEXT: v_add_u16_sdwa v10, v10, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 3, v28
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v11, 8, v29
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 3, v42
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v10
|
|
; GFX9-NEXT: v_add_u16_sdwa v11, v11, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 3, v41
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v12, 8, v40
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 3, v55
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v11
|
|
; GFX9-NEXT: v_add_u16_sdwa v12, v12, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 3, v62
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v13, 8, v61
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 3, v60
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v12
|
|
; GFX9-NEXT: v_add_u16_sdwa v13, v13, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 3, v58
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v14, 8, v57
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v14, v14, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_sdwa v15, v15, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v16, 8, v16
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v16, 3, v56
|
|
; GFX9-NEXT: v_or_b32_sdwa v16, v17, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v15
|
|
; GFX9-NEXT: v_add_u16_sdwa v16, v16, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX9-NEXT: .LBB86_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v8f64:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1f
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:128
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:124
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:116
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:112
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:108
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:104
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:100
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:96
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:92
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:88
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:84
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:80
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:76
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:72
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:68
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:64
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v128, off, s32 offset:132
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v15.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v14.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v13.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v12.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v11.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v9.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v7.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v6.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v5.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v4.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v0.l
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v128
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB86_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB86_4
|
|
; GFX11-TRUE16-NEXT: .LBB86_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB86_3: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v119, v118, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v117, v116, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v114, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v113, v112, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v103, v101, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v102, v100, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v99, v98, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v97, v16, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v96, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v30, v87, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v86, v85, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v84, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v81, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v80, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v71, v69, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v68, v67, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v66, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v65, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v54, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v35, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB86_2
|
|
; GFX11-TRUE16-NEXT: .LBB86_4: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v119.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v117.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v118.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v116.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v115.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v113.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v114.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v112.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v103.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v102.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v100.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v99.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v2.h, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v101.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v17.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v3.h, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v4.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0xff, v4.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v98.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, v97.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, v96.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, v18.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, v20.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v3.l, v3.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v3.h, 0xff, v4.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v4.l, 8, v16.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v4.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v22.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, v26.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v27.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v3.h, v4.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v4.l, v5.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v4.h, 0xff, v5.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v5.l, 8, v19.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v21.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, v28.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v4.h, v5.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, v30.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v5.l, v6.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v5.h, 0xff, v6.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v23.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, v24.l, 3
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v86.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, v82.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v81.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v5.h, v6.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v6.l, 0xff, v6.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v6.h, 8, v25.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, v80.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, v71.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v68.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v6.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v7.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v7.l, 0xff, v8.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v7.h, 8, v29.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v8.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v87.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, v65.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v12.h, 8, v55.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v7.l, v7.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, v54.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v7.h, v8.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v9.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v8.h, 8, v85.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, v84.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.l, 0xff, v12.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v13.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v13.h, 8, v52.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v9.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v83.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v12.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, v51.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.l, 8, v50.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v49.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v9.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v9.l, v10.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.h, 0xff, v10.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v10.l, 8, v70.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v69.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v12.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v13.l, v13.h, v13.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v9.h, v10.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, v37.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v11.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.l, 8, v67.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v66.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, v35.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v33.l, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v36.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v11.h, 8, v64.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v15.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v34.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v15.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v32.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v11.l, v11.h, v11.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, v53.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v31.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v15.l, v17.l, v15.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v15.h, v17.h, v15.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v11.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v13.h, v14.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v12.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, v48.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v12.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v13.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v13.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, v38.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v14.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v14.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v14.h, 8, v39.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v3.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v13.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v3.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v4.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v14.h, v14.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v4.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v16.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v18.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v5.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v5.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v6.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v6.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v7.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v7.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v8.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v8.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v9.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v9.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v10.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v10.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v11.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v14.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v14.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v15.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v15.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v16.l
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v8f64:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v2 :: v_dual_mov_b32 v54, v0
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1f
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32 offset:128
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v65, off, s32 offset:124
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:120
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:116
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:112
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:108
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:104
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:100
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:96
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v80, off, s32 offset:92
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:88
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:84
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:80
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:76
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v84, off, s32 offset:72
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:68
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:64
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v103, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v113, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v112, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v114, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s32 offset:132
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v115, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v116, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v117, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v118, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v119, off, s32
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v15 :: v_dual_mov_b32 v32, v14
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, v13 :: v_dual_mov_b32 v34, v12
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v11 :: v_dual_mov_b32 v36, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, v9 :: v_dual_mov_b32 v38, v8
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v7 :: v_dual_mov_b32 v48, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, v5 :: v_dual_mov_b32 v50, v4
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v3 :: v_dual_mov_b32 v52, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB86_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB86_4
|
|
; GFX11-FAKE16-NEXT: .LBB86_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB86_3: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v54, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v53, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v48, v39, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v38, v37, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v36, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v34, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v16, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v18, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v20, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v22, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v24, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v26, v27, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v28, v29, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v30, v119, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v118, v117, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v116, v115, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v114, v112, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v113, v103, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v102, v100, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v101, v99, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v11, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v13, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v15, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v96, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v97, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v86, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v85, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v83, v81, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v70, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v71, v68, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v67, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v65, v55, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB86_2
|
|
; GFX11-FAKE16-NEXT: .LBB86_4: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v54, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v53, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v52
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v51
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v50, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v48, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v49
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v36, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v38, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v37
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v34, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v35
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v33
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v32, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v31
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v16, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v20, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v22, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v24, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v119
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v118, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v117
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v98, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v15, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v83, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v84
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v82
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v81
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v80, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v71, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v69, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v67, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v65, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v18, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v70
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v68
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v66
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v20
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v64
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v55
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v23, v19
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v25, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v20
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v8f64_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v28
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s11, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v24
|
|
; SI-NEXT: v_readfirstlane_b32 s13, v23
|
|
; SI-NEXT: v_readfirstlane_b32 s14, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s15, v21
|
|
; SI-NEXT: v_readfirstlane_b32 s40, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s41, v19
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s43, v17
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s45, v15
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s47, v13
|
|
; SI-NEXT: v_readfirstlane_b32 s56, v12
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v30
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s59, v9
|
|
; SI-NEXT: v_readfirstlane_b32 s60, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s61, v7
|
|
; SI-NEXT: v_readfirstlane_b32 s62, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s63, v5
|
|
; SI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s73, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s74, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s75, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s76, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
|
|
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 24, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 24, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 8, v22
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 24, v24
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 8, v25
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 24, v35
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v37
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 8, v27
|
|
; SI-NEXT: s_cbranch_scc0 .LBB87_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s6, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, s4, v34
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s18, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s77, s19, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s77, s5
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s77, s21, 8
|
|
; SI-NEXT: s_or_b32 s5, s5, s77
|
|
; SI-NEXT: s_and_b32 s77, s22, 0xff
|
|
; SI-NEXT: s_lshl_b32 s77, s77, 16
|
|
; SI-NEXT: s_lshl_b32 s78, s23, 24
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s77, s78, s77
|
|
; SI-NEXT: s_or_b32 s5, s5, s77
|
|
; SI-NEXT: s_and_b32 s77, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s78, s25, 8
|
|
; SI-NEXT: s_or_b32 s77, s77, s78
|
|
; SI-NEXT: s_and_b32 s78, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s78, s78, 16
|
|
; SI-NEXT: s_lshl_b32 s79, s27, 24
|
|
; SI-NEXT: s_and_b32 s77, s77, 0xffff
|
|
; SI-NEXT: s_or_b32 s78, s79, s78
|
|
; SI-NEXT: s_or_b32 s77, s77, s78
|
|
; SI-NEXT: s_and_b32 s78, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s79, s29, 8
|
|
; SI-NEXT: s_or_b32 s78, s78, s79
|
|
; SI-NEXT: s_and_b32 s79, s76, 0xff
|
|
; SI-NEXT: s_lshl_b32 s79, s79, 16
|
|
; SI-NEXT: s_lshl_b32 s88, s75, 24
|
|
; SI-NEXT: s_and_b32 s78, s78, 0xffff
|
|
; SI-NEXT: s_or_b32 s79, s88, s79
|
|
; SI-NEXT: s_or_b32 s78, s78, s79
|
|
; SI-NEXT: s_and_b32 s79, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s88, s73, 8
|
|
; SI-NEXT: s_or_b32 s79, s79, s88
|
|
; SI-NEXT: s_and_b32 s88, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s88, s88, 16
|
|
; SI-NEXT: s_lshl_b32 s89, s63, 24
|
|
; SI-NEXT: s_and_b32 s79, s79, 0xffff
|
|
; SI-NEXT: s_or_b32 s88, s89, s88
|
|
; SI-NEXT: s_or_b32 s79, s79, s88
|
|
; SI-NEXT: s_and_b32 s88, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s89, s61, 8
|
|
; SI-NEXT: s_or_b32 s88, s88, s89
|
|
; SI-NEXT: s_and_b32 s89, s60, 0xff
|
|
; SI-NEXT: s_lshl_b32 s89, s89, 16
|
|
; SI-NEXT: s_lshl_b32 s90, s59, 24
|
|
; SI-NEXT: s_and_b32 s88, s88, 0xffff
|
|
; SI-NEXT: s_or_b32 s89, s90, s89
|
|
; SI-NEXT: s_or_b32 s88, s88, s89
|
|
; SI-NEXT: s_and_b32 s89, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s90, s57, 8
|
|
; SI-NEXT: s_or_b32 s89, s89, s90
|
|
; SI-NEXT: s_and_b32 s90, s56, 0xff
|
|
; SI-NEXT: s_lshl_b32 s90, s90, 16
|
|
; SI-NEXT: s_lshl_b32 s91, s47, 24
|
|
; SI-NEXT: s_and_b32 s89, s89, 0xffff
|
|
; SI-NEXT: s_or_b32 s90, s91, s90
|
|
; SI-NEXT: s_or_b32 s89, s89, s90
|
|
; SI-NEXT: s_and_b32 s90, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s91, s45, 8
|
|
; SI-NEXT: s_or_b32 s90, s90, s91
|
|
; SI-NEXT: s_and_b32 s91, s44, 0xff
|
|
; SI-NEXT: s_lshl_b32 s91, s91, 16
|
|
; SI-NEXT: s_lshl_b32 s92, s43, 24
|
|
; SI-NEXT: s_and_b32 s90, s90, 0xffff
|
|
; SI-NEXT: s_or_b32 s91, s92, s91
|
|
; SI-NEXT: s_or_b32 s90, s90, s91
|
|
; SI-NEXT: s_and_b32 s91, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s92, s41, 8
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v20
|
|
; SI-NEXT: s_or_b32 s91, s91, s92
|
|
; SI-NEXT: s_and_b32 s92, s40, 0xff
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_lshl_b32 s92, s92, 16
|
|
; SI-NEXT: s_lshl_b32 s93, s15, 24
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v33, v1
|
|
; SI-NEXT: s_and_b32 s91, s91, 0xffff
|
|
; SI-NEXT: s_or_b32 s92, s93, s92
|
|
; SI-NEXT: v_or_b32_e32 v11, v0, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v23
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v21
|
|
; SI-NEXT: s_or_b32 s91, s91, s92
|
|
; SI-NEXT: s_and_b32 s92, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s93, s13, 8
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s92, s92, s93
|
|
; SI-NEXT: s_and_b32 s93, s12, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v29, v1
|
|
; SI-NEXT: s_lshl_b32 s93, s93, 16
|
|
; SI-NEXT: s_lshl_b32 s94, s11, 24
|
|
; SI-NEXT: v_or_b32_e32 v13, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v19
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v18
|
|
; SI-NEXT: s_and_b32 s92, s92, 0xffff
|
|
; SI-NEXT: s_or_b32 s93, s94, s93
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s92, s92, s93
|
|
; SI-NEXT: s_and_b32 s93, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s94, s9, 8
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v25, v1
|
|
; SI-NEXT: s_or_b32 s93, s93, s94
|
|
; SI-NEXT: s_and_b32 s94, s8, 0xff
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v28
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v26
|
|
; SI-NEXT: v_or_b32_e32 v14, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v17
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v16
|
|
; SI-NEXT: s_lshl_b32 s94, s94, 16
|
|
; SI-NEXT: s_lshl_b32 s95, s7, 24
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_and_b32 s93, s93, 0xffff
|
|
; SI-NEXT: s_or_b32 s94, s95, s94
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v3, v31, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v22, v1
|
|
; SI-NEXT: s_or_b32 s93, s93, s94
|
|
; SI-NEXT: v_or_b32_e32 v12, v2, v3
|
|
; SI-NEXT: v_or_b32_e32 v15, v0, v1
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
; SI-NEXT: v_mov_b32_e32 v2, s77
|
|
; SI-NEXT: v_mov_b32_e32 v3, s78
|
|
; SI-NEXT: v_mov_b32_e32 v4, s79
|
|
; SI-NEXT: v_mov_b32_e32 v5, s88
|
|
; SI-NEXT: v_mov_b32_e32 v6, s89
|
|
; SI-NEXT: v_mov_b32_e32 v7, s90
|
|
; SI-NEXT: v_mov_b32_e32 v8, s91
|
|
; SI-NEXT: v_mov_b32_e32 v9, s92
|
|
; SI-NEXT: v_mov_b32_e32 v10, s93
|
|
; SI-NEXT: s_cbranch_execnz .LBB87_3
|
|
; SI-NEXT: .LBB87_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s16, s18, 0xff
|
|
; SI-NEXT: s_addk_i32 s4, 0x300
|
|
; SI-NEXT: s_lshl_b32 s5, s19, 24
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s5, s16
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s16, s21, 8
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_or_b32 s5, s16, s5
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xff
|
|
; SI-NEXT: s_addk_i32 s5, 0x300
|
|
; SI-NEXT: s_lshl_b32 s16, s23, 24
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_or_b32 s5, s16, s5
|
|
; SI-NEXT: s_and_b32 s16, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s25, 8
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s6, s6, 3
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s18, s26, 0xff
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
|
|
; SI-NEXT: s_addk_i32 s16, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s27, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, s6, v34
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s17, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s18, s29, 8
|
|
; SI-NEXT: s_add_i32 s76, s76, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v33, v1
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_and_b32 s19, s76, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_addk_i32 s17, 0x300
|
|
; SI-NEXT: s_lshl_b32 s18, s75, 24
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 0x3000000, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v28
|
|
; SI-NEXT: s_and_b32 s17, s17, 0xffff
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_add_i32 s74, s74, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_and_b32 s18, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s19, s73, 8
|
|
; SI-NEXT: s_add_i32 s72, s72, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v32, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_and_b32 s20, s72, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_addk_i32 s18, 0x300
|
|
; SI-NEXT: s_lshl_b32 s19, s63, 24
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v31, v1
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xffff
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_add_i32 s62, s62, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_and_b32 s19, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s20, s61, 8
|
|
; SI-NEXT: s_add_i32 s60, s60, 3
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v23
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s21, s60, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v21
|
|
; SI-NEXT: s_addk_i32 s19, 0x300
|
|
; SI-NEXT: s_lshl_b32 s20, s59, 24
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, v30, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s19, s19, 0xffff
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_add_i32 s58, s58, 3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s20, s58, 0xff
|
|
; SI-NEXT: s_lshl_b32 s21, s57, 8
|
|
; SI-NEXT: s_add_i32 s56, s56, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v29, v1
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s22, s56, 0xff
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_addk_i32 s20, 0x300
|
|
; SI-NEXT: s_lshl_b32 s21, s47, 24
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19
|
|
; SI-NEXT: s_and_b32 s20, s20, 0xffff
|
|
; SI-NEXT: s_or_b32 s21, s21, s22
|
|
; SI-NEXT: s_add_i32 s46, s46, 3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v18
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s21, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s22, s45, 8
|
|
; SI-NEXT: s_add_i32 s44, s44, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v27, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_or_b32 s21, s22, s21
|
|
; SI-NEXT: s_and_b32 s23, s44, 0xff
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_addk_i32 s21, 0x300
|
|
; SI-NEXT: s_lshl_b32 s22, s43, 24
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v25, v1
|
|
; SI-NEXT: s_and_b32 s21, s21, 0xffff
|
|
; SI-NEXT: s_or_b32 s22, s22, s23
|
|
; SI-NEXT: s_add_i32 s42, s42, 3
|
|
; SI-NEXT: s_add_i32 s14, s14, 3
|
|
; SI-NEXT: s_add_i32 s10, s10, 3
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: s_or_b32 s21, s22, s21
|
|
; SI-NEXT: s_and_b32 s22, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s23, s41, 8
|
|
; SI-NEXT: s_add_i32 s40, s40, 3
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 8
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 8
|
|
; SI-NEXT: s_add_i32 s8, s8, 3
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v17
|
|
; SI-NEXT: s_or_b32 s22, s23, s22
|
|
; SI-NEXT: s_and_b32 s23, s40, 0xff
|
|
; SI-NEXT: s_or_b32 s13, s13, s14
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xff
|
|
; SI-NEXT: s_or_b32 s9, s9, s10
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xff
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16
|
|
; SI-NEXT: s_addk_i32 s22, 0x300
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 24
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_addk_i32 s13, 0x300
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 24
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_addk_i32 s9, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 24
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: v_or_b32_e32 v0, v24, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_and_b32 s22, s22, 0xffff
|
|
; SI-NEXT: s_or_b32 s15, s15, s23
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_or_b32 s11, s11, s12
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s8
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_or_b32 s15, s15, s22
|
|
; SI-NEXT: s_or_b32 s11, s11, s13
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v22, v1
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
|
|
; SI-NEXT: s_add_i32 s16, s16, 0x3000000
|
|
; SI-NEXT: s_add_i32 s17, s17, 0x3000000
|
|
; SI-NEXT: s_add_i32 s18, s18, 0x3000000
|
|
; SI-NEXT: s_add_i32 s19, s19, 0x3000000
|
|
; SI-NEXT: s_add_i32 s20, s20, 0x3000000
|
|
; SI-NEXT: s_add_i32 s21, s21, 0x3000000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x3000000, v0
|
|
; SI-NEXT: v_mov_b32_e32 v0, s4
|
|
; SI-NEXT: v_mov_b32_e32 v1, s5
|
|
; SI-NEXT: v_mov_b32_e32 v2, s16
|
|
; SI-NEXT: v_mov_b32_e32 v3, s17
|
|
; SI-NEXT: v_mov_b32_e32 v4, s18
|
|
; SI-NEXT: v_mov_b32_e32 v5, s19
|
|
; SI-NEXT: v_mov_b32_e32 v6, s20
|
|
; SI-NEXT: v_mov_b32_e32 v7, s21
|
|
; SI-NEXT: v_mov_b32_e32 v8, s15
|
|
; SI-NEXT: v_mov_b32_e32 v9, s11
|
|
; SI-NEXT: v_mov_b32_e32 v10, s7
|
|
; SI-NEXT: .LBB87_3: ; %end
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB87_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; SI-NEXT: s_branch .LBB87_2
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v8f64_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v30
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v29
|
|
; VI-NEXT: v_readfirstlane_b32 s8, v28
|
|
; VI-NEXT: v_readfirstlane_b32 s9, v27
|
|
; VI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; VI-NEXT: v_readfirstlane_b32 s11, v25
|
|
; VI-NEXT: v_readfirstlane_b32 s12, v24
|
|
; VI-NEXT: v_readfirstlane_b32 s13, v23
|
|
; VI-NEXT: v_readfirstlane_b32 s14, v22
|
|
; VI-NEXT: v_readfirstlane_b32 s15, v21
|
|
; VI-NEXT: v_readfirstlane_b32 s40, v20
|
|
; VI-NEXT: v_readfirstlane_b32 s41, v19
|
|
; VI-NEXT: v_readfirstlane_b32 s42, v18
|
|
; VI-NEXT: v_readfirstlane_b32 s43, v17
|
|
; VI-NEXT: v_readfirstlane_b32 s44, v16
|
|
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: v_readfirstlane_b32 s45, v15
|
|
; VI-NEXT: v_readfirstlane_b32 s46, v14
|
|
; VI-NEXT: v_readfirstlane_b32 s47, v13
|
|
; VI-NEXT: v_readfirstlane_b32 s56, v12
|
|
; VI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; VI-NEXT: v_readfirstlane_b32 s58, v10
|
|
; VI-NEXT: v_readfirstlane_b32 s59, v9
|
|
; VI-NEXT: v_readfirstlane_b32 s60, v8
|
|
; VI-NEXT: v_readfirstlane_b32 s61, v7
|
|
; VI-NEXT: v_readfirstlane_b32 s62, v6
|
|
; VI-NEXT: v_readfirstlane_b32 s63, v5
|
|
; VI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; VI-NEXT: v_readfirstlane_b32 s73, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s74, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s75, v1
|
|
; VI-NEXT: v_readfirstlane_b32 s76, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; VI-NEXT: s_cbranch_scc0 .LBB87_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_mov_b32_e32 v3, s23
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_mov_b32_e32 v2, s21
|
|
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s75
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_mov_b32_e32 v5, s63
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_mov_b32_e32 v4, s73
|
|
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_mov_b32_e32 v5, s61
|
|
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_mov_b32_e32 v7, s47
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_mov_b32_e32 v6, s57
|
|
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_mov_b32_e32 v8, s43
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_mov_b32_e32 v7, s45
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_mov_b32_e32 v9, s15
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_mov_b32_e32 v8, s41
|
|
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_mov_b32_e32 v10, s11
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_mov_b32_e32 v9, s13
|
|
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_mov_b32_e32 v12, s7
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_mov_b32_e32 v10, s9
|
|
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; VI-NEXT: v_perm_b32 v12, v24, v22, s4
|
|
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
|
|
; VI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
|
|
; VI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
|
|
; VI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
|
|
; VI-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; VI-NEXT: s_cbranch_execnz .LBB87_3
|
|
; VI-NEXT: .LBB87_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x300, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s21
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: v_mov_b32_e32 v2, s23
|
|
; VI-NEXT: v_perm_b32 v1, s20, v1, v11
|
|
; VI-NEXT: v_perm_b32 v2, s22, v2, v11
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x300, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x300, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: s_add_i32 s76, s76, 3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s75
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x300, v3
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s74, s74, 3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s73
|
|
; VI-NEXT: s_add_i32 s72, s72, 3
|
|
; VI-NEXT: v_mov_b32_e32 v5, s63
|
|
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x300, v4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s62, s62, 3
|
|
; VI-NEXT: v_mov_b32_e32 v5, s61
|
|
; VI-NEXT: s_add_i32 s60, s60, 3
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x300, v5
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s58, s58, 3
|
|
; VI-NEXT: v_mov_b32_e32 v6, s57
|
|
; VI-NEXT: s_add_i32 s56, s56, 3
|
|
; VI-NEXT: v_mov_b32_e32 v7, s47
|
|
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x300, v6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s46, s46, 3
|
|
; VI-NEXT: v_mov_b32_e32 v7, s45
|
|
; VI-NEXT: s_add_i32 s44, s44, 3
|
|
; VI-NEXT: v_mov_b32_e32 v8, s43
|
|
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x300, v7
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s42, s42, 3
|
|
; VI-NEXT: v_mov_b32_e32 v8, s41
|
|
; VI-NEXT: s_add_i32 s40, s40, 3
|
|
; VI-NEXT: v_mov_b32_e32 v9, s15
|
|
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x300, v8
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s14, s14, 3
|
|
; VI-NEXT: v_mov_b32_e32 v9, s13
|
|
; VI-NEXT: s_add_i32 s12, s12, 3
|
|
; VI-NEXT: v_mov_b32_e32 v10, s11
|
|
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x300, v9
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s10, s10, 3
|
|
; VI-NEXT: v_mov_b32_e32 v10, s9
|
|
; VI-NEXT: s_add_i32 s8, s8, 3
|
|
; VI-NEXT: v_mov_b32_e32 v12, s7
|
|
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x300, v10
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_sdwa v10, v12, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v24
|
|
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
|
|
; VI-NEXT: v_perm_b32 v12, v12, v22, s4
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x300, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 3, v34
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v32
|
|
; VI-NEXT: v_perm_b32 v12, v12, v33, s4
|
|
; VI-NEXT: v_perm_b32 v13, v13, v31, s4
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x300, v12
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 3, v30
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v28
|
|
; VI-NEXT: v_perm_b32 v13, v13, v29, s4
|
|
; VI-NEXT: v_perm_b32 v14, v14, v27, s4
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x300, v13
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 3, v25
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v21
|
|
; VI-NEXT: v_perm_b32 v14, v14, v23, s4
|
|
; VI-NEXT: v_perm_b32 v15, v15, v20, s4
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x300, v14
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 3, v19
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 3, v17
|
|
; VI-NEXT: v_perm_b32 v15, v15, v18, s4
|
|
; VI-NEXT: v_perm_b32 v16, v17, v16, s4
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x300, v15
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x3000000, v3
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x3000000, v4
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x3000000, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x3000000, v6
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x3000000, v10
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x3000000, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x3000000, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x3000000, v13
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x3000000, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x3000000, v15
|
|
; VI-NEXT: .LBB87_3: ; %end
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB87_4:
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_branch .LBB87_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v8f64_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v30
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v29
|
|
; GFX9-NEXT: v_readfirstlane_b32 s8, v28
|
|
; GFX9-NEXT: v_readfirstlane_b32 s9, v27
|
|
; GFX9-NEXT: v_readfirstlane_b32 s10, v26
|
|
; GFX9-NEXT: v_readfirstlane_b32 s11, v25
|
|
; GFX9-NEXT: v_readfirstlane_b32 s12, v24
|
|
; GFX9-NEXT: v_readfirstlane_b32 s13, v23
|
|
; GFX9-NEXT: v_readfirstlane_b32 s14, v22
|
|
; GFX9-NEXT: v_readfirstlane_b32 s15, v21
|
|
; GFX9-NEXT: v_readfirstlane_b32 s40, v20
|
|
; GFX9-NEXT: v_readfirstlane_b32 s41, v19
|
|
; GFX9-NEXT: v_readfirstlane_b32 s42, v18
|
|
; GFX9-NEXT: v_readfirstlane_b32 s43, v17
|
|
; GFX9-NEXT: v_readfirstlane_b32 s44, v16
|
|
; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s45, v15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s46, v14
|
|
; GFX9-NEXT: v_readfirstlane_b32 s47, v13
|
|
; GFX9-NEXT: v_readfirstlane_b32 s56, v12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s57, v11
|
|
; GFX9-NEXT: v_readfirstlane_b32 s58, v10
|
|
; GFX9-NEXT: v_readfirstlane_b32 s59, v9
|
|
; GFX9-NEXT: v_readfirstlane_b32 s60, v8
|
|
; GFX9-NEXT: v_readfirstlane_b32 s61, v7
|
|
; GFX9-NEXT: v_readfirstlane_b32 s62, v6
|
|
; GFX9-NEXT: v_readfirstlane_b32 s63, v5
|
|
; GFX9-NEXT: v_readfirstlane_b32 s72, v4
|
|
; GFX9-NEXT: v_readfirstlane_b32 s73, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s74, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s75, v1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s76, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s75
|
|
; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s63
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s73
|
|
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s59
|
|
; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s61
|
|
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s47
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s57
|
|
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s43
|
|
; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s45
|
|
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s15
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s41
|
|
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s11
|
|
; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s13
|
|
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s7
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s9
|
|
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
|
|
; GFX9-NEXT: .LBB87_2: ; %cmp.true
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; GFX9-NEXT: s_movk_i32 s4, 0x300
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_add_u32_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u32_sdwa v3, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_add_u32_sdwa v3, v3, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: s_add_i32 s76, s76, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s75
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_add_u32_sdwa v4, v4, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s73
|
|
; GFX9-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s63
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
|
|
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_add_u32_sdwa v5, v5, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s61
|
|
; GFX9-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s59
|
|
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
|
|
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_add_u32_sdwa v6, v6, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s57
|
|
; GFX9-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s47
|
|
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
|
|
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_add_u32_sdwa v7, v7, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s45
|
|
; GFX9-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s43
|
|
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
|
|
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_add_u32_sdwa v8, v8, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s41
|
|
; GFX9-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s15
|
|
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
|
|
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 0x300, v8
|
|
; GFX9-NEXT: v_add_u32_sdwa v9, v9, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s13
|
|
; GFX9-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s11
|
|
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
|
|
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 0x300, v9
|
|
; GFX9-NEXT: v_add_u32_sdwa v10, v10, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s9
|
|
; GFX9-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s7
|
|
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
|
|
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v23
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v21, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v11
|
|
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 3, v34
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v32
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v33, s5
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v31, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v12
|
|
; GFX9-NEXT: v_add_u32_sdwa v13, v13, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 3, v30
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v28
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v29, s5
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v27, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 3, v26
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v22
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v24, s5
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v20, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v14
|
|
; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 3, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v18, s5
|
|
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s5
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v15
|
|
; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; GFX9-NEXT: .LBB87_3: ; %end
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB87_4:
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_branch .LBB87_2
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v8f64_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0xf
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v27
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v26
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v25
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v24
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v23
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v22
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v21
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v19
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v18
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v16
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v15
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v14
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v13
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v12
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v11
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v10
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v9
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v8
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v7
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v5
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v4
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v3
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v2
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v1
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB87_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB87_3
|
|
; GFX11-TRUE16-NEXT: .LBB87_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s24, s25, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s28, s29, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s74, s73, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s62, s61, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s58, s57, v11
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s46, s45, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s42, s41, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s14, s13, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s12, s11, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s10, s9, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v13
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v14, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-TRUE16-NEXT: .LBB87_3: ; %end
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB87_4:
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB87_2
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v8f64_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_clause 0xf
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v30
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v29
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v28
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v27
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v26
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v25
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v24
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v23
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v22
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v21
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v19
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v18
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v16
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v15
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v14
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v13
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v12
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v11
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v10
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v9
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v8
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v7
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v6
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v5
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v4
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v3
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v2
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v1
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB87_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB87_3
|
|
; GFX11-FAKE16-NEXT: .LBB87_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s24, s25, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s26, s27, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s28, s29, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s74, s73, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s62, s61, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s58, s57, v11
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s46, s45, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s42, s41, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s13, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s12, s11, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s10, s9, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v13
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v14, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v51
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s8, s7, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s6, s5, v11
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s4, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v15, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v19, v20
|
|
; GFX11-FAKE16-NEXT: .LBB87_3: ; %end
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB87_4:
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB87_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <8 x double>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <8 x double>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <8 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <8 x double> %phi
|
|
}
|
|
|
|
define <32 x half> @bitcast_v32i16_to_v32f16(<32 x i16> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v32f16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v42, 16, v31
|
|
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v41, 16, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v43, 16, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v45, 16, v27
|
|
; SI-NEXT: s_waitcnt expcnt(5)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v47, 16, v26
|
|
; SI-NEXT: s_waitcnt expcnt(3)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v57, 16, v24
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v23
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v21
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB88_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v36, v1, v42
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v34, v1, v44
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v55, v0, v40
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v32, v1, v46
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v51, v0, v41
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v29, v1, v56
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v39, v0, v43
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v26, v1, v58
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v35, v0, v45
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v23, v1, v60
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v33, v0, v47
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v21, v1, v62
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
|
|
; SI-NEXT: v_or_b32_e32 v30, v0, v57
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v16, v1, v63
|
|
; SI-NEXT: v_or_b32_e32 v27, v0, v59
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v14
|
|
; SI-NEXT: v_alignbit_b32 v37, v36, v40, 16
|
|
; SI-NEXT: v_alignbit_b32 v38, v34, v41, 16
|
|
; SI-NEXT: v_alignbit_b32 v48, v32, v43, 16
|
|
; SI-NEXT: v_alignbit_b32 v49, v29, v45, 16
|
|
; SI-NEXT: v_alignbit_b32 v50, v26, v47, 16
|
|
; SI-NEXT: v_alignbit_b32 v52, v23, v57, 16
|
|
; SI-NEXT: v_alignbit_b32 v53, v21, v59, 16
|
|
; SI-NEXT: v_alignbit_b32 v54, v16, v61, 16
|
|
; SI-NEXT: v_or_b32_e32 v24, v0, v61
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: .LBB88_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB88_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v14, v61, v14
|
|
; SI-NEXT: s_mov_b32 s6, 0x30000
|
|
; SI-NEXT: v_or_b32_e32 v12, v59, v12
|
|
; SI-NEXT: v_or_b32_e32 v10, v57, v10
|
|
; SI-NEXT: v_or_b32_e32 v8, v47, v8
|
|
; SI-NEXT: v_or_b32_e32 v6, v45, v6
|
|
; SI-NEXT: v_or_b32_e32 v4, v43, v4
|
|
; SI-NEXT: v_or_b32_e32 v2, v41, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v40, v0
|
|
; SI-NEXT: v_add_i32_e32 v24, vcc, 0x30000, v14
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v27, vcc, s6, v12
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v30, vcc, s6, v10
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v8
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v35, vcc, s6, v6
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v55, vcc, s6, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v14, v63, v14
|
|
; SI-NEXT: v_or_b32_e32 v12, v62, v12
|
|
; SI-NEXT: v_or_b32_e32 v10, v60, v10
|
|
; SI-NEXT: v_or_b32_e32 v8, v58, v8
|
|
; SI-NEXT: v_or_b32_e32 v6, v56, v6
|
|
; SI-NEXT: v_or_b32_e32 v4, v46, v4
|
|
; SI-NEXT: v_or_b32_e32 v2, v44, v2
|
|
; SI-NEXT: v_or_b32_e32 v0, v42, v0
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, s6, v14
|
|
; SI-NEXT: v_add_i32_e32 v21, vcc, s6, v12
|
|
; SI-NEXT: v_add_i32_e32 v23, vcc, s6, v10
|
|
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v8
|
|
; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v6
|
|
; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v4
|
|
; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v2
|
|
; SI-NEXT: v_add_i32_e32 v36, vcc, s6, v0
|
|
; SI-NEXT: v_alignbit_b32 v37, v36, v55, 16
|
|
; SI-NEXT: v_alignbit_b32 v38, v34, v51, 16
|
|
; SI-NEXT: v_alignbit_b32 v48, v32, v39, 16
|
|
; SI-NEXT: v_alignbit_b32 v49, v29, v35, 16
|
|
; SI-NEXT: v_alignbit_b32 v50, v26, v33, 16
|
|
; SI-NEXT: v_alignbit_b32 v52, v23, v30, 16
|
|
; SI-NEXT: v_alignbit_b32 v53, v21, v27, 16
|
|
; SI-NEXT: v_alignbit_b32 v54, v16, v24, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v16
|
|
; SI-NEXT: .LBB88_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v55
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v48
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v35
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v49
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v33
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v50
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v52
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v53
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v18
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v54
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v32f16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB88_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 3
|
|
; VI-NEXT: v_add_u16_sdwa v19, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v13, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v13
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v12, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v12
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v11, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v11
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v10, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v10
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v9, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v9
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v8, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v7, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v6, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v5, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v5
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v4, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v4
|
|
; VI-NEXT: v_add_u16_sdwa v17, v0, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v18, v1, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v16, v3, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v3
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v2
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v1
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v16
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v19
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v18
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v17
|
|
; VI-NEXT: .LBB88_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v32f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB88_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB88_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v32f16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB88_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: .LBB88_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define inreg <32 x half> @bitcast_v32i16_to_v32f16_scalar(<32 x i16> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v32f16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v16, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v16, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v16, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v16, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v16, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v16, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v16, s30, 6
|
|
; SI-NEXT: v_writelane_b32 v16, s31, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s37, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s39, v0
|
|
; SI-NEXT: s_lshr_b32 s92, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s36, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s91, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s35, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s90, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s34, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s89, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s31, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s88, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s30, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s79, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s95, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s78, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s94, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s93, s37, 16
|
|
; SI-NEXT: s_lshr_b32 s38, s39, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB89_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s5, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s78, 16
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s44, s94, 16
|
|
; SI-NEXT: s_or_b32 s45, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s79, 16
|
|
; SI-NEXT: s_or_b32 s14, s4, s44
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s46, s95, 16
|
|
; SI-NEXT: s_or_b32 s47, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s88, 16
|
|
; SI-NEXT: s_or_b32 s12, s4, s46
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s56, s30, 16
|
|
; SI-NEXT: s_or_b32 s57, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s89, 16
|
|
; SI-NEXT: s_or_b32 s10, s4, s56
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s58, s31, 16
|
|
; SI-NEXT: s_or_b32 s59, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s90, 16
|
|
; SI-NEXT: s_or_b32 s8, s4, s58
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s60, s34, 16
|
|
; SI-NEXT: s_or_b32 s61, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s91, 16
|
|
; SI-NEXT: s_or_b32 s6, s4, s60
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s42, s35, 16
|
|
; SI-NEXT: s_or_b32 s43, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s92, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s42
|
|
; SI-NEXT: s_lshl_b32 s40, s36, 16
|
|
; SI-NEXT: s_or_b32 s41, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s37, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s93, 16
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[42:43], 16
|
|
; SI-NEXT: s_and_b32 s42, s28, 0xffff
|
|
; SI-NEXT: s_or_b32 s75, s5, s7
|
|
; SI-NEXT: s_lshl_b32 s74, s38, 16
|
|
; SI-NEXT: s_or_b32 s42, s42, s40
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[40:41], 16
|
|
; SI-NEXT: s_and_b32 s40, s39, 0xffff
|
|
; SI-NEXT: s_mov_b32 s15, s45
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[44:45], 16
|
|
; SI-NEXT: s_mov_b32 s13, s47
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[46:47], 16
|
|
; SI-NEXT: s_mov_b32 s11, s57
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[56:57], 16
|
|
; SI-NEXT: s_mov_b32 s9, s59
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[58:59], 16
|
|
; SI-NEXT: s_mov_b32 s7, s61
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
|
|
; SI-NEXT: s_mov_b32 s5, s43
|
|
; SI-NEXT: s_mov_b32 s43, s41
|
|
; SI-NEXT: s_or_b32 s40, s40, s74
|
|
; SI-NEXT: s_mov_b32 s41, s75
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB89_3
|
|
; SI-NEXT: .LBB89_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s39, s39, 3
|
|
; SI-NEXT: s_and_b32 s4, s39, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s38, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s37, s37, 3
|
|
; SI-NEXT: s_add_i32 s40, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s37, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s93, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_add_i32 s41, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s36, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_add_i32 s42, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s92, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_add_i32 s43, s4, 0x30000
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s35, 16
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s91, 16
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: s_and_b32 s6, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s34, 16
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s7, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s8, s90, 16
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: s_and_b32 s8, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s31, 16
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_and_b32 s9, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s10, s89, 16
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: s_and_b32 s10, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s11, s30, 16
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_or_b32 s10, s11, s10
|
|
; SI-NEXT: s_and_b32 s11, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s12, s88, 16
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_or_b32 s11, s12, s11
|
|
; SI-NEXT: s_and_b32 s12, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s13, s95, 16
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: s_and_b32 s13, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s14, s79, 16
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_or_b32 s13, s14, s13
|
|
; SI-NEXT: s_and_b32 s14, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s15, s94, 16
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_or_b32 s14, s15, s14
|
|
; SI-NEXT: s_and_b32 s15, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s78, 16
|
|
; SI-NEXT: s_or_b32 s15, s16, s15
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x30000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x30000
|
|
; SI-NEXT: s_add_i32 s6, s6, 0x30000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x30000
|
|
; SI-NEXT: s_add_i32 s8, s8, 0x30000
|
|
; SI-NEXT: s_add_i32 s9, s9, 0x30000
|
|
; SI-NEXT: s_add_i32 s10, s10, 0x30000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x30000
|
|
; SI-NEXT: s_add_i32 s12, s12, 0x30000
|
|
; SI-NEXT: s_add_i32 s13, s13, 0x30000
|
|
; SI-NEXT: s_add_i32 s14, s14, 0x30000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x30000
|
|
; SI-NEXT: s_lshr_b64 s[44:45], s[14:15], 16
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b64 s[58:59], s[8:9], 16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[42:43], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b32 s78, s15, 16
|
|
; SI-NEXT: s_lshr_b32 s79, s13, 16
|
|
; SI-NEXT: s_lshr_b32 s88, s11, 16
|
|
; SI-NEXT: s_lshr_b32 s89, s9, 16
|
|
; SI-NEXT: s_lshr_b32 s90, s7, 16
|
|
; SI-NEXT: s_lshr_b32 s91, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s92, s43, 16
|
|
; SI-NEXT: s_lshr_b32 s93, s41, 16
|
|
; SI-NEXT: .LBB89_3: ; %end
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s44, 16
|
|
; SI-NEXT: s_or_b32 s14, s14, s16
|
|
; SI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s78, 16
|
|
; SI-NEXT: s_or_b32 s15, s15, s16
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s46, 16
|
|
; SI-NEXT: s_or_b32 s12, s12, s16
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s79, 16
|
|
; SI-NEXT: s_or_b32 s13, s13, s16
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s56, 16
|
|
; SI-NEXT: s_or_b32 s10, s10, s16
|
|
; SI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s88, 16
|
|
; SI-NEXT: s_or_b32 s11, s11, s16
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s58, 16
|
|
; SI-NEXT: s_or_b32 s8, s8, s16
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s89, 16
|
|
; SI-NEXT: s_or_b32 s9, s9, s16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s60, 16
|
|
; SI-NEXT: s_or_b32 s6, s6, s16
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s90, 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s62, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s16
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s16, s91, 16
|
|
; SI-NEXT: s_or_b32 s5, s5, s16
|
|
; SI-NEXT: s_and_b32 s16, s42, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s17, s72, 16
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s43, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s18, s92, 16
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_and_b32 s18, s40, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s19, s74, 16
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_and_b32 s19, s41, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s93, 16
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: v_readlane_b32 s30, v16, 6
|
|
; SI-NEXT: v_mov_b32_e32 v0, s14
|
|
; SI-NEXT: v_mov_b32_e32 v1, s15
|
|
; SI-NEXT: v_mov_b32_e32 v2, s12
|
|
; SI-NEXT: v_mov_b32_e32 v3, s13
|
|
; SI-NEXT: v_mov_b32_e32 v4, s10
|
|
; SI-NEXT: v_mov_b32_e32 v5, s11
|
|
; SI-NEXT: v_mov_b32_e32 v6, s8
|
|
; SI-NEXT: v_mov_b32_e32 v7, s9
|
|
; SI-NEXT: v_mov_b32_e32 v8, s6
|
|
; SI-NEXT: v_mov_b32_e32 v9, s7
|
|
; SI-NEXT: v_mov_b32_e32 v10, s4
|
|
; SI-NEXT: v_mov_b32_e32 v11, s5
|
|
; SI-NEXT: v_mov_b32_e32 v12, s16
|
|
; SI-NEXT: v_mov_b32_e32 v13, s17
|
|
; SI-NEXT: v_mov_b32_e32 v14, s18
|
|
; SI-NEXT: v_mov_b32_e32 v15, s19
|
|
; SI-NEXT: v_readlane_b32 s31, v16, 7
|
|
; SI-NEXT: v_readlane_b32 s39, v16, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v16, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v16, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v16, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v16, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v16, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB89_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: s_branch .LBB89_2
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v32f16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB89_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB89_3
|
|
; VI-NEXT: .LBB89_2: ; %cmp.true
|
|
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s5, s16, 3
|
|
; VI-NEXT: s_and_b32 s8, s17, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s9, s17, 3
|
|
; VI-NEXT: s_and_b32 s10, s18, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s11, s18, 3
|
|
; VI-NEXT: s_and_b32 s12, s19, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s13, s19, 3
|
|
; VI-NEXT: s_and_b32 s14, s20, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s15, s20, 3
|
|
; VI-NEXT: s_and_b32 s16, s21, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s17, s21, 3
|
|
; VI-NEXT: s_and_b32 s18, s22, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s19, s22, 3
|
|
; VI-NEXT: s_and_b32 s20, s23, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s21, s23, 3
|
|
; VI-NEXT: s_and_b32 s22, s24, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s23, s24, 3
|
|
; VI-NEXT: s_and_b32 s24, s25, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_and_b32 s40, s26, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_and_b32 s41, s27, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_and_b32 s42, s28, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_and_b32 s43, s29, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_and_b32 s44, s7, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s7, s7, 3
|
|
; VI-NEXT: s_and_b32 s45, s6, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_and_b32 s29, s29, 0xffff
|
|
; VI-NEXT: s_and_b32 s28, s28, 0xffff
|
|
; VI-NEXT: s_and_b32 s27, s27, 0xffff
|
|
; VI-NEXT: s_and_b32 s26, s26, 0xffff
|
|
; VI-NEXT: s_and_b32 s25, s25, 0xffff
|
|
; VI-NEXT: s_and_b32 s23, s23, 0xffff
|
|
; VI-NEXT: s_and_b32 s21, s21, 0xffff
|
|
; VI-NEXT: s_and_b32 s19, s19, 0xffff
|
|
; VI-NEXT: s_and_b32 s17, s17, 0xffff
|
|
; VI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; VI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; VI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; VI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s45, s6
|
|
; VI-NEXT: s_or_b32 s7, s44, s7
|
|
; VI-NEXT: s_or_b32 s29, s43, s29
|
|
; VI-NEXT: s_or_b32 s28, s42, s28
|
|
; VI-NEXT: s_or_b32 s27, s41, s27
|
|
; VI-NEXT: s_or_b32 s26, s40, s26
|
|
; VI-NEXT: s_or_b32 s24, s24, s25
|
|
; VI-NEXT: s_or_b32 s22, s22, s23
|
|
; VI-NEXT: s_or_b32 s20, s20, s21
|
|
; VI-NEXT: s_or_b32 s18, s18, s19
|
|
; VI-NEXT: s_or_b32 s16, s16, s17
|
|
; VI-NEXT: s_or_b32 s14, s14, s15
|
|
; VI-NEXT: s_or_b32 s12, s12, s13
|
|
; VI-NEXT: s_or_b32 s10, s10, s11
|
|
; VI-NEXT: s_or_b32 s8, s8, s9
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s6, s6, 0x30000
|
|
; VI-NEXT: s_add_i32 s7, s7, 0x30000
|
|
; VI-NEXT: s_add_i32 s29, s29, 0x30000
|
|
; VI-NEXT: s_add_i32 s28, s28, 0x30000
|
|
; VI-NEXT: s_add_i32 s27, s27, 0x30000
|
|
; VI-NEXT: s_add_i32 s26, s26, 0x30000
|
|
; VI-NEXT: s_add_i32 s25, s24, 0x30000
|
|
; VI-NEXT: s_add_i32 s24, s22, 0x30000
|
|
; VI-NEXT: s_add_i32 s23, s20, 0x30000
|
|
; VI-NEXT: s_add_i32 s22, s18, 0x30000
|
|
; VI-NEXT: s_add_i32 s21, s16, 0x30000
|
|
; VI-NEXT: s_add_i32 s20, s14, 0x30000
|
|
; VI-NEXT: s_add_i32 s19, s12, 0x30000
|
|
; VI-NEXT: s_add_i32 s18, s10, 0x30000
|
|
; VI-NEXT: s_add_i32 s17, s8, 0x30000
|
|
; VI-NEXT: s_add_i32 s16, s4, 0x30000
|
|
; VI-NEXT: .LBB89_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB89_4:
|
|
; VI-NEXT: s_branch .LBB89_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v32f16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB89_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB89_4
|
|
; GFX9-NEXT: .LBB89_2: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, s31, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, s30, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB89_5
|
|
; GFX9-NEXT: .LBB89_3:
|
|
; GFX9-NEXT: s_branch .LBB89_2
|
|
; GFX9-NEXT: .LBB89_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB89_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v32f16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB89_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB89_4
|
|
; GFX11-NEXT: .LBB89_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB89_3:
|
|
; GFX11-NEXT: s_branch .LBB89_2
|
|
; GFX11-NEXT: .LBB89_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define <32 x i16> @bitcast_v32f16_to_v32i16(<32 x half> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v32i16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v5
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v0
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB90_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v19, v19
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v21, v21
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v23, v23
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v24, v24
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v26, v26
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v31, v31
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v30, v30
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v29, v29
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v28, v28
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v27, v27
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v25, v25
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v22, v22
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v20, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v18
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v26
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v21
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v31, 0x38000000, v31
|
|
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
|
|
; SI-NEXT: v_add_f32_e32 v29, 0x38000000, v29
|
|
; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
|
|
; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27
|
|
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
|
|
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
|
|
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v23
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v31, v31
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v24
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v30
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v29
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v28
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v27
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v25
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v22
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v20
|
|
; SI-NEXT: v_alignbit_b32 v31, v1, v31, 16
|
|
; SI-NEXT: v_alignbit_b32 v30, v3, v30, 16
|
|
; SI-NEXT: v_alignbit_b32 v29, v5, v29, 16
|
|
; SI-NEXT: v_alignbit_b32 v28, v7, v28, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v9, v27, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v11, v25, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v13, v22, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v15, v20, 16
|
|
; SI-NEXT: .LBB90_2: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v16
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v24
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v16
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v27
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v16
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v19
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v16
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v22
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v26
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v31
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v26
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v32i16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB90_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v17, 0x200
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v15
|
|
; VI-NEXT: v_add_f16_sdwa v15, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v19, v15
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v14
|
|
; VI-NEXT: v_add_f16_sdwa v14, v14, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v19, v14
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v13
|
|
; VI-NEXT: v_add_f16_sdwa v13, v13, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v19, v13
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v12
|
|
; VI-NEXT: v_add_f16_sdwa v12, v12, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v19, v12
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v11
|
|
; VI-NEXT: v_add_f16_sdwa v11, v11, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v19, v11
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v10
|
|
; VI-NEXT: v_add_f16_sdwa v10, v10, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v19, v10
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v9
|
|
; VI-NEXT: v_add_f16_sdwa v9, v9, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v19, v9
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v8
|
|
; VI-NEXT: v_add_f16_sdwa v8, v8, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v19, v8
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v7
|
|
; VI-NEXT: v_add_f16_sdwa v7, v7, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v19, v7
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v6
|
|
; VI-NEXT: v_add_f16_sdwa v6, v6, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v19, v6
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v5
|
|
; VI-NEXT: v_add_f16_sdwa v5, v5, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v19, v5
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v4
|
|
; VI-NEXT: v_add_f16_sdwa v4, v4, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v16, 0x200, v0
|
|
; VI-NEXT: v_add_f16_sdwa v0, v0, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v18, 0x200, v1
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v19, v4
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v2
|
|
; VI-NEXT: v_add_f16_sdwa v2, v2, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_sdwa v17, v3, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: v_or_b32_e32 v2, v19, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v18, v1
|
|
; VI-NEXT: v_or_b32_e32 v0, v16, v0
|
|
; VI-NEXT: .LBB90_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v32i16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB90_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB90_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v32i16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB90_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: .LBB90_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define inreg <32 x i16> @bitcast_v32f16_to_v32i16_scalar(<32 x half> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v32i16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v0
|
|
; SI-NEXT: s_lshr_b32 s41, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s42, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s12, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s40, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s43, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s45, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s9, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s46, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s8, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s47, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s44, s7, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s6, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB91_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_cbranch_execnz .LBB91_4
|
|
; SI-NEXT: .LBB91_2: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s46
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s45
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s18
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v2
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v2
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s43
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s40
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s14
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s44
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v1
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v1
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s42
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v32, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s27
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s12
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v33, v3
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v34, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s25
|
|
; SI-NEXT: v_or_b32_e32 v11, v1, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s23
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v35, v3
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v34
|
|
; SI-NEXT: v_or_b32_e32 v9, v5, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v35
|
|
; SI-NEXT: v_or_b32_e32 v7, v3, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s21
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v36, v1
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v37, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v36
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s19
|
|
; SI-NEXT: v_or_b32_e32 v5, v1, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v19, s17
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v39, v3
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v19, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s41
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v3, v15, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v1, v19, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v19, s7
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v38, v13
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v38
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s47
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v32
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v18, s20
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v19
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v19, s22
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
|
|
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v55, v16, v0
|
|
; SI-NEXT: v_or_b32_e32 v53, v17, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, s24
|
|
; SI-NEXT: v_or_b32_e32 v52, v18, v4
|
|
; SI-NEXT: v_or_b32_e32 v49, v19, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, s26
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v18, s28
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v19, s6
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
|
|
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v54, v16, v8
|
|
; SI-NEXT: v_or_b32_e32 v51, v17, v10
|
|
; SI-NEXT: v_or_b32_e32 v50, v18, v12
|
|
; SI-NEXT: v_or_b32_e32 v48, v19, v14
|
|
; SI-NEXT: v_lshr_b64 v[30:31], v[0:1], 16
|
|
; SI-NEXT: v_lshr_b64 v[28:29], v[2:3], 16
|
|
; SI-NEXT: v_lshr_b64 v[26:27], v[4:5], 16
|
|
; SI-NEXT: v_lshr_b64 v[24:25], v[6:7], 16
|
|
; SI-NEXT: v_lshr_b64 v[22:23], v[8:9], 16
|
|
; SI-NEXT: v_lshr_b64 v[20:21], v[10:11], 16
|
|
; SI-NEXT: v_lshr_b64 v[18:19], v[12:13], 16
|
|
; SI-NEXT: v_lshr_b64 v[16:17], v[14:15], 16
|
|
; SI-NEXT: s_branch .LBB91_5
|
|
; SI-NEXT: .LBB91_3:
|
|
; SI-NEXT: s_branch .LBB91_2
|
|
; SI-NEXT: .LBB91_4:
|
|
; SI-NEXT: v_mov_b32_e32 v32, s44
|
|
; SI-NEXT: v_mov_b32_e32 v38, s41
|
|
; SI-NEXT: v_mov_b32_e32 v33, s42
|
|
; SI-NEXT: v_mov_b32_e32 v34, s12
|
|
; SI-NEXT: v_mov_b32_e32 v35, s11
|
|
; SI-NEXT: v_mov_b32_e32 v36, s10
|
|
; SI-NEXT: v_mov_b32_e32 v37, s9
|
|
; SI-NEXT: v_mov_b32_e32 v39, s8
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v48, s6
|
|
; SI-NEXT: v_mov_b32_e32 v50, s28
|
|
; SI-NEXT: v_mov_b32_e32 v51, s26
|
|
; SI-NEXT: v_mov_b32_e32 v54, s24
|
|
; SI-NEXT: v_mov_b32_e32 v49, s22
|
|
; SI-NEXT: v_mov_b32_e32 v52, s20
|
|
; SI-NEXT: v_mov_b32_e32 v53, s18
|
|
; SI-NEXT: v_mov_b32_e32 v55, s16
|
|
; SI-NEXT: v_mov_b32_e32 v5, s21
|
|
; SI-NEXT: v_mov_b32_e32 v7, s23
|
|
; SI-NEXT: v_mov_b32_e32 v9, s25
|
|
; SI-NEXT: v_mov_b32_e32 v11, s27
|
|
; SI-NEXT: v_mov_b32_e32 v13, s29
|
|
; SI-NEXT: v_mov_b32_e32 v15, s7
|
|
; SI-NEXT: v_mov_b32_e32 v30, s47
|
|
; SI-NEXT: v_mov_b32_e32 v28, s46
|
|
; SI-NEXT: v_mov_b32_e32 v26, s45
|
|
; SI-NEXT: v_mov_b32_e32 v24, s43
|
|
; SI-NEXT: v_mov_b32_e32 v22, s40
|
|
; SI-NEXT: v_mov_b32_e32 v20, s14
|
|
; SI-NEXT: v_mov_b32_e32 v18, s13
|
|
; SI-NEXT: v_mov_b32_e32 v16, s15
|
|
; SI-NEXT: .LBB91_5: ; %end
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v30
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v55
|
|
; SI-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v53
|
|
; SI-NEXT: v_or_b32_e32 v2, v4, v2
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v26
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v52
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v36
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v49
|
|
; SI-NEXT: v_or_b32_e32 v6, v8, v6
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v54
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v22
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v10
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v34
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v20
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v33
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v50
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v18
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v14
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v48
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v32
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v32i16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v18, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v18, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB91_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB91_4
|
|
; VI-NEXT: .LBB91_2: ; %cmp.true
|
|
; VI-NEXT: s_lshr_b32 s5, s30, 16
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0x200
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: s_lshr_b32 s5, s31, 16
|
|
; VI-NEXT: v_add_f16_e32 v2, s30, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
; VI-NEXT: s_lshr_b32 s5, s29, 16
|
|
; VI-NEXT: v_or_b32_e32 v14, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s29, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s28, 16
|
|
; VI-NEXT: v_or_b32_e32 v13, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s28, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s27, 16
|
|
; VI-NEXT: v_or_b32_e32 v12, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s27, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s26, 16
|
|
; VI-NEXT: v_or_b32_e32 v11, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s26, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s25, 16
|
|
; VI-NEXT: v_or_b32_e32 v10, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s25, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s24, 16
|
|
; VI-NEXT: v_or_b32_e32 v9, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s24, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s23, 16
|
|
; VI-NEXT: v_or_b32_e32 v8, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s23, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s22, 16
|
|
; VI-NEXT: v_or_b32_e32 v7, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s22, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s21, 16
|
|
; VI-NEXT: v_or_b32_e32 v6, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v4, s31, v1
|
|
; VI-NEXT: v_add_f16_sdwa v5, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s21, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s20, 16
|
|
; VI-NEXT: v_or_b32_e32 v15, v4, v5
|
|
; VI-NEXT: v_or_b32_e32 v5, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s20, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s19, 16
|
|
; VI-NEXT: v_or_b32_e32 v4, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: s_lshr_b32 s5, s18, 16
|
|
; VI-NEXT: v_add_f16_e32 v2, s19, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_mov_b32_e32 v16, s5
|
|
; VI-NEXT: s_lshr_b32 s4, s16, 16
|
|
; VI-NEXT: v_or_b32_e32 v3, v2, v3
|
|
; VI-NEXT: v_add_f16_e32 v2, s18, v1
|
|
; VI-NEXT: v_add_f16_sdwa v16, v16, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v16
|
|
; VI-NEXT: v_mov_b32_e32 v16, s4
|
|
; VI-NEXT: s_lshr_b32 s4, s17, 16
|
|
; VI-NEXT: v_mov_b32_e32 v17, s4
|
|
; VI-NEXT: v_add_f16_e32 v0, s16, v1
|
|
; VI-NEXT: v_add_f16_sdwa v16, v16, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_sdwa v17, v17, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v1, s17, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v17
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: s_branch .LBB91_5
|
|
; VI-NEXT: .LBB91_3:
|
|
; VI-NEXT: s_branch .LBB91_2
|
|
; VI-NEXT: .LBB91_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB91_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v18, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v18, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v32i16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB91_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB91_4
|
|
; GFX9-NEXT: .LBB91_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, s31, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, s30, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB91_5
|
|
; GFX9-NEXT: .LBB91_3:
|
|
; GFX9-NEXT: s_branch .LBB91_2
|
|
; GFX9-NEXT: .LBB91_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB91_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v32i16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB91_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB91_4
|
|
; GFX11-NEXT: .LBB91_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB91_3:
|
|
; GFX11-NEXT: s_branch .LBB91_2
|
|
; GFX11-NEXT: .LBB91_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define <32 x bfloat> @bitcast_v32i16_to_v32bf16(<32 x i16> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v32bf16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB92_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: .LBB92_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB92_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v15, v31, v15
|
|
; SI-NEXT: s_mov_b32 s6, 0x30000
|
|
; SI-NEXT: v_or_b32_e32 v14, v30, v14
|
|
; SI-NEXT: v_or_b32_e32 v13, v29, v13
|
|
; SI-NEXT: v_or_b32_e32 v12, v28, v12
|
|
; SI-NEXT: v_or_b32_e32 v11, v27, v11
|
|
; SI-NEXT: v_or_b32_e32 v10, v26, v10
|
|
; SI-NEXT: v_or_b32_e32 v9, v25, v9
|
|
; SI-NEXT: v_or_b32_e32 v8, v24, v8
|
|
; SI-NEXT: v_or_b32_e32 v7, v23, v7
|
|
; SI-NEXT: v_or_b32_e32 v6, v22, v6
|
|
; SI-NEXT: v_or_b32_e32 v5, v21, v5
|
|
; SI-NEXT: v_or_b32_e32 v4, v20, v4
|
|
; SI-NEXT: v_or_b32_e32 v3, v19, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v18, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v17, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v16, v0
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 0x30000, v15
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v0
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v15
|
|
; SI-NEXT: .LBB92_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v32
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v33
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v34
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v35
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v36
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v37
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v38
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v39
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v48
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v49
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v50
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v51
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v52
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v53
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v54
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v55
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v32bf16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB92_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 3
|
|
; VI-NEXT: v_add_u16_sdwa v19, v15, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v15, 3, v15
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v14, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v14, 3, v14
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v13, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v13, 3, v13
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v12, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v12, 3, v12
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v11, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v11, 3, v11
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v10, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v10, 3, v10
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v9, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v9, 3, v9
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v8, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v8, 3, v8
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v7, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v7, 3, v7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v6, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v6, 3, v6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v5, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v5, 3, v5
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v4, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v4, 3, v4
|
|
; VI-NEXT: v_add_u16_sdwa v17, v0, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v18, v1, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v19
|
|
; VI-NEXT: v_add_u16_sdwa v19, v2, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v16, v3, v16 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v3
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v2
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v1
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v16
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v19
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v18
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v17
|
|
; VI-NEXT: .LBB92_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v32bf16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB92_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB92_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v32bf16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB92_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: .LBB92_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define inreg <32 x bfloat> @bitcast_v32i16_to_v32bf16_scalar(<32 x i16> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v32bf16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v17, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v17, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v17, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v17, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v17, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v17, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v17, s30, 6
|
|
; SI-NEXT: v_writelane_b32 v17, s31, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s39, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s37, v0
|
|
; SI-NEXT: s_lshr_b32 s35, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s34, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s31, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s30, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s95, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s94, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s93, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s92, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s91, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s90, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s89, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s88, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s79, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s78, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s38, s39, 16
|
|
; SI-NEXT: s_lshr_b32 s36, s37, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB93_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshl_b32 s73, s16, 16
|
|
; SI-NEXT: s_lshl_b32 s77, s78, 16
|
|
; SI-NEXT: s_lshl_b32 s63, s17, 16
|
|
; SI-NEXT: s_lshl_b32 s76, s79, 16
|
|
; SI-NEXT: s_lshl_b32 s61, s18, 16
|
|
; SI-NEXT: s_lshl_b32 s75, s88, 16
|
|
; SI-NEXT: s_lshl_b32 s59, s19, 16
|
|
; SI-NEXT: s_lshl_b32 s74, s89, 16
|
|
; SI-NEXT: s_lshl_b32 s57, s20, 16
|
|
; SI-NEXT: s_lshl_b32 s72, s90, 16
|
|
; SI-NEXT: s_lshl_b32 s47, s21, 16
|
|
; SI-NEXT: s_lshl_b32 s62, s91, 16
|
|
; SI-NEXT: s_lshl_b32 s45, s22, 16
|
|
; SI-NEXT: s_lshl_b32 s60, s92, 16
|
|
; SI-NEXT: s_lshl_b32 s43, s23, 16
|
|
; SI-NEXT: s_lshl_b32 s58, s93, 16
|
|
; SI-NEXT: s_lshl_b32 s41, s24, 16
|
|
; SI-NEXT: s_lshl_b32 s56, s94, 16
|
|
; SI-NEXT: s_lshl_b32 s15, s25, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s95, 16
|
|
; SI-NEXT: s_lshl_b32 s13, s26, 16
|
|
; SI-NEXT: s_lshl_b32 s44, s30, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s27, 16
|
|
; SI-NEXT: s_lshl_b32 s42, s31, 16
|
|
; SI-NEXT: s_lshl_b32 s10, s28, 16
|
|
; SI-NEXT: s_lshl_b32 s40, s34, 16
|
|
; SI-NEXT: s_lshl_b32 s8, s29, 16
|
|
; SI-NEXT: s_lshl_b32 s14, s35, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s37, 16
|
|
; SI-NEXT: s_lshl_b32 s12, s36, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s39, 16
|
|
; SI-NEXT: s_lshl_b32 s9, s38, 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB93_3
|
|
; SI-NEXT: .LBB93_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s39, s39, 3
|
|
; SI-NEXT: s_and_b32 s4, s39, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s38, 16
|
|
; SI-NEXT: s_add_i32 s37, s37, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s37, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s36, 16
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: s_and_b32 s6, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s35, 16
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s7, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s8, s34, 16
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s31, 16
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_and_b32 s9, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s10, s30, 16
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: s_and_b32 s10, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s11, s95, 16
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_or_b32 s10, s11, s10
|
|
; SI-NEXT: s_and_b32 s11, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s12, s94, 16
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_or_b32 s11, s12, s11
|
|
; SI-NEXT: s_and_b32 s12, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s13, s93, 16
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: s_and_b32 s13, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s14, s92, 16
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_or_b32 s13, s14, s13
|
|
; SI-NEXT: s_and_b32 s14, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s15, s91, 16
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_or_b32 s14, s15, s14
|
|
; SI-NEXT: s_and_b32 s15, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s90, 16
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_or_b32 s15, s20, s15
|
|
; SI-NEXT: s_and_b32 s19, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s89, 16
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_or_b32 s19, s20, s19
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s88, 16
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_or_b32 s18, s20, s18
|
|
; SI-NEXT: s_and_b32 s17, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s79, 16
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_or_b32 s17, s20, s17
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s78, 16
|
|
; SI-NEXT: s_or_b32 s16, s20, s16
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x30000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x30000
|
|
; SI-NEXT: s_add_i32 s6, s6, 0x30000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x30000
|
|
; SI-NEXT: s_add_i32 s8, s8, 0x30000
|
|
; SI-NEXT: s_add_i32 s9, s9, 0x30000
|
|
; SI-NEXT: s_add_i32 s10, s10, 0x30000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x30000
|
|
; SI-NEXT: s_add_i32 s12, s12, 0x30000
|
|
; SI-NEXT: s_add_i32 s13, s13, 0x30000
|
|
; SI-NEXT: s_add_i32 s14, s14, 0x30000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x30000
|
|
; SI-NEXT: s_add_i32 s19, s19, 0x30000
|
|
; SI-NEXT: s_add_i32 s18, s18, 0x30000
|
|
; SI-NEXT: s_add_i32 s17, s17, 0x30000
|
|
; SI-NEXT: s_add_i32 s16, s16, 0x30000
|
|
; SI-NEXT: s_and_b32 s77, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s73, s16, 16
|
|
; SI-NEXT: s_and_b32 s76, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s63, s17, 16
|
|
; SI-NEXT: s_and_b32 s75, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s61, s18, 16
|
|
; SI-NEXT: s_and_b32 s74, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s59, s19, 16
|
|
; SI-NEXT: s_and_b32 s72, s15, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s57, s15, 16
|
|
; SI-NEXT: s_and_b32 s62, s14, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s47, s14, 16
|
|
; SI-NEXT: s_and_b32 s60, s13, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s45, s13, 16
|
|
; SI-NEXT: s_and_b32 s58, s12, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s43, s12, 16
|
|
; SI-NEXT: s_and_b32 s56, s11, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s41, s11, 16
|
|
; SI-NEXT: s_and_b32 s46, s10, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s10, 16
|
|
; SI-NEXT: s_and_b32 s44, s9, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s9, 16
|
|
; SI-NEXT: s_and_b32 s42, s8, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s8, 16
|
|
; SI-NEXT: s_and_b32 s40, s7, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s10, s7, 16
|
|
; SI-NEXT: s_and_b32 s14, s6, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s8, s6, 16
|
|
; SI-NEXT: s_and_b32 s12, s5, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s5, 16
|
|
; SI-NEXT: s_and_b32 s9, s4, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s6, s4, 16
|
|
; SI-NEXT: .LBB93_3: ; %end
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s77
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s73
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s76
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s63
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s75
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s61
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s74
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s59
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s72
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s57
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s62
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s47
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s60
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s45
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s58
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s43
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s56
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s41
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s46
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s15
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s44
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s13
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s42
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s11
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s40
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s10
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s8
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s7
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s6
|
|
; SI-NEXT: v_readlane_b32 s30, v17, 6
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
|
|
; SI-NEXT: v_readlane_b32 s31, v17, 7
|
|
; SI-NEXT: v_readlane_b32 s39, v17, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v17, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v17, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v17, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v17, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v17, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB93_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr43
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr41
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr15
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr13
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr11
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr7
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr9
|
|
; SI-NEXT: s_branch .LBB93_2
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v32bf16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB93_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB93_3
|
|
; VI-NEXT: .LBB93_2: ; %cmp.true
|
|
; VI-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s5, s16, 3
|
|
; VI-NEXT: s_and_b32 s8, s17, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s9, s17, 3
|
|
; VI-NEXT: s_and_b32 s10, s18, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s11, s18, 3
|
|
; VI-NEXT: s_and_b32 s12, s19, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s13, s19, 3
|
|
; VI-NEXT: s_and_b32 s14, s20, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s15, s20, 3
|
|
; VI-NEXT: s_and_b32 s16, s21, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s17, s21, 3
|
|
; VI-NEXT: s_and_b32 s18, s22, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s19, s22, 3
|
|
; VI-NEXT: s_and_b32 s20, s23, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s21, s23, 3
|
|
; VI-NEXT: s_and_b32 s22, s24, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s23, s24, 3
|
|
; VI-NEXT: s_and_b32 s24, s25, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s25, s25, 3
|
|
; VI-NEXT: s_and_b32 s40, s26, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: s_and_b32 s41, s27, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s27, s27, 3
|
|
; VI-NEXT: s_and_b32 s42, s28, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: s_and_b32 s43, s29, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s29, s29, 3
|
|
; VI-NEXT: s_and_b32 s44, s7, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s7, s7, 3
|
|
; VI-NEXT: s_and_b32 s45, s6, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s6, s6, 3
|
|
; VI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_and_b32 s29, s29, 0xffff
|
|
; VI-NEXT: s_and_b32 s28, s28, 0xffff
|
|
; VI-NEXT: s_and_b32 s27, s27, 0xffff
|
|
; VI-NEXT: s_and_b32 s26, s26, 0xffff
|
|
; VI-NEXT: s_and_b32 s25, s25, 0xffff
|
|
; VI-NEXT: s_and_b32 s23, s23, 0xffff
|
|
; VI-NEXT: s_and_b32 s21, s21, 0xffff
|
|
; VI-NEXT: s_and_b32 s19, s19, 0xffff
|
|
; VI-NEXT: s_and_b32 s17, s17, 0xffff
|
|
; VI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; VI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; VI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; VI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s45, s6
|
|
; VI-NEXT: s_or_b32 s7, s44, s7
|
|
; VI-NEXT: s_or_b32 s29, s43, s29
|
|
; VI-NEXT: s_or_b32 s28, s42, s28
|
|
; VI-NEXT: s_or_b32 s27, s41, s27
|
|
; VI-NEXT: s_or_b32 s26, s40, s26
|
|
; VI-NEXT: s_or_b32 s24, s24, s25
|
|
; VI-NEXT: s_or_b32 s22, s22, s23
|
|
; VI-NEXT: s_or_b32 s20, s20, s21
|
|
; VI-NEXT: s_or_b32 s18, s18, s19
|
|
; VI-NEXT: s_or_b32 s16, s16, s17
|
|
; VI-NEXT: s_or_b32 s14, s14, s15
|
|
; VI-NEXT: s_or_b32 s12, s12, s13
|
|
; VI-NEXT: s_or_b32 s10, s10, s11
|
|
; VI-NEXT: s_or_b32 s8, s8, s9
|
|
; VI-NEXT: s_or_b32 s4, s4, s5
|
|
; VI-NEXT: s_add_i32 s6, s6, 0x30000
|
|
; VI-NEXT: s_add_i32 s7, s7, 0x30000
|
|
; VI-NEXT: s_add_i32 s29, s29, 0x30000
|
|
; VI-NEXT: s_add_i32 s28, s28, 0x30000
|
|
; VI-NEXT: s_add_i32 s27, s27, 0x30000
|
|
; VI-NEXT: s_add_i32 s26, s26, 0x30000
|
|
; VI-NEXT: s_add_i32 s25, s24, 0x30000
|
|
; VI-NEXT: s_add_i32 s24, s22, 0x30000
|
|
; VI-NEXT: s_add_i32 s23, s20, 0x30000
|
|
; VI-NEXT: s_add_i32 s22, s18, 0x30000
|
|
; VI-NEXT: s_add_i32 s21, s16, 0x30000
|
|
; VI-NEXT: s_add_i32 s20, s14, 0x30000
|
|
; VI-NEXT: s_add_i32 s19, s12, 0x30000
|
|
; VI-NEXT: s_add_i32 s18, s10, 0x30000
|
|
; VI-NEXT: s_add_i32 s17, s8, 0x30000
|
|
; VI-NEXT: s_add_i32 s16, s4, 0x30000
|
|
; VI-NEXT: .LBB93_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s7
|
|
; VI-NEXT: v_mov_b32_e32 v15, s6
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB93_4:
|
|
; VI-NEXT: s_branch .LBB93_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v32bf16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB93_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB93_4
|
|
; GFX9-NEXT: .LBB93_2: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v15, s31, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, s30, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, s29, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, s28, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, s27, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, s26, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, s25, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB93_5
|
|
; GFX9-NEXT: .LBB93_3:
|
|
; GFX9-NEXT: s_branch .LBB93_2
|
|
; GFX9-NEXT: .LBB93_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB93_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v32bf16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB93_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB93_4
|
|
; GFX11-NEXT: .LBB93_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v15, s27, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, s26, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, s25, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, s24, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, s23, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, s22, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, s21, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB93_3:
|
|
; GFX11-NEXT: s_branch .LBB93_2
|
|
; GFX11-NEXT: .LBB93_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define <32 x i16> @bitcast_v32bf16_to_v32i16(<32 x bfloat> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v32i16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e32 v63, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v62, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v1
|
|
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
|
|
; SI-NEXT: v_mul_f32_e32 v61, 1.0, v2
|
|
; SI-NEXT: v_mul_f32_e32 v60, 1.0, v32
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v31
|
|
; SI-NEXT: v_mul_f32_e32 v59, 1.0, v4
|
|
; SI-NEXT: v_mul_f32_e32 v58, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v57, 1.0, v6
|
|
; SI-NEXT: v_mul_f32_e32 v56, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v39, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v47, 1.0, v8
|
|
; SI-NEXT: v_mul_f32_e32 v46, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v49, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v23
|
|
; SI-NEXT: v_mul_f32_e32 v45, 1.0, v10
|
|
; SI-NEXT: v_mul_f32_e32 v44, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v51, 1.0, v11
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v43, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v42, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v53, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v52, 1.0, v19
|
|
; SI-NEXT: v_mul_f32_e32 v41, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v40, 1.0, v18
|
|
; SI-NEXT: v_mul_f32_e32 v55, 1.0, v15
|
|
; SI-NEXT: v_mul_f32_e32 v54, 1.0, v17
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB94_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v63
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v62
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v61
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v60
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v33
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v59
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v58
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v56
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v38
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v47
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v46
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v48
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v45
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v44
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v51
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v43
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 16, v42
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v53
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v52
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v40
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v54
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: .LBB94_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB94_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v62
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
|
|
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v1
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v60
|
|
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v61
|
|
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v58
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v59
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v56
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v46
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v47
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v44
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v45
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v42
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v43
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v40
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v41
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v54
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v55
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v52
|
|
; SI-NEXT: v_alignbit_b32 v15, v16, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v53
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
|
|
; SI-NEXT: v_alignbit_b32 v13, v17, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v48
|
|
; SI-NEXT: v_alignbit_b32 v11, v18, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v49
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v38
|
|
; SI-NEXT: v_alignbit_b32 v9, v19, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v36
|
|
; SI-NEXT: v_alignbit_b32 v7, v20, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v33
|
|
; SI-NEXT: v_alignbit_b32 v5, v21, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v34
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v23
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v27
|
|
; SI-NEXT: v_alignbit_b32 v3, v22, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v28
|
|
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_alignbit_b32 v1, v23, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
|
|
; SI-NEXT: v_alignbit_b32 v24, v1, v24, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v3, v25, 16
|
|
; SI-NEXT: v_alignbit_b32 v26, v5, v26, 16
|
|
; SI-NEXT: v_alignbit_b32 v29, v7, v29, 16
|
|
; SI-NEXT: v_alignbit_b32 v30, v9, v30, 16
|
|
; SI-NEXT: v_alignbit_b32 v31, v11, v31, 16
|
|
; SI-NEXT: v_alignbit_b32 v32, v13, v32, 16
|
|
; SI-NEXT: v_alignbit_b32 v35, v15, v35, 16
|
|
; SI-NEXT: .LBB94_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v23
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v22
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v21
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v20
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v30
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v19
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v18
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v32
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v17
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v35
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v24
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v23
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v22
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v21
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v20
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v19
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v18
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v32i16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB94_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; VI-NEXT: s_movk_i32 s6, 0x7fff
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; VI-NEXT: v_bfe_u32 v19, v18, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, s6, v19
|
|
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
|
|
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
|
|
; VI-NEXT: v_bfe_u32 v19, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v2
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, s6, v19
|
|
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
|
|
; VI-NEXT: v_bfe_u32 v20, v19, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, s6, v20
|
|
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
|
|
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
|
|
; VI-NEXT: v_bfe_u32 v20, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v3
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, s6, v20
|
|
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
|
|
; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, s6, v21
|
|
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v20
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
|
|
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
|
|
; VI-NEXT: v_bfe_u32 v21, v4, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v4
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, s6, v21
|
|
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
|
|
; VI-NEXT: v_bfe_u32 v22, v21, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, s6, v22
|
|
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
|
|
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
|
|
; VI-NEXT: v_bfe_u32 v22, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v5
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, s6, v22
|
|
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v22, v23, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v6
|
|
; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; VI-NEXT: v_bfe_u32 v23, v22, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, s6, v23
|
|
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
|
|
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc
|
|
; VI-NEXT: v_bfe_u32 v23, v6, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v6
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, s6, v23
|
|
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v6
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v23, v24, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; VI-NEXT: v_bfe_u32 v24, v23, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v23
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, s6, v24
|
|
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v23
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
|
|
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
|
|
; VI-NEXT: v_bfe_u32 v24, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v7
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, s6, v24
|
|
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v24, v25, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v8
|
|
; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
|
|
; VI-NEXT: v_bfe_u32 v25, v24, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, s6, v25
|
|
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v24
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
|
|
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
|
|
; VI-NEXT: v_bfe_u32 v25, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v8
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, s6, v25
|
|
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v25, v26, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
|
|
; VI-NEXT: v_bfe_u32 v26, v25, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v25
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, s6, v26
|
|
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; VI-NEXT: v_or_b32_e32 v27, 0x400000, v25
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
|
|
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
|
|
; VI-NEXT: v_bfe_u32 v26, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v9
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, s6, v26
|
|
; VI-NEXT: v_or_b32_e32 v27, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v26, v27, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
|
|
; VI-NEXT: v_bfe_u32 v27, v26, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v26
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, s6, v27
|
|
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; VI-NEXT: v_or_b32_e32 v28, 0x400000, v26
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
|
|
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc
|
|
; VI-NEXT: v_bfe_u32 v27, v10, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v10
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, s6, v27
|
|
; VI-NEXT: v_or_b32_e32 v28, 0x400000, v10
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v10, v27, v28, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
|
|
; VI-NEXT: v_bfe_u32 v28, v27, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v27
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, s6, v28
|
|
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; VI-NEXT: v_or_b32_e32 v29, 0x400000, v27
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
|
|
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc
|
|
; VI-NEXT: v_bfe_u32 v28, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v11
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, s6, v28
|
|
; VI-NEXT: v_or_b32_e32 v29, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v12
|
|
; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
|
|
; VI-NEXT: v_bfe_u32 v29, v28, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v28
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, s6, v29
|
|
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; VI-NEXT: v_or_b32_e32 v30, 0x400000, v28
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
|
|
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc
|
|
; VI-NEXT: v_bfe_u32 v29, v12, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v12
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, s6, v29
|
|
; VI-NEXT: v_or_b32_e32 v30, 0x400000, v12
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v12, v29, v30, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
|
|
; VI-NEXT: v_bfe_u32 v30, v29, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v29
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, s6, v30
|
|
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; VI-NEXT: v_or_b32_e32 v31, 0x400000, v29
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
|
|
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc
|
|
; VI-NEXT: v_bfe_u32 v30, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v13
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, s6, v30
|
|
; VI-NEXT: v_or_b32_e32 v31, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v30, v31, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v14
|
|
; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
|
|
; VI-NEXT: v_bfe_u32 v31, v30, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v30
|
|
; VI-NEXT: v_add_u32_e32 v31, vcc, s6, v31
|
|
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; VI-NEXT: v_or_b32_e32 v32, 0x400000, v30
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
|
|
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v30, v31, v32, vcc
|
|
; VI-NEXT: v_bfe_u32 v31, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v14
|
|
; VI-NEXT: v_add_u32_e32 v31, vcc, s6, v31
|
|
; VI-NEXT: v_or_b32_e32 v32, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v31, v32, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v15
|
|
; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
|
|
; VI-NEXT: v_bfe_u32 v32, v31, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v31
|
|
; VI-NEXT: v_add_u32_e32 v32, vcc, s6, v32
|
|
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; VI-NEXT: v_or_b32_e32 v33, 0x400000, v31
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
|
|
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc
|
|
; VI-NEXT: v_bfe_u32 v32, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v15
|
|
; VI-NEXT: v_add_u32_e32 v32, vcc, s6, v32
|
|
; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v32, v33, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_alignbit_b32 v15, v15, v31, 16
|
|
; VI-NEXT: v_alignbit_b32 v14, v14, v30, 16
|
|
; VI-NEXT: v_alignbit_b32 v13, v13, v29, 16
|
|
; VI-NEXT: v_alignbit_b32 v12, v12, v28, 16
|
|
; VI-NEXT: v_alignbit_b32 v11, v11, v27, 16
|
|
; VI-NEXT: v_alignbit_b32 v10, v10, v26, 16
|
|
; VI-NEXT: v_alignbit_b32 v9, v9, v25, 16
|
|
; VI-NEXT: v_alignbit_b32 v8, v8, v24, 16
|
|
; VI-NEXT: v_alignbit_b32 v7, v7, v23, 16
|
|
; VI-NEXT: v_alignbit_b32 v6, v6, v22, 16
|
|
; VI-NEXT: v_alignbit_b32 v5, v5, v21, 16
|
|
; VI-NEXT: v_alignbit_b32 v4, v4, v20, 16
|
|
; VI-NEXT: v_alignbit_b32 v3, v3, v19, 16
|
|
; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16
|
|
; VI-NEXT: v_alignbit_b32 v1, v1, v17, 16
|
|
; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
|
|
; VI-NEXT: .LBB94_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v32i16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB94_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v0, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX9-NEXT: v_add3_u32 v18, v18, v17, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v1, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v18, v18, v1, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; GFX9-NEXT: v_bfe_u32 v19, v18, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX9-NEXT: v_add3_u32 v19, v19, v18, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v19, v2, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v19, v19, v2, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
|
|
; GFX9-NEXT: v_bfe_u32 v20, v19, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX9-NEXT: v_add3_u32 v20, v20, v19, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v21, 0x400000, v19
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v20, v3, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v20, v20, v3, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v21, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; GFX9-NEXT: v_bfe_u32 v21, v20, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX9-NEXT: v_add3_u32 v21, v21, v20, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v22, 0x400000, v20
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v21, v4, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v21, v21, v4, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v22, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
|
|
; GFX9-NEXT: v_bfe_u32 v22, v21, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX9-NEXT: v_add3_u32 v22, v22, v21, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v23, 0x400000, v21
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v22, v5, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v22, v22, v5, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v23, 0x400000, v5
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v5, v22, v23, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; GFX9-NEXT: v_bfe_u32 v23, v22, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX9-NEXT: v_add3_u32 v23, v23, v22, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v23, v6, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v23, v23, v6, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v24, 0x400000, v6
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v6, v23, v24, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; GFX9-NEXT: v_bfe_u32 v24, v23, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX9-NEXT: v_add3_u32 v24, v24, v23, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v25, 0x400000, v23
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v24, v7, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v24, v24, v7, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v25, 0x400000, v7
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v7, v24, v25, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
|
|
; GFX9-NEXT: v_bfe_u32 v25, v24, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX9-NEXT: v_add3_u32 v25, v25, v24, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v26, 0x400000, v24
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v25, v8, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v25, v25, v8, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v26, 0x400000, v8
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v8, v25, v26, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
|
|
; GFX9-NEXT: v_bfe_u32 v26, v25, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX9-NEXT: v_add3_u32 v26, v26, v25, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v27, 0x400000, v25
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v26, v9, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v26, v26, v9, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v27, 0x400000, v9
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v9, v26, v27, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
|
|
; GFX9-NEXT: v_bfe_u32 v27, v26, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX9-NEXT: v_add3_u32 v27, v27, v26, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v28, 0x400000, v26
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v27, v10, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v27, v27, v10, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v28, 0x400000, v10
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v10, v27, v28, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
|
|
; GFX9-NEXT: v_bfe_u32 v28, v27, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX9-NEXT: v_add3_u32 v28, v28, v27, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v29, 0x400000, v27
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v28, v11, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v28, v28, v11, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v29, 0x400000, v11
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
|
|
; GFX9-NEXT: v_bfe_u32 v29, v28, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX9-NEXT: v_add3_u32 v29, v29, v28, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v30, 0x400000, v28
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v29, v12, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v29, v29, v12, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v30, 0x400000, v12
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v12, v29, v30, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
|
|
; GFX9-NEXT: v_bfe_u32 v30, v29, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX9-NEXT: v_add3_u32 v30, v30, v29, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v31, 0x400000, v29
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v30, v13, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v30, v30, v13, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v31, 0x400000, v13
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v13, v30, v31, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
|
|
; GFX9-NEXT: v_bfe_u32 v31, v30, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX9-NEXT: v_add3_u32 v31, v31, v30, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v32, 0x400000, v30
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v30, v31, v32, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v31, v14, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v31, v31, v14, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v32, 0x400000, v14
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v14, v31, v32, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
|
|
; GFX9-NEXT: v_bfe_u32 v32, v31, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX9-NEXT: v_add3_u32 v32, v32, v31, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v33, 0x400000, v31
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v32, v15, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v32, v32, v15, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v33, 0x400000, v15
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v15, v32, v33, vcc
|
|
; GFX9-NEXT: s_mov_b32 s6, 0x7060302
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v31, s6
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v30, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v29, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v28, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v27, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v10, v26, s6
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v25, s6
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v24, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v23, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v6, v22, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v4, v20, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v19, s6
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v18, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v0, v0, v16, s6
|
|
; GFX9-NEXT: .LBB94_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v32i16:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB94_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v22, v17, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v19, v20, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v18, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v0, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v21, v23, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v20, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v22, v24, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v19, v21, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v22, v18, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v17.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v19, v21, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v22, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v22, v23, v20, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v19, v21, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v21, 0x40c00000, v24
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v22, v23, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v21, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v22 :: v_dual_cndmask_b32 v3, v19, v23
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v24, v21, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v22, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v20.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v24, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v19, v23, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v24, v25, v22, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v22
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v21, v23, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v26
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v19.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v24, v25, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v23, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_cndmask_b32 v5, v21, v25
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v26, v23, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v23
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v24, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v23, v26, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v21, v25, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v26, v27, v24, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v23, v25, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v25, 0x40c00000, v28
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v21.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v23, v23, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v26, v27, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v25, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_cndmask_b32 v7, v23, v27
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v23, v28, v25, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v25
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v26, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v25, v28, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v23, v27, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v28, v29, v26, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v26
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v25, v27, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v30
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v23.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v22.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v25, v25, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v28, v29, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v27, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_cndmask_b32 v9, v25, v29
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v25, v30, v27, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v27
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v30, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v28, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v27, v30, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v25, v29, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v30, v31, v28, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v28
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v27, v29, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v25.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v24.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v27, v27, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v30, v31, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v29, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v27, v30, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v27, 0x40c00000, v31
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v30, v32, v29, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v29
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v27, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v34, 0x400000, v27
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v30, v32, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v33, v27, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v33, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v30, v31, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v33
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v31, v35, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v29.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v32, v34, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v33, v30, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v26.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v31, v32, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v34
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v33, v30, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, 0x400000, v30
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v35, v31, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v27.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v33, v34, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v34, v35, v31, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v31
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v34, v35, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v32, v32, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v33, v36, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v30.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v32, v37, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v31.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v28.h
|
|
; GFX11-TRUE16-NEXT: .LBB94_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v32i16:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB94_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_add_f32 v6, 0x40c00000, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_lshlrev_b32 v27, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v22, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_add_f32 v27, 0x40c00000, v27
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_lshlrev_b32 v29, 16, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v31, 16, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v20, v23 :: v_dual_lshlrev_b32 v23, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v21, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v1, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v31, 0x40c00000, v31
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v19, v20 :: v_dual_add_f32 v18, 0x40c00000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v2, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v7, 0xffff0000, v7
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v2, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v22, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v22
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v23, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v21, v3, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v22, v23, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v23
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v19, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v4, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v23, v24, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v25, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v20, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v5, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v22, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v24, v25, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v25
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v26, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v21, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v23, v24, v6, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v24, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v23, v25, v26, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v26
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v27, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v22, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v24, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v25, v7, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v26, v27, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v27
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v28, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v23, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v25, v26, v8, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v25, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v25, v27, v28, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v28
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v29, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v24, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v26, v27, v9, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v26, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v26, v28, v29, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v29
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v30, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v25, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v27, v28, v10, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v27, v28, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v27, v29, v30, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v30
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v28 :: v_dual_lshlrev_b32 v28, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v31, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v34, v12, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v29, v29, v11, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v33, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v28, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v28
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v31, v33, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v35, v28, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v26, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v35 :: v_dual_cndmask_b32 v28, v34, v36
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v37, v13, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v31, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v34, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v34
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v35, v37, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v14, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v39, v34, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v37, v38, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v15, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v31, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v39, v48, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v35, v49, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v34, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v33, v36, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v30, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v28, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v29, v32, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v27, 0x7060302
|
|
; GFX11-FAKE16-NEXT: .LBB94_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define inreg <32 x i16> @bitcast_v32bf16_to_v32i16_scalar(<32 x bfloat> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v32i16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v0
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s5, s29, 16
|
|
; SI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s28, 16
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s9, s27, 16
|
|
; SI-NEXT: s_and_b32 s10, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s26, 16
|
|
; SI-NEXT: s_and_b32 s12, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s25, 16
|
|
; SI-NEXT: s_and_b32 s14, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s24, 16
|
|
; SI-NEXT: s_and_b32 s24, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_and_b32 s25, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: s_and_b32 s26, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s27, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s28, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: s_and_b32 s29, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s40, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s41, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s43, s42, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s42, 16
|
|
; SI-NEXT: s_and_b32 s45, s44, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s46, 0
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v63, 1.0, s16
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s41
|
|
; SI-NEXT: v_mul_f32_e64 v50, 1.0, s17
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s40
|
|
; SI-NEXT: v_mul_f32_e64 v62, 1.0, s18
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s29
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s19
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s28
|
|
; SI-NEXT: v_mul_f32_e64 v61, 1.0, s20
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s27
|
|
; SI-NEXT: v_mul_f32_e64 v37, 1.0, s21
|
|
; SI-NEXT: v_mul_f32_e64 v22, 1.0, s26
|
|
; SI-NEXT: v_mul_f32_e64 v60, 1.0, s22
|
|
; SI-NEXT: v_mul_f32_e64 v59, 1.0, s25
|
|
; SI-NEXT: v_mul_f32_e64 v34, 1.0, s23
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s24
|
|
; SI-NEXT: v_mul_f32_e64 v58, 1.0, s15
|
|
; SI-NEXT: v_mul_f32_e64 v57, 1.0, s14
|
|
; SI-NEXT: v_mul_f32_e64 v48, 1.0, s13
|
|
; SI-NEXT: v_mul_f32_e64 v20, 1.0, s12
|
|
; SI-NEXT: v_mul_f32_e64 v56, 1.0, s11
|
|
; SI-NEXT: v_mul_f32_e64 v47, 1.0, s10
|
|
; SI-NEXT: v_mul_f32_e64 v32, 1.0, s9
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s8
|
|
; SI-NEXT: v_mul_f32_e64 v46, 1.0, s7
|
|
; SI-NEXT: v_mul_f32_e64 v45, 1.0, s6
|
|
; SI-NEXT: v_mul_f32_e64 v30, 1.0, s5
|
|
; SI-NEXT: v_mul_f32_e64 v18, 1.0, s4
|
|
; SI-NEXT: v_mul_f32_e64 v44, 1.0, s44
|
|
; SI-NEXT: v_mul_f32_e64 v28, 1.0, s45
|
|
; SI-NEXT: v_mul_f32_e64 v55, 1.0, s42
|
|
; SI-NEXT: v_mul_f32_e64 v16, 1.0, s43
|
|
; SI-NEXT: s_cbranch_scc0 .LBB95_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v63
|
|
; SI-NEXT: v_lshrrev_b32_e32 v52, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v62
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v61
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v60
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v59
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v58
|
|
; SI-NEXT: v_lshrrev_b32_e32 v40, 16, v57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v56
|
|
; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v47
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v46
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v45
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v18
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v44
|
|
; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v48
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v55
|
|
; SI-NEXT: s_cbranch_execnz .LBB95_3
|
|
; SI-NEXT: .LBB95_2: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v63
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v6
|
|
; SI-NEXT: v_add_f32_e32 v39, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v39
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v62
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v61
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[6:7], 16
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v14
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v1
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v59
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v60
|
|
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v21
|
|
; SI-NEXT: v_lshr_b64 v[23:24], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v57
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v58
|
|
; SI-NEXT: v_add_f32_e32 v38, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v38
|
|
; SI-NEXT: v_lshr_b64 v[24:25], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v47
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v56
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v10
|
|
; SI-NEXT: v_lshr_b64 v[25:26], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v45
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v46
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v11
|
|
; SI-NEXT: v_lshr_b64 v[26:27], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v28
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v44
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v14
|
|
; SI-NEXT: v_lshr_b64 v[27:28], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v55
|
|
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v30
|
|
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v18
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v32
|
|
; SI-NEXT: v_add_f32_e32 v32, 0x40c00000, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v12
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v48
|
|
; SI-NEXT: v_add_f32_e32 v35, 0x40c00000, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v20
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v6
|
|
; SI-NEXT: v_lshr_b64 v[19:20], v[35:36], 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v34
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v2
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_add_f32_e32 v34, 0x40c00000, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v8
|
|
; SI-NEXT: v_add_f32_e32 v48, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v0
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[48:49], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v50
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[34:35], 16
|
|
; SI-NEXT: v_add_f32_e32 v50, 0x40c00000, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[28:29], 16
|
|
; SI-NEXT: v_lshr_b64 v[17:18], v[30:31], 16
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v37, 0x40c00000, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v11
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[32:33], 16
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v38
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v3
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[50:51], 16
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v39
|
|
; SI-NEXT: v_lshr_b64 v[39:40], v[6:7], 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v8
|
|
; SI-NEXT: v_lshr_b64 v[40:41], v[18:19], 16
|
|
; SI-NEXT: v_lshr_b64 v[21:22], v[37:38], 16
|
|
; SI-NEXT: v_lshr_b64 v[52:53], v[2:3], 16
|
|
; SI-NEXT: v_lshr_b64 v[41:42], v[10:11], 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; SI-NEXT: v_lshr_b64 v[53:54], v[0:1], 16
|
|
; SI-NEXT: v_lshr_b64 v[42:43], v[16:17], 16
|
|
; SI-NEXT: v_lshr_b64 v[54:55], v[20:21], 16
|
|
; SI-NEXT: v_lshr_b64 v[43:44], v[14:15], 16
|
|
; SI-NEXT: .LBB95_3: ; %end
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v52
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v53
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v49
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v40
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v41
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v43
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v54
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v8
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v35
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v24
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v36
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v25
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v33
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v26
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v31
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v27
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB95_4:
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: s_branch .LBB95_2
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v32i16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v20, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v20, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB95_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB95_4
|
|
; VI-NEXT: .LBB95_2: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
|
|
; VI-NEXT: s_lshl_b32 s4, s26, 16
|
|
; VI-NEXT: v_add_f32_e32 v4, s4, v16
|
|
; VI-NEXT: s_lshl_b32 s4, s28, 16
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
|
|
; VI-NEXT: v_add_f32_e32 v1, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s30, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; VI-NEXT: v_add_f32_e32 v2, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
|
|
; VI-NEXT: v_add_f32_e32 v3, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: s_and_b32 s6, s26, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[2:3]
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v4, 16, 1
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s24, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s24, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s22, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s22, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s20, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s20, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s18, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s18, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
|
|
; VI-NEXT: s_and_b32 s7, s16, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v5, s7, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v5
|
|
; VI-NEXT: s_lshl_b32 s6, s16, 16
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
; VI-NEXT: v_bfe_u32 v0, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v3
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s17, 0xffff0000
|
|
; VI-NEXT: v_add_f32_e32 v3, s5, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
|
|
; VI-NEXT: s_lshl_b32 s4, s17, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: s_and_b32 s5, s19, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s5, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v5, v7, vcc
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: s_lshl_b32 s4, s19, 16
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
|
|
; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: s_and_b32 s5, s21, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v5, s5, v16
|
|
; VI-NEXT: v_mov_b32_e32 v1, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v7, v9, vcc
|
|
; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
|
|
; VI-NEXT: s_lshl_b32 s4, s21, 16
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_add_f32_e32 v5, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
|
|
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: s_and_b32 s5, s23, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v7, s5, v16
|
|
; VI-NEXT: v_mov_b32_e32 v3, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v9, v11, vcc
|
|
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
|
|
; VI-NEXT: s_lshl_b32 s4, s23, 16
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_add_f32_e32 v7, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
|
|
; VI-NEXT: v_bfe_u32 v11, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v7
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: s_and_b32 s5, s25, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v9, s5, v16
|
|
; VI-NEXT: v_mov_b32_e32 v5, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v11, v13, vcc
|
|
; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
|
|
; VI-NEXT: s_lshl_b32 s4, s25, 16
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_add_f32_e32 v9, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
|
|
; VI-NEXT: v_bfe_u32 v13, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v9
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: s_and_b32 s5, s27, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v11, s5, v16
|
|
; VI-NEXT: v_mov_b32_e32 v7, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v13, v15, vcc
|
|
; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
|
|
; VI-NEXT: s_lshl_b32 s4, s27, 16
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_add_f32_e32 v11, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
|
|
; VI-NEXT: v_bfe_u32 v15, v11, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v11
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: s_and_b32 s5, s29, 0xffff0000
|
|
; VI-NEXT: v_mov_b32_e32 v9, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s5, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v15, v17, vcc
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: s_lshl_b32 s4, s29, 16
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v11, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: s_lshl_b32 s4, s31, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
|
|
; VI-NEXT: v_add_f32_e32 v15, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
|
|
; VI-NEXT: v_mov_b32_e32 v13, v17
|
|
; VI-NEXT: s_branch .LBB95_5
|
|
; VI-NEXT: .LBB95_3:
|
|
; VI-NEXT: s_branch .LBB95_2
|
|
; VI-NEXT: .LBB95_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB95_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v20, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v20, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v32i16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB95_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB95_4
|
|
; GFX9-NEXT: .LBB95_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000
|
|
; GFX9-NEXT: s_and_b32 s5, s30, 0xffff0000
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s5, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s5, s30, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s5, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: s_and_b32 s5, s31, 0xffff0000
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v3, s5, v0
|
|
; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: s_lshl_b32 s5, s31, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v4, s5, v0
|
|
; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
|
|
; GFX9-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_and_or_b32 v14, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_and_or_b32 v15, v3, v16, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s29, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v13, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s28, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v12, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s27, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v11, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s26, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v10, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s25, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v9, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s24, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v8, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s23, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v7, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s22, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v6, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s21, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v5, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s20, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v4, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s19, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v3, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s18, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v17, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_and_or_b32 v2, v1, v16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s17, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; GFX9-NEXT: v_and_or_b32 v1, v1, v16, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: s_lshl_b32 s4, s16, 16
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v0, s4, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v0, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v0
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v0, v18, v19, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX9-NEXT: v_and_or_b32 v0, v17, v16, v0
|
|
; GFX9-NEXT: s_branch .LBB95_5
|
|
; GFX9-NEXT: .LBB95_3:
|
|
; GFX9-NEXT: s_branch .LBB95_2
|
|
; GFX9-NEXT: .LBB95_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB95_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v20, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v32i16_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB95_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB95_4
|
|
; GFX11-TRUE16-NEXT: .LBB95_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s12, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s12, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s25, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s13, 16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v2
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s14, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v3, v7 :: v_dual_add_nc_u32 v5, 0x7fff, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v5, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v7
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s15, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v2, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v2, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v3, v7 :: v_dual_add_nc_u32 v5, v5, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s16, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v11
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v4, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v4, v5, v9 :: v_dual_add_nc_u32 v5, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v12
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v5, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v6, v11 :: v_dual_add_nc_u32 v6, 0x7fff, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v13
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v6, v9
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v10
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v6, v7, v11 :: v_dual_add_nc_u32 v7, 0x7fff, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v14
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v7, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v15
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v8, v13 :: v_dual_add_nc_u32 v8, 0x7fff, v11
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v8, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v8, v11
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v9, v13 :: v_dual_add_nc_u32 v9, 0x7fff, v14
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v24, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v13, v24
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v9, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v25, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v24
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v26.h
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v10, v15 :: v_dual_add_nc_u32 v10, 0x7fff, v13
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v25
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v10, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v25
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, v10, v13
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v28, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v24.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v15, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v27
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v27, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, v25, v28
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v12, v15, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v27, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v25
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v28
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v29, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v12, v27
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v27
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v13, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v25, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v31, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v13, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v25
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v14, v25
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v31, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v12, v29, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, v27, v31
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v28.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v29, v13, v29, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s26, 16
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v30.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v29.h
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v14, v32 :: v_dual_add_nc_u32 v14, 0x7fff, v27
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v27, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, 0x400000, v31
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v27, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v33, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v31, v14, v32, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v34, v27
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v27
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v36, v33
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, v25, v15
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v35, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v33
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v14, v37, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x7fff, v25
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, v32, v35
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v35
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v34, v38, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v31.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x7fff, v32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v17.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v25, v36, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v27.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v32, v37, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v33.h
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB95_3:
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB95_2
|
|
; GFX11-TRUE16-NEXT: .LBB95_4:
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v32i16_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB95_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB95_4
|
|
; GFX11-FAKE16-NEXT: .LBB95_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s12, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s12, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s13, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s2, s14, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s27, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v3, 0x40c00000, s2
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v2, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v9, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v3
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s15, 16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v5, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v8, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v6, v8 :: v_dual_add_nc_u32 v7, v9, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v11
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v7, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v5, v7, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v7, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v8, v10 :: v_dual_add_nc_u32 v8, 0x7fff, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v12, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v13
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v10, v11 :: v_dual_add_nc_u32 v10, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v14, v9
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v14, v15
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v10, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v24, v11, v12 :: v_dual_add_nc_u32 v9, 0x7fff, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v14, v10
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v23, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v23
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v13
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v25, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v12, v14, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v15, v11
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v23
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v25
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v10, v15, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v25
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v12, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v28, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v27, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v11, v13 :: v_dual_add_nc_u32 v12, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v27, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s25, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v25, v12, v28 :: v_dual_add_nc_u32 v12, v29, v15
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v27
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v27
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v28, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v29 :: v_dual_add_nc_u32 v15, v30, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v27, v13, v31, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v32, v28
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v28
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v29, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v15, v30 :: v_dual_add_nc_u32 v13, 0x7fff, v13
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s26, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v32, v29
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v30, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v31, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v31, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s27, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v33, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v32, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v30, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v32, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v34, v30
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, v35, v31
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v30
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v32
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, v37, v32
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v35, 0x7fff, v35
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, v28, v33
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v37, 0x7fff, v37
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v29
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v35, v39, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v28
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v33
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v23
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v31
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v34, v48, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v22
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v30
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v37, v49, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v7, 0xffff0000, v7, v22
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v15, v36, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v15, 0xffff0000, v32, v31
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v28, v28, v38, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v12, 0xffff0000, v27, v31
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v11, 0xffff0000, v25, v32
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v14, 0xffff0000, v28, v30
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v9, 0xffff0000, v26, v23
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v8, 0xffff0000, v24, v25
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v6, 0xffff0000, v5, v27
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v5, 0xffff0000, v21, v28
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v13, 0xffff0000, v13, v29
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v10, 0xffff0000, v10, v33
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v4, 0xffff0000, v19, v20
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v3, 0xffff0000, v18, v21
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v2, 0xffff0000, v17, v22
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0xffff0000, v16, v23
|
|
; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xffff0000, v0, v24
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB95_3:
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB95_2
|
|
; GFX11-FAKE16-NEXT: .LBB95_4:
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v64i8:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v1
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: s_waitcnt expcnt(4)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 16, v31
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 16, v44
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v61, 16, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v60, 16, v35
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v63, 16, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 16, v18
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; kill: killed $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB96_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v58, v1, v59
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v57, v1, v56
|
|
; SI-NEXT: v_alignbit_b32 v1, v57, v58, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v57, v58, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v51, v1, v61
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v39, v1, v60
|
|
; SI-NEXT: v_alignbit_b32 v1, v39, v51, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v39, v51, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v34, v1, v63
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
|
|
; SI-NEXT: v_or_b32_e32 v33, v1, v62
|
|
; SI-NEXT: v_alignbit_b32 v1, v33, v34, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v33, v34, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v33, v34, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
|
|
; SI-NEXT: v_or_b32_e32 v32, v1, v37
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v31, v1, v36
|
|
; SI-NEXT: v_alignbit_b32 v1, v31, v32, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v31, v32, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v31, v32, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
|
|
; SI-NEXT: v_or_b32_e32 v29, v1, v48
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v28, v1, v38
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v29, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v29, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v29, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
|
|
; SI-NEXT: v_or_b32_e32 v26, v1, v50
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v25, v1, v49
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v26, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v26, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v26, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
|
|
; SI-NEXT: v_or_b32_e32 v24, v1, v53
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v22, v1, v52
|
|
; SI-NEXT: v_alignbit_b32 v1, v22, v24, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v22, v24, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v22, v24, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
|
|
; SI-NEXT: v_or_b32_e32 v21, v1, v55
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
|
|
; SI-NEXT: v_or_b32_e32 v17, v1, v54
|
|
; SI-NEXT: v_alignbit_b32 v1, v17, v21, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v17, v21, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v17, v21, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v33
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v31
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v28
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v25
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v17
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_bfe_u32 v1, v27, 8, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_bfe_u32 v1, v23, 8, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_bfe_u32 v1, v20, 8, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_bfe_u32 v1, v19, 8, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_bfe_u32 v1, v18, 8, 8
|
|
; SI-NEXT: v_alignbit_b32 v41, v57, v58, 8
|
|
; SI-NEXT: v_alignbit_b32 v40, v39, v51, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v46, 8, v57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v43, 8, v39
|
|
; SI-NEXT: v_bfe_u32 v47, v44, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v45, v35, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v42, v30, 8, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: .LBB96_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB96_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_mov_b32 s6, 0x30000
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3
|
|
; SI-NEXT: v_or_b32_e32 v1, v59, v1
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_add_i32_e32 v58, vcc, s6, v1
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v2
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_or_b32_e32 v3, v61, v3
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_add_i32_e32 v51, vcc, s6, v3
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v4
|
|
; SI-NEXT: v_or_b32_e32 v1, v56, v1
|
|
; SI-NEXT: v_or_b32_e32 v5, v63, v5
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_add_i32_e32 v57, vcc, s6, v1
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_add_i32_e32 v34, vcc, s6, v5
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v60, v3
|
|
; SI-NEXT: v_alignbit_b32 v1, v57, v58, 24
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_add_i32_e32 v39, vcc, s6, v3
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v57, v58, 16
|
|
; SI-NEXT: v_or_b32_e32 v7, v37, v7
|
|
; SI-NEXT: v_or_b32_e32 v5, v62, v5
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v39, v51, 24
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_add_i32_e32 v32, vcc, s6, v7
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v8
|
|
; SI-NEXT: v_add_i32_e32 v33, vcc, s6, v5
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v39, v51, 16
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v33, v34, 24
|
|
; SI-NEXT: v_or_b32_e32 v9, v48, v9
|
|
; SI-NEXT: v_or_b32_e32 v7, v36, v7
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v33, v34, 16
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_add_i32_e32 v29, vcc, s6, v9
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v10
|
|
; SI-NEXT: v_add_i32_e32 v31, vcc, s6, v7
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v33, v34, 8
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v31, v32, 24
|
|
; SI-NEXT: v_or_b32_e32 v11, v50, v11
|
|
; SI-NEXT: v_or_b32_e32 v9, v38, v9
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v31, v32, 16
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_add_i32_e32 v26, vcc, s6, v11
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
|
|
; SI-NEXT: v_add_i32_e32 v28, vcc, s6, v9
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v31, v32, 8
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v29, 24
|
|
; SI-NEXT: v_or_b32_e32 v13, v53, v13
|
|
; SI-NEXT: v_or_b32_e32 v11, v49, v11
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v29, 16
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_add_i32_e32 v24, vcc, s6, v13
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v14
|
|
; SI-NEXT: v_add_i32_e32 v25, vcc, s6, v11
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v29, 8
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v26, 24
|
|
; SI-NEXT: v_or_b32_e32 v15, v55, v15
|
|
; SI-NEXT: v_or_b32_e32 v13, v52, v13
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v26, 16
|
|
; SI-NEXT: v_add_i32_e32 v21, vcc, 0x30000, v15
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v16
|
|
; SI-NEXT: v_add_i32_e32 v22, vcc, s6, v13
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v26, 8
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v22, v24, 24
|
|
; SI-NEXT: v_or_b32_e32 v15, v54, v15
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v22, v24, 16
|
|
; SI-NEXT: v_add_i32_e32 v17, vcc, s6, v15
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v22, v24, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v17, v21, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v17, v21, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v17, v21, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v33
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v31
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v31
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v28
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v28
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v25
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v25
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v22
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v22
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 24, v17
|
|
; SI-NEXT: v_alignbit_b32 v41, v57, v58, 8
|
|
; SI-NEXT: v_alignbit_b32 v40, v39, v51, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 24, v57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v46, 8, v57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 24, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v43, 8, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 24, v33
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 16, v33
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v22
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v17
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v17
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: .LBB96_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v41
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v57
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v46
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v44
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v47
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v40
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v35
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v45
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v42
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v31
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v29
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v28
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v26
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v25
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v24
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v22
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v21
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v64i8:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: v_lshrrev_b32_e32 v26, 16, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v1
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; kill: killed $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB96_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v4
|
|
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v15
|
|
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v14
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[13:14]
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v14
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v13
|
|
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v12
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v11
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v10
|
|
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v7
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v9
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v6
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 24, v16
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 24, v8
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 8, v5
|
|
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 24, v12
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v6
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v1
|
|
; VI-NEXT: v_mov_b32_e32 v25, v50
|
|
; VI-NEXT: v_mov_b32_e32 v55, v1
|
|
; VI-NEXT: v_mov_b32_e32 v53, v2
|
|
; VI-NEXT: v_mov_b32_e32 v56, v3
|
|
; VI-NEXT: v_mov_b32_e32 v46, v4
|
|
; VI-NEXT: v_mov_b32_e32 v61, v5
|
|
; VI-NEXT: v_mov_b32_e32 v59, v6
|
|
; VI-NEXT: v_mov_b32_e32 v52, v7
|
|
; VI-NEXT: v_mov_b32_e32 v50, v8
|
|
; VI-NEXT: v_mov_b32_e32 v43, v9
|
|
; VI-NEXT: v_mov_b32_e32 v41, v10
|
|
; VI-NEXT: v_mov_b32_e32 v47, v11
|
|
; VI-NEXT: v_mov_b32_e32 v45, v12
|
|
; VI-NEXT: v_mov_b32_e32 v60, v13
|
|
; VI-NEXT: v_mov_b32_e32 v58, v14
|
|
; VI-NEXT: v_mov_b32_e32 v51, v15
|
|
; VI-NEXT: v_mov_b32_e32 v62, v16
|
|
; VI-NEXT: ; implicit-def: $vgpr1
|
|
; VI-NEXT: ; implicit-def: $vgpr3
|
|
; VI-NEXT: ; implicit-def: $vgpr5
|
|
; VI-NEXT: ; implicit-def: $vgpr7
|
|
; VI-NEXT: ; implicit-def: $vgpr9
|
|
; VI-NEXT: ; implicit-def: $vgpr11
|
|
; VI-NEXT: ; implicit-def: $vgpr13
|
|
; VI-NEXT: ; implicit-def: $vgpr15
|
|
; VI-NEXT: .LBB96_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB96_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v17, 3
|
|
; VI-NEXT: v_add_u16_sdwa v28, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v33, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v26, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v29, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v30, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v35, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v45, 3, v12
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
|
|
; VI-NEXT: v_add_u16_e32 v47, 3, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
|
|
; VI-NEXT: v_add_u16_e32 v62, 3, v16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v26
|
|
; VI-NEXT: v_add_u16_e32 v51, 3, v15
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v29
|
|
; VI-NEXT: v_add_u16_sdwa v32, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v37, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v41, 3, v10
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v30
|
|
; VI-NEXT: v_add_u16_e32 v43, 3, v9
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
|
|
; VI-NEXT: v_or_b32_e32 v12, v45, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v47, v11
|
|
; VI-NEXT: v_or_b32_e32 v16, v62, v16
|
|
; VI-NEXT: v_or_b32_e32 v15, v51, v15
|
|
; VI-NEXT: v_add_u16_sdwa v38, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v49, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v36, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v48, v3, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v34, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v39, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v50, 3, v8
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
|
|
; VI-NEXT: v_add_u16_e32 v52, 3, v7
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
|
|
; VI-NEXT: v_or_b32_e32 v10, v41, v10
|
|
; VI-NEXT: v_or_b32_e32 v9, v43, v9
|
|
; VI-NEXT: v_add_u16_sdwa v27, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v31, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_add_u16_e32 v59, 3, v6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
|
|
; VI-NEXT: v_add_u16_e32 v61, 3, v5
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
|
|
; VI-NEXT: v_or_b32_e32 v8, v50, v8
|
|
; VI-NEXT: v_or_b32_e32 v7, v52, v7
|
|
; VI-NEXT: v_add_u16_e32 v58, 3, v14
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v27
|
|
; VI-NEXT: v_add_u16_e32 v60, 3, v13
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; VI-NEXT: v_add_u16_e32 v46, 3, v4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
|
|
; VI-NEXT: v_add_u16_e32 v56, 3, v3
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
|
|
; VI-NEXT: v_or_b32_e32 v6, v59, v6
|
|
; VI-NEXT: v_or_b32_e32 v5, v61, v5
|
|
; VI-NEXT: v_or_b32_e32 v14, v58, v14
|
|
; VI-NEXT: v_or_b32_e32 v13, v60, v13
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; VI-NEXT: v_add_u16_e32 v53, 3, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v38
|
|
; VI-NEXT: v_add_u16_e32 v55, 3, v1
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v49
|
|
; VI-NEXT: v_or_b32_e32 v4, v46, v4
|
|
; VI-NEXT: v_or_b32_e32 v3, v56, v3
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; VI-NEXT: v_or_b32_e32 v2, v53, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v55, v1
|
|
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v1
|
|
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; VI-NEXT: v_bfe_u32 v1, v27, 8, 8
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v6
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_bfe_u32 v1, v30, 8, 8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v16, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v8
|
|
; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v2
|
|
; VI-NEXT: v_bfe_u32 v25, v26, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v54, v28, 8, 8
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_bfe_u32 v1, v32, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v40, v34, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v18, v36, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v63, v38, 8, 8
|
|
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; VI-NEXT: .LBB96_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v1, v49, v24, s4
|
|
; VI-NEXT: v_perm_b32 v2, v55, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_perm_b32 v2, v38, v63, s4
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v53, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v48, v23, s4
|
|
; VI-NEXT: v_perm_b32 v2, v56, v42, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v46, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v39, v22, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v61, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v34, v40, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v59, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v37, v21, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v52, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v1, v50, v17, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v32, v2, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v35, v20, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v43, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v1, v41, v1, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v30, v2, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v33, v19, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v47, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v28, v54, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v45, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v2, v31, v2, s4
|
|
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v1, v58, v1, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v27, v2, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v2, v29, v2, s4
|
|
; VI-NEXT: v_perm_b32 v1, v51, v1, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v26, v25, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v62, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v64i8:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB96_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v16
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, v22
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: .LBB96_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB96_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: .LBB96_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v22, v30, v24, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v22, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v21, v62, v21, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v61, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v21, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v43, v23, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v54, v20, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v27, v25, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32i16_to_v64i8:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB96_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB96_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB96_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
|
|
; GFX11-TRUE16-NEXT: s_clause 0x3
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32i16_to_v64i8:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB96_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB96_2: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB96_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v16, v16, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v15, v15, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v14, v14, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v13, v13, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v12, v12, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v11, v11, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v10, v10, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v9, v9, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB96_4: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
|
|
; GFX11-FAKE16-NEXT: s_clause 0x3
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32i16_to_v64i8_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_writelane_b32 v4, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v4, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v4, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v4, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v4, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v4, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v4, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v4, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v4, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v4, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v4, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v4, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v4, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v4, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v4, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v4, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v4, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v4, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v4, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v4, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v4, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v4, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v4, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v4, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v4, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v4, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v4, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v4, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v4, s86, 28
|
|
; SI-NEXT: v_writelane_b32 v4, s87, 29
|
|
; SI-NEXT: v_writelane_b32 v4, s96, 30
|
|
; SI-NEXT: v_writelane_b32 v4, s97, 31
|
|
; SI-NEXT: v_writelane_b32 v4, s98, 32
|
|
; SI-NEXT: v_writelane_b32 v4, s99, 33
|
|
; SI-NEXT: v_writelane_b32 v4, s30, 34
|
|
; SI-NEXT: v_writelane_b32 v4, s31, 35
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v1
|
|
; SI-NEXT: s_lshr_b32 s68, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s44, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s70, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s97, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s71, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s96, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s80, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s87, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s81, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s86, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s82, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s85, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s83, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s84, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s69, s46, 16
|
|
; SI-NEXT: s_lshr_b32 s56, s58, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
|
|
; SI-NEXT: s_cbranch_scc0 .LBB97_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s84, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s83, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 24
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v5, s4, 2
|
|
; SI-NEXT: v_writelane_b32 v5, s5, 3
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 16
|
|
; SI-NEXT: v_writelane_b32 v5, s4, 0
|
|
; SI-NEXT: v_writelane_b32 v5, s5, 1
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s85, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s82, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[40:41], 24
|
|
; SI-NEXT: v_writelane_b32 v5, s4, 4
|
|
; SI-NEXT: v_writelane_b32 v5, s5, 5
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s86, 16
|
|
; SI-NEXT: s_or_b32 s12, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s81, 16
|
|
; SI-NEXT: s_or_b32 s13, s4, s5
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[12:13], 24
|
|
; SI-NEXT: v_writelane_b32 v5, s4, 6
|
|
; SI-NEXT: v_writelane_b32 v5, s5, 7
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s87, 16
|
|
; SI-NEXT: s_or_b32 s8, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s80, 16
|
|
; SI-NEXT: s_or_b32 s9, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s96, 16
|
|
; SI-NEXT: s_or_b32 s14, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s71, 16
|
|
; SI-NEXT: s_or_b32 s15, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s97, 16
|
|
; SI-NEXT: s_or_b32 s10, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s70, 16
|
|
; SI-NEXT: s_or_b32 s11, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s44, 16
|
|
; SI-NEXT: s_or_b32 s6, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s68, 16
|
|
; SI-NEXT: s_or_b32 s7, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s58, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s46, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s45, s69, 16
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[42:43], 8
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 8
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[12:13], 8
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[8:9], 24
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[8:9], 16
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[8:9], 8
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[14:15], 24
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[14:15], 16
|
|
; SI-NEXT: s_or_b32 s5, s5, s45
|
|
; SI-NEXT: s_lshr_b32 s98, s43, 8
|
|
; SI-NEXT: s_lshr_b32 s93, s41, 8
|
|
; SI-NEXT: s_lshr_b32 s89, s13, 8
|
|
; SI-NEXT: s_lshr_b32 s77, s9, 8
|
|
; SI-NEXT: s_lshr_b32 s73, s15, 8
|
|
; SI-NEXT: s_lshr_b32 s61, s11, 8
|
|
; SI-NEXT: s_lshr_b32 s57, s7, 8
|
|
; SI-NEXT: s_lshr_b32 s45, s5, 8
|
|
; SI-NEXT: s_bfe_u32 s99, s83, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s95, s82, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s91, s81, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s79, s80, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s75, s71, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s63, s70, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s59, s68, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s47, s69, 0x80008
|
|
; SI-NEXT: s_lshr_b64 s[66:67], s[14:15], 8
|
|
; SI-NEXT: s_lshr_b64 s[52:53], s[10:11], 24
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b64 s[64:65], s[10:11], 8
|
|
; SI-NEXT: s_lshr_b64 s[38:39], s[6:7], 24
|
|
; SI-NEXT: s_lshr_b64 s[48:49], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[50:51], s[6:7], 8
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[4:5], 8
|
|
; SI-NEXT: s_cbranch_execnz .LBB97_3
|
|
; SI-NEXT: .LBB97_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s58, s58, 3
|
|
; SI-NEXT: s_and_b32 s4, s58, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s56, 16
|
|
; SI-NEXT: s_add_i32 s46, s46, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s46, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s6, s69, 16
|
|
; SI-NEXT: s_add_i32 s28, s28, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: s_and_b32 s6, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s7, s44, 16
|
|
; SI-NEXT: s_add_i32 s29, s29, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s7, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s8, s68, 16
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: s_and_b32 s8, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s97, 16
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_add_i32 s27, s27, 3
|
|
; SI-NEXT: s_add_i32 s10, s8, 0x30000
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s70, 16
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_add_i32 s11, s8, 0x30000
|
|
; SI-NEXT: s_and_b32 s8, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s96, 16
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_add_i32 s25, s25, 3
|
|
; SI-NEXT: s_add_i32 s14, s8, 0x30000
|
|
; SI-NEXT: s_and_b32 s8, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s71, 16
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_add_i32 s22, s22, 3
|
|
; SI-NEXT: s_add_i32 s15, s8, 0x30000
|
|
; SI-NEXT: s_and_b32 s8, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s9, s87, 16
|
|
; SI-NEXT: s_add_i32 s23, s23, 3
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_and_b32 s9, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s12, s80, 16
|
|
; SI-NEXT: s_add_i32 s20, s20, 3
|
|
; SI-NEXT: s_or_b32 s9, s12, s9
|
|
; SI-NEXT: s_and_b32 s12, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s13, s86, 16
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: s_and_b32 s13, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s81, 16
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_or_b32 s13, s20, s13
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s85, 16
|
|
; SI-NEXT: s_or_b32 s18, s20, s18
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_add_i32 s40, s18, 0x30000
|
|
; SI-NEXT: s_and_b32 s18, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s19, s82, 16
|
|
; SI-NEXT: s_or_b32 s18, s19, s18
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: s_add_i32 s41, s18, 0x30000
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s18, s84, 16
|
|
; SI-NEXT: s_or_b32 s16, s18, s16
|
|
; SI-NEXT: s_add_i32 s17, s17, 3
|
|
; SI-NEXT: s_add_i32 s42, s16, 0x30000
|
|
; SI-NEXT: s_and_b32 s16, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s17, s83, 16
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_add_i32 s43, s16, 0x30000
|
|
; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 24
|
|
; SI-NEXT: v_writelane_b32 v5, s16, 2
|
|
; SI-NEXT: v_writelane_b32 v5, s17, 3
|
|
; SI-NEXT: s_lshr_b64 s[16:17], s[42:43], 16
|
|
; SI-NEXT: v_writelane_b32 v5, s16, 0
|
|
; SI-NEXT: v_writelane_b32 v5, s17, 1
|
|
; SI-NEXT: s_lshr_b64 s[16:17], s[40:41], 24
|
|
; SI-NEXT: s_add_i32 s8, s8, 0x30000
|
|
; SI-NEXT: s_add_i32 s9, s9, 0x30000
|
|
; SI-NEXT: s_add_i32 s12, s12, 0x30000
|
|
; SI-NEXT: s_add_i32 s13, s13, 0x30000
|
|
; SI-NEXT: v_writelane_b32 v5, s16, 4
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x30000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x30000
|
|
; SI-NEXT: s_add_i32 s6, s6, 0x30000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x30000
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[42:43], 8
|
|
; SI-NEXT: v_writelane_b32 v5, s17, 5
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 8
|
|
; SI-NEXT: s_lshr_b64 s[16:17], s[12:13], 24
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[12:13], 8
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[8:9], 24
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[8:9], 16
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[8:9], 8
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[14:15], 24
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[14:15], 16
|
|
; SI-NEXT: v_writelane_b32 v5, s16, 6
|
|
; SI-NEXT: s_lshr_b64 s[66:67], s[14:15], 8
|
|
; SI-NEXT: s_lshr_b64 s[52:53], s[10:11], 24
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b64 s[64:65], s[10:11], 8
|
|
; SI-NEXT: s_lshr_b64 s[38:39], s[6:7], 24
|
|
; SI-NEXT: s_lshr_b64 s[48:49], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[50:51], s[6:7], 8
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[4:5], 8
|
|
; SI-NEXT: s_lshr_b32 s99, s43, 24
|
|
; SI-NEXT: s_lshr_b32 s83, s43, 16
|
|
; SI-NEXT: s_lshr_b32 s98, s43, 8
|
|
; SI-NEXT: s_lshr_b32 s95, s41, 24
|
|
; SI-NEXT: s_lshr_b32 s82, s41, 16
|
|
; SI-NEXT: s_lshr_b32 s93, s41, 8
|
|
; SI-NEXT: s_lshr_b32 s91, s13, 24
|
|
; SI-NEXT: s_lshr_b32 s81, s13, 16
|
|
; SI-NEXT: s_lshr_b32 s89, s13, 8
|
|
; SI-NEXT: s_lshr_b32 s79, s9, 24
|
|
; SI-NEXT: s_lshr_b32 s80, s9, 16
|
|
; SI-NEXT: s_lshr_b32 s77, s9, 8
|
|
; SI-NEXT: s_lshr_b32 s75, s15, 24
|
|
; SI-NEXT: s_lshr_b32 s71, s15, 16
|
|
; SI-NEXT: s_lshr_b32 s73, s15, 8
|
|
; SI-NEXT: s_lshr_b32 s63, s11, 24
|
|
; SI-NEXT: s_lshr_b32 s70, s11, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s11, 8
|
|
; SI-NEXT: s_lshr_b32 s59, s7, 24
|
|
; SI-NEXT: s_lshr_b32 s68, s7, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s7, 8
|
|
; SI-NEXT: s_lshr_b32 s47, s5, 24
|
|
; SI-NEXT: s_lshr_b32 s69, s5, 16
|
|
; SI-NEXT: s_lshr_b32 s45, s5, 8
|
|
; SI-NEXT: v_writelane_b32 v5, s17, 7
|
|
; SI-NEXT: .LBB97_3: ; %end
|
|
; SI-NEXT: v_readlane_b32 s18, v5, 0
|
|
; SI-NEXT: s_and_b32 s16, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s62, 8
|
|
; SI-NEXT: v_readlane_b32 s19, v5, 1
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s18, 0xff
|
|
; SI-NEXT: v_readlane_b32 s18, v5, 2
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 24
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: v_mov_b32_e32 v1, s16
|
|
; SI-NEXT: s_and_b32 s16, s43, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s98, 8
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s83, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_lshl_b32 s18, s99, 24
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: v_readlane_b32 s19, v5, 3
|
|
; SI-NEXT: v_mov_b32_e32 v2, s16
|
|
; SI-NEXT: s_and_b32 s16, s40, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s74, 8
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s60, 0xff
|
|
; SI-NEXT: v_readlane_b32 s18, v5, 4
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 24
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 4, v0
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s16
|
|
; SI-NEXT: s_and_b32 s16, s41, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s93, 8
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s82, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_lshl_b32 s18, s95, 24
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: v_readlane_b32 s19, v5, 5
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s16
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xff
|
|
; SI-NEXT: s_lshl_b32 s16, s76, 8
|
|
; SI-NEXT: s_or_b32 s12, s12, s16
|
|
; SI-NEXT: s_and_b32 s16, s72, 0xff
|
|
; SI-NEXT: v_readlane_b32 s18, v5, 6
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s18, 24
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 12, v0
|
|
; SI-NEXT: s_or_b32 s12, s12, s16
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s12
|
|
; SI-NEXT: s_and_b32 s12, s13, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s89, 8
|
|
; SI-NEXT: s_or_b32 s12, s12, s13
|
|
; SI-NEXT: s_and_b32 s13, s81, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_lshl_b32 s16, s91, 24
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_or_b32 s13, s16, s13
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
|
|
; SI-NEXT: s_or_b32 s12, s12, s13
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s12
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xff
|
|
; SI-NEXT: s_lshl_b32 s12, s94, 8
|
|
; SI-NEXT: s_or_b32 s8, s8, s12
|
|
; SI-NEXT: s_and_b32 s12, s90, 0xff
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_lshl_b32 s13, s78, 24
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 20, v0
|
|
; SI-NEXT: s_or_b32 s8, s8, s12
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s8
|
|
; SI-NEXT: s_and_b32 s8, s9, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s77, 8
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: s_and_b32 s9, s80, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s12, s79, 24
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s12, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s8
|
|
; SI-NEXT: s_and_b32 s8, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s66, 8
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: s_and_b32 s9, s92, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s12, s88, 24
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s12, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 28, v0
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s8
|
|
; SI-NEXT: s_and_b32 s8, s15, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s73, 8
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: s_and_b32 s9, s71, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s12, s75, 24
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s12, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s8
|
|
; SI-NEXT: s_and_b32 s8, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s64, 8
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: s_and_b32 s9, s54, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s10, s52, 24
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 36, v0
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s8
|
|
; SI-NEXT: s_and_b32 s8, s11, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s61, 8
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: s_and_b32 s9, s70, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s10, s63, 24
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s8
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xff
|
|
; SI-NEXT: s_lshl_b32 s8, s50, 8
|
|
; SI-NEXT: s_or_b32 s6, s6, s8
|
|
; SI-NEXT: s_and_b32 s8, s48, 0xff
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_lshl_b32 s9, s38, 24
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 44, v0
|
|
; SI-NEXT: s_or_b32 s6, s6, s8
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
|
; SI-NEXT: s_and_b32 s6, s7, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s57, 8
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: s_and_b32 s7, s68, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s8, s59, 24
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s36, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s34, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s30, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 52, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v2, s4
|
|
; SI-NEXT: s_and_b32 s4, s5, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s45, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s69, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s47, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: v_mov_b32_e32 v1, s4
|
|
; SI-NEXT: v_readlane_b32 s30, v4, 34
|
|
; SI-NEXT: v_readlane_b32 s19, v5, 7
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: v_readlane_b32 s31, v4, 35
|
|
; SI-NEXT: v_readlane_b32 s99, v4, 33
|
|
; SI-NEXT: v_readlane_b32 s98, v4, 32
|
|
; SI-NEXT: v_readlane_b32 s97, v4, 31
|
|
; SI-NEXT: v_readlane_b32 s96, v4, 30
|
|
; SI-NEXT: v_readlane_b32 s87, v4, 29
|
|
; SI-NEXT: v_readlane_b32 s86, v4, 28
|
|
; SI-NEXT: v_readlane_b32 s85, v4, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v4, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v4, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v4, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v4, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v4, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v4, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v4, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v4, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v4, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v4, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v4, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v4, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v4, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v4, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v4, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v4, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v4, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v4, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v4, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v4, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v4, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v4, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v4, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v4, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v4, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v4, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v4, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB97_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v5, s4, 0
|
|
; SI-NEXT: v_writelane_b32 v5, s5, 1
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr98
|
|
; SI-NEXT: ; implicit-def: $sgpr99
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr93
|
|
; SI-NEXT: ; implicit-def: $sgpr95
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr89
|
|
; SI-NEXT: ; implicit-def: $sgpr91
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr79
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr90
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr66
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr64
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr52
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr50
|
|
; SI-NEXT: ; implicit-def: $sgpr48
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr36
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: v_writelane_b32 v5, s4, 2
|
|
; SI-NEXT: v_writelane_b32 v5, s5, 3
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: v_writelane_b32 v5, s4, 4
|
|
; SI-NEXT: v_writelane_b32 v5, s5, 5
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: v_writelane_b32 v5, s4, 6
|
|
; SI-NEXT: v_writelane_b32 v5, s5, 7
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: s_branch .LBB97_2
|
|
;
|
|
; VI-LABEL: bitcast_v32i16_to_v64i8_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v4, s34, 0
|
|
; VI-NEXT: v_writelane_b32 v4, s35, 1
|
|
; VI-NEXT: v_writelane_b32 v4, s36, 2
|
|
; VI-NEXT: v_writelane_b32 v4, s37, 3
|
|
; VI-NEXT: v_writelane_b32 v4, s38, 4
|
|
; VI-NEXT: v_writelane_b32 v4, s39, 5
|
|
; VI-NEXT: v_writelane_b32 v4, s48, 6
|
|
; VI-NEXT: v_writelane_b32 v4, s49, 7
|
|
; VI-NEXT: v_writelane_b32 v4, s50, 8
|
|
; VI-NEXT: v_writelane_b32 v4, s51, 9
|
|
; VI-NEXT: v_writelane_b32 v4, s52, 10
|
|
; VI-NEXT: v_writelane_b32 v4, s53, 11
|
|
; VI-NEXT: v_writelane_b32 v4, s54, 12
|
|
; VI-NEXT: v_writelane_b32 v4, s55, 13
|
|
; VI-NEXT: v_writelane_b32 v4, s64, 14
|
|
; VI-NEXT: v_writelane_b32 v4, s65, 15
|
|
; VI-NEXT: v_writelane_b32 v4, s66, 16
|
|
; VI-NEXT: v_writelane_b32 v4, s67, 17
|
|
; VI-NEXT: v_writelane_b32 v4, s30, 18
|
|
; VI-NEXT: v_writelane_b32 v4, s31, 19
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; VI-NEXT: s_cbranch_scc0 .LBB97_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_lshr_b32 s56, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s58, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s60, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s61, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s63, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s72, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s74, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s75, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s76, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s77, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s78, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s79, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s89, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s90, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s91, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s31, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s34, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s35, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s36, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s39, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s48, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s49, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s50, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s51, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s52, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s53, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s54, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s65, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s66, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 8
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; VI-NEXT: s_cbranch_execnz .LBB97_3
|
|
; VI-NEXT: .LBB97_2: ; %cmp.true
|
|
; VI-NEXT: s_add_i32 s7, s17, 3
|
|
; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s16, 3
|
|
; VI-NEXT: s_add_i32 s17, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s19, 3
|
|
; VI-NEXT: s_add_i32 s16, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s18, 3
|
|
; VI-NEXT: s_add_i32 s19, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s18, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s21, 3
|
|
; VI-NEXT: s_add_i32 s18, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s20, 3
|
|
; VI-NEXT: s_add_i32 s21, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s20, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s23, 3
|
|
; VI-NEXT: s_add_i32 s20, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s22, 3
|
|
; VI-NEXT: s_add_i32 s23, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s22, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s25, 3
|
|
; VI-NEXT: s_add_i32 s22, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s24, 3
|
|
; VI-NEXT: s_add_i32 s25, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s24, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s27, 3
|
|
; VI-NEXT: s_add_i32 s24, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s26, 3
|
|
; VI-NEXT: s_add_i32 s27, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s26, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s29, 3
|
|
; VI-NEXT: s_add_i32 s26, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s29, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s7, s28, 3
|
|
; VI-NEXT: s_add_i32 s29, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; VI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; VI-NEXT: s_or_b32 s6, s6, s7
|
|
; VI-NEXT: s_add_i32 s28, s6, 0x30000
|
|
; VI-NEXT: s_and_b32 s6, s5, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s5, s5, 3
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; VI-NEXT: s_or_b32 s5, s6, s5
|
|
; VI-NEXT: s_and_b32 s6, s4, 0xffff0000
|
|
; VI-NEXT: s_add_i32 s4, s4, 3
|
|
; VI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; VI-NEXT: s_or_b32 s4, s6, s4
|
|
; VI-NEXT: s_add_i32 s5, s5, 0x30000
|
|
; VI-NEXT: s_add_i32 s4, s4, 0x30000
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[16:17], 24
|
|
; VI-NEXT: s_lshr_b32 s56, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s58, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s60, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s61, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s62, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s63, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s72, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s74, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s75, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s76, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s77, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s78, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s79, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s89, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s90, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s91, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s31, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s34, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s35, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s36, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s39, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s48, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s49, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s50, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s51, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s52, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s53, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s54, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s65, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s66, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 8
|
|
; VI-NEXT: .LBB97_3: ; %end
|
|
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v3, s44
|
|
; VI-NEXT: v_mov_b32_e32 v1, s67
|
|
; VI-NEXT: v_perm_b32 v3, s66, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s55
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v1, s65
|
|
; VI-NEXT: v_perm_b32 v3, s64, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s42
|
|
; VI-NEXT: v_mov_b32_e32 v1, s54
|
|
; VI-NEXT: v_perm_b32 v3, s53, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s50
|
|
; VI-NEXT: v_mov_b32_e32 v1, s52
|
|
; VI-NEXT: v_perm_b32 v3, s51, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s40
|
|
; VI-NEXT: v_mov_b32_e32 v1, s49
|
|
; VI-NEXT: v_perm_b32 v3, s48, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s37
|
|
; VI-NEXT: v_mov_b32_e32 v1, s39
|
|
; VI-NEXT: v_perm_b32 v3, s38, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s14
|
|
; VI-NEXT: v_mov_b32_e32 v1, s36
|
|
; VI-NEXT: v_perm_b32 v3, s35, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s30
|
|
; VI-NEXT: v_mov_b32_e32 v1, s34
|
|
; VI-NEXT: v_perm_b32 v3, s31, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s12
|
|
; VI-NEXT: v_mov_b32_e32 v1, s91
|
|
; VI-NEXT: v_perm_b32 v3, s90, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s79
|
|
; VI-NEXT: v_mov_b32_e32 v1, s89
|
|
; VI-NEXT: v_perm_b32 v3, s88, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s10
|
|
; VI-NEXT: v_mov_b32_e32 v1, s78
|
|
; VI-NEXT: v_perm_b32 v3, s77, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s26, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s74
|
|
; VI-NEXT: v_mov_b32_e32 v1, s76
|
|
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s27, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s8
|
|
; VI-NEXT: v_mov_b32_e32 v1, s73
|
|
; VI-NEXT: v_perm_b32 v3, s72, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s28, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s61
|
|
; VI-NEXT: v_mov_b32_e32 v1, s63
|
|
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s29, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v3, s6
|
|
; VI-NEXT: v_mov_b32_e32 v1, s60
|
|
; VI-NEXT: v_perm_b32 v3, s59, v3, v2
|
|
; VI-NEXT: v_perm_b32 v1, s4, v1, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_mov_b32_e32 v1, s58
|
|
; VI-NEXT: v_mov_b32_e32 v3, s56
|
|
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
|
|
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: v_readlane_b32 s30, v4, 18
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_readlane_b32 s31, v4, 19
|
|
; VI-NEXT: v_readlane_b32 s67, v4, 17
|
|
; VI-NEXT: v_readlane_b32 s66, v4, 16
|
|
; VI-NEXT: v_readlane_b32 s65, v4, 15
|
|
; VI-NEXT: v_readlane_b32 s64, v4, 14
|
|
; VI-NEXT: v_readlane_b32 s55, v4, 13
|
|
; VI-NEXT: v_readlane_b32 s54, v4, 12
|
|
; VI-NEXT: v_readlane_b32 s53, v4, 11
|
|
; VI-NEXT: v_readlane_b32 s52, v4, 10
|
|
; VI-NEXT: v_readlane_b32 s51, v4, 9
|
|
; VI-NEXT: v_readlane_b32 s50, v4, 8
|
|
; VI-NEXT: v_readlane_b32 s49, v4, 7
|
|
; VI-NEXT: v_readlane_b32 s48, v4, 6
|
|
; VI-NEXT: v_readlane_b32 s39, v4, 5
|
|
; VI-NEXT: v_readlane_b32 s38, v4, 4
|
|
; VI-NEXT: v_readlane_b32 s37, v4, 3
|
|
; VI-NEXT: v_readlane_b32 s36, v4, 2
|
|
; VI-NEXT: v_readlane_b32 s35, v4, 1
|
|
; VI-NEXT: v_readlane_b32 s34, v4, 0
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB97_4:
|
|
; VI-NEXT: ; implicit-def: $sgpr67
|
|
; VI-NEXT: ; implicit-def: $sgpr66
|
|
; VI-NEXT: ; implicit-def: $sgpr44
|
|
; VI-NEXT: ; implicit-def: $sgpr65
|
|
; VI-NEXT: ; implicit-def: $sgpr64
|
|
; VI-NEXT: ; implicit-def: $sgpr55
|
|
; VI-NEXT: ; implicit-def: $sgpr54
|
|
; VI-NEXT: ; implicit-def: $sgpr53
|
|
; VI-NEXT: ; implicit-def: $sgpr42
|
|
; VI-NEXT: ; implicit-def: $sgpr52
|
|
; VI-NEXT: ; implicit-def: $sgpr51
|
|
; VI-NEXT: ; implicit-def: $sgpr50
|
|
; VI-NEXT: ; implicit-def: $sgpr49
|
|
; VI-NEXT: ; implicit-def: $sgpr48
|
|
; VI-NEXT: ; implicit-def: $sgpr40
|
|
; VI-NEXT: ; implicit-def: $sgpr39
|
|
; VI-NEXT: ; implicit-def: $sgpr38
|
|
; VI-NEXT: ; implicit-def: $sgpr37
|
|
; VI-NEXT: ; implicit-def: $sgpr36
|
|
; VI-NEXT: ; implicit-def: $sgpr35
|
|
; VI-NEXT: ; implicit-def: $sgpr14
|
|
; VI-NEXT: ; implicit-def: $sgpr34
|
|
; VI-NEXT: ; implicit-def: $sgpr31
|
|
; VI-NEXT: ; implicit-def: $sgpr30
|
|
; VI-NEXT: ; implicit-def: $sgpr91
|
|
; VI-NEXT: ; implicit-def: $sgpr90
|
|
; VI-NEXT: ; implicit-def: $sgpr12
|
|
; VI-NEXT: ; implicit-def: $sgpr89
|
|
; VI-NEXT: ; implicit-def: $sgpr88
|
|
; VI-NEXT: ; implicit-def: $sgpr79
|
|
; VI-NEXT: ; implicit-def: $sgpr78
|
|
; VI-NEXT: ; implicit-def: $sgpr77
|
|
; VI-NEXT: ; implicit-def: $sgpr10
|
|
; VI-NEXT: ; implicit-def: $sgpr76
|
|
; VI-NEXT: ; implicit-def: $sgpr75
|
|
; VI-NEXT: ; implicit-def: $sgpr74
|
|
; VI-NEXT: ; implicit-def: $sgpr73
|
|
; VI-NEXT: ; implicit-def: $sgpr72
|
|
; VI-NEXT: ; implicit-def: $sgpr8
|
|
; VI-NEXT: ; implicit-def: $sgpr63
|
|
; VI-NEXT: ; implicit-def: $sgpr62
|
|
; VI-NEXT: ; implicit-def: $sgpr61
|
|
; VI-NEXT: ; implicit-def: $sgpr60
|
|
; VI-NEXT: ; implicit-def: $sgpr59
|
|
; VI-NEXT: ; implicit-def: $sgpr6
|
|
; VI-NEXT: ; implicit-def: $sgpr58
|
|
; VI-NEXT: ; implicit-def: $sgpr57
|
|
; VI-NEXT: ; implicit-def: $sgpr56
|
|
; VI-NEXT: s_branch .LBB97_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v32i16_to_v64i8_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
|
|
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
|
|
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
|
|
; GFX9-NEXT: v_writelane_b32 v63, s37, 3
|
|
; GFX9-NEXT: v_writelane_b32 v63, s38, 4
|
|
; GFX9-NEXT: v_writelane_b32 v63, s39, 5
|
|
; GFX9-NEXT: v_writelane_b32 v63, s48, 6
|
|
; GFX9-NEXT: v_writelane_b32 v63, s49, 7
|
|
; GFX9-NEXT: v_writelane_b32 v63, s50, 8
|
|
; GFX9-NEXT: v_writelane_b32 v63, s51, 9
|
|
; GFX9-NEXT: v_writelane_b32 v63, s52, 10
|
|
; GFX9-NEXT: v_writelane_b32 v63, s53, 11
|
|
; GFX9-NEXT: v_writelane_b32 v63, s54, 12
|
|
; GFX9-NEXT: v_writelane_b32 v63, s55, 13
|
|
; GFX9-NEXT: v_writelane_b32 v63, s30, 14
|
|
; GFX9-NEXT: v_writelane_b32 v63, s31, 15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB97_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s57, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s59, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s58, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s60, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s61, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s62, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s72, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s63, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s74, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s75, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s77, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s76, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s78, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s79, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s88, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s90, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s89, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s91, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s92, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s93, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s95, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s94, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s30, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s36, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s35, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s37, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s38, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s39, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s49, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s48, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s50, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s52, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s54, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s53, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB97_4
|
|
; GFX9-NEXT: .LBB97_2: ; %cmp.true
|
|
; GFX9-NEXT: v_pk_add_u16 v6, s27, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v5, s26, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v2, s5, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v1, s4, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v8, s25, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v7, s24, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
|
|
; GFX9-NEXT: v_pk_add_u16 v10, s23, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v9, s22, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX9-NEXT: v_pk_add_u16 v12, s21, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v11, s20, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v4, s29, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v3, s28, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; GFX9-NEXT: v_pk_add_u16 v14, s19, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v13, s18, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
|
|
; GFX9-NEXT: v_pk_add_u16 v19, s17, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_u16 v18, s16, 3 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[25:26], 24, v[18:19]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v18
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v18
|
|
; GFX9-NEXT: s_branch .LBB97_5
|
|
; GFX9-NEXT: .LBB97_3:
|
|
; GFX9-NEXT: ; implicit-def: $sgpr55
|
|
; GFX9-NEXT: ; implicit-def: $sgpr53
|
|
; GFX9-NEXT: ; implicit-def: $sgpr6
|
|
; GFX9-NEXT: ; implicit-def: $sgpr54
|
|
; GFX9-NEXT: ; implicit-def: $sgpr52
|
|
; GFX9-NEXT: ; implicit-def: $sgpr51
|
|
; GFX9-NEXT: ; implicit-def: $sgpr50
|
|
; GFX9-NEXT: ; implicit-def: $sgpr48
|
|
; GFX9-NEXT: ; implicit-def: $sgpr8
|
|
; GFX9-NEXT: ; implicit-def: $sgpr49
|
|
; GFX9-NEXT: ; implicit-def: $sgpr39
|
|
; GFX9-NEXT: ; implicit-def: $sgpr38
|
|
; GFX9-NEXT: ; implicit-def: $sgpr37
|
|
; GFX9-NEXT: ; implicit-def: $sgpr35
|
|
; GFX9-NEXT: ; implicit-def: $sgpr10
|
|
; GFX9-NEXT: ; implicit-def: $sgpr36
|
|
; GFX9-NEXT: ; implicit-def: $sgpr34
|
|
; GFX9-NEXT: ; implicit-def: $sgpr31
|
|
; GFX9-NEXT: ; implicit-def: $sgpr30
|
|
; GFX9-NEXT: ; implicit-def: $sgpr94
|
|
; GFX9-NEXT: ; implicit-def: $sgpr12
|
|
; GFX9-NEXT: ; implicit-def: $sgpr95
|
|
; GFX9-NEXT: ; implicit-def: $sgpr93
|
|
; GFX9-NEXT: ; implicit-def: $sgpr92
|
|
; GFX9-NEXT: ; implicit-def: $sgpr91
|
|
; GFX9-NEXT: ; implicit-def: $sgpr89
|
|
; GFX9-NEXT: ; implicit-def: $sgpr14
|
|
; GFX9-NEXT: ; implicit-def: $sgpr90
|
|
; GFX9-NEXT: ; implicit-def: $sgpr88
|
|
; GFX9-NEXT: ; implicit-def: $sgpr79
|
|
; GFX9-NEXT: ; implicit-def: $sgpr78
|
|
; GFX9-NEXT: ; implicit-def: $sgpr76
|
|
; GFX9-NEXT: ; implicit-def: $sgpr40
|
|
; GFX9-NEXT: ; implicit-def: $sgpr77
|
|
; GFX9-NEXT: ; implicit-def: $sgpr75
|
|
; GFX9-NEXT: ; implicit-def: $sgpr74
|
|
; GFX9-NEXT: ; implicit-def: $sgpr73
|
|
; GFX9-NEXT: ; implicit-def: $sgpr63
|
|
; GFX9-NEXT: ; implicit-def: $sgpr42
|
|
; GFX9-NEXT: ; implicit-def: $sgpr72
|
|
; GFX9-NEXT: ; implicit-def: $sgpr62
|
|
; GFX9-NEXT: ; implicit-def: $sgpr61
|
|
; GFX9-NEXT: ; implicit-def: $sgpr60
|
|
; GFX9-NEXT: ; implicit-def: $sgpr58
|
|
; GFX9-NEXT: ; implicit-def: $sgpr44
|
|
; GFX9-NEXT: ; implicit-def: $sgpr59
|
|
; GFX9-NEXT: ; implicit-def: $sgpr57
|
|
; GFX9-NEXT: ; implicit-def: $sgpr56
|
|
; GFX9-NEXT: s_branch .LBB97_2
|
|
; GFX9-NEXT: .LBB97_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s44
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s42
|
|
; GFX9-NEXT: v_mov_b32_e32 v18, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s5
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s55
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, s53
|
|
; GFX9-NEXT: v_mov_b32_e32 v62, s54
|
|
; GFX9-NEXT: v_mov_b32_e32 v59, s52
|
|
; GFX9-NEXT: v_mov_b32_e32 v60, s51
|
|
; GFX9-NEXT: v_mov_b32_e32 v58, s50
|
|
; GFX9-NEXT: v_mov_b32_e32 v61, s48
|
|
; GFX9-NEXT: v_mov_b32_e32 v57, s49
|
|
; GFX9-NEXT: v_mov_b32_e32 v47, s39
|
|
; GFX9-NEXT: v_mov_b32_e32 v56, s38
|
|
; GFX9-NEXT: v_mov_b32_e32 v46, s37
|
|
; GFX9-NEXT: v_mov_b32_e32 v45, s35
|
|
; GFX9-NEXT: v_mov_b32_e32 v44, s36
|
|
; GFX9-NEXT: v_mov_b32_e32 v42, s34
|
|
; GFX9-NEXT: v_mov_b32_e32 v43, s31
|
|
; GFX9-NEXT: v_mov_b32_e32 v41, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v40, s94
|
|
; GFX9-NEXT: v_mov_b32_e32 v55, s95
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, s93
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, s92
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, s91
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, s89
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, s90
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, s88
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, s79
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, s78
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, s76
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, s77
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, s75
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, s74
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, s73
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, s63
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, s72
|
|
; GFX9-NEXT: v_mov_b32_e32 v30, s62
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, s61
|
|
; GFX9-NEXT: v_mov_b32_e32 v29, s60
|
|
; GFX9-NEXT: v_mov_b32_e32 v28, s58
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, s59
|
|
; GFX9-NEXT: v_mov_b32_e32 v17, s57
|
|
; GFX9-NEXT: v_mov_b32_e32 v26, s56
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s12
|
|
; GFX9-NEXT: v_mov_b32_e32 v23, s10
|
|
; GFX9-NEXT: v_mov_b32_e32 v24, s8
|
|
; GFX9-NEXT: v_mov_b32_e32 v25, s6
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s40
|
|
; GFX9-NEXT: v_mov_b32_e32 v21, s14
|
|
; GFX9-NEXT: .LBB97_5: ; %end
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
|
|
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
|
|
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
|
|
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
|
|
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
|
|
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
|
|
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v34, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v29, s4
|
|
; GFX9-NEXT: v_readlane_b32 s30, v63, 14
|
|
; GFX9-NEXT: v_readlane_b32 s31, v63, 15
|
|
; GFX9-NEXT: v_readlane_b32 s55, v63, 13
|
|
; GFX9-NEXT: v_readlane_b32 s54, v63, 12
|
|
; GFX9-NEXT: v_readlane_b32 s53, v63, 11
|
|
; GFX9-NEXT: v_readlane_b32 s52, v63, 10
|
|
; GFX9-NEXT: v_readlane_b32 s51, v63, 9
|
|
; GFX9-NEXT: v_readlane_b32 s50, v63, 8
|
|
; GFX9-NEXT: v_readlane_b32 s49, v63, 7
|
|
; GFX9-NEXT: v_readlane_b32 s48, v63, 6
|
|
; GFX9-NEXT: v_readlane_b32 s39, v63, 5
|
|
; GFX9-NEXT: v_readlane_b32 s38, v63, 4
|
|
; GFX9-NEXT: v_readlane_b32 s37, v63, 3
|
|
; GFX9-NEXT: v_readlane_b32 s36, v63, 2
|
|
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
|
|
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
|
|
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32i16_to_v64i8_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_or_saveexec_b32 s4, -1
|
|
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s4
|
|
; GFX11-NEXT: v_writelane_b32 v40, s34, 0
|
|
; GFX11-NEXT: v_writelane_b32 v40, s35, 1
|
|
; GFX11-NEXT: v_writelane_b32 v40, s36, 2
|
|
; GFX11-NEXT: v_writelane_b32 v40, s37, 3
|
|
; GFX11-NEXT: v_writelane_b32 v40, s38, 4
|
|
; GFX11-NEXT: v_writelane_b32 v40, s39, 5
|
|
; GFX11-NEXT: v_writelane_b32 v40, s48, 6
|
|
; GFX11-NEXT: v_writelane_b32 v40, s49, 7
|
|
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
|
|
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s42, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB97_3
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
|
|
; GFX11-NEXT: s_lshr_b32 s44, s27, 16
|
|
; GFX11-NEXT: s_lshr_b32 s46, s27, 8
|
|
; GFX11-NEXT: s_lshr_b32 s45, s26, 16
|
|
; GFX11-NEXT: s_lshr_b32 s47, s26, 8
|
|
; GFX11-NEXT: s_lshr_b32 s56, s25, 24
|
|
; GFX11-NEXT: s_lshr_b32 s57, s25, 16
|
|
; GFX11-NEXT: s_lshr_b32 s59, s25, 8
|
|
; GFX11-NEXT: s_lshr_b32 s58, s24, 16
|
|
; GFX11-NEXT: s_lshr_b32 s60, s24, 8
|
|
; GFX11-NEXT: s_lshr_b32 s61, s23, 24
|
|
; GFX11-NEXT: s_lshr_b32 s62, s23, 16
|
|
; GFX11-NEXT: s_lshr_b32 s72, s23, 8
|
|
; GFX11-NEXT: s_lshr_b32 s63, s22, 16
|
|
; GFX11-NEXT: s_lshr_b32 s73, s22, 8
|
|
; GFX11-NEXT: s_lshr_b32 s74, s21, 24
|
|
; GFX11-NEXT: s_lshr_b32 s75, s21, 16
|
|
; GFX11-NEXT: s_lshr_b32 s77, s21, 8
|
|
; GFX11-NEXT: s_lshr_b32 s76, s20, 16
|
|
; GFX11-NEXT: s_lshr_b32 s78, s20, 8
|
|
; GFX11-NEXT: s_lshr_b32 s79, s19, 24
|
|
; GFX11-NEXT: s_lshr_b32 s88, s19, 16
|
|
; GFX11-NEXT: s_lshr_b32 s90, s19, 8
|
|
; GFX11-NEXT: s_lshr_b32 s89, s18, 16
|
|
; GFX11-NEXT: s_lshr_b32 s91, s18, 8
|
|
; GFX11-NEXT: s_lshr_b32 s92, s17, 24
|
|
; GFX11-NEXT: s_lshr_b32 s93, s17, 16
|
|
; GFX11-NEXT: s_lshr_b32 s95, s17, 8
|
|
; GFX11-NEXT: s_lshr_b32 s94, s16, 16
|
|
; GFX11-NEXT: s_lshr_b32 vcc_hi, s16, 8
|
|
; GFX11-NEXT: s_lshr_b32 s30, s3, 24
|
|
; GFX11-NEXT: s_lshr_b32 s31, s3, 16
|
|
; GFX11-NEXT: s_lshr_b32 s35, s3, 8
|
|
; GFX11-NEXT: s_lshr_b32 s34, s2, 16
|
|
; GFX11-NEXT: s_lshr_b32 s36, s2, 8
|
|
; GFX11-NEXT: s_lshr_b32 s37, s1, 24
|
|
; GFX11-NEXT: s_lshr_b32 s38, s1, 16
|
|
; GFX11-NEXT: s_lshr_b32 s48, s1, 8
|
|
; GFX11-NEXT: s_lshr_b32 s39, s0, 16
|
|
; GFX11-NEXT: s_lshr_b32 s49, s0, 8
|
|
; GFX11-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[28:29], s[24:25], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[12:13], s[20:21], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[10:11], s[18:19], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[8:9], s[16:17], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[6:7], s[2:3], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[4:5], s[0:1], 24
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB97_4
|
|
; GFX11-NEXT: .LBB97_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_u16 v4, s25, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v3, s24, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v6, s23, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v5, s22, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v8, s21, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v7, s20, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v10, s19, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v9, s18, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v12, s17, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v11, s16, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v14, s3, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v13, s2, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[3:4]
|
|
; GFX11-NEXT: v_pk_add_u16 v18, s1, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v17, s0, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v2, s27, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_pk_add_u16 v1, s26, 3 op_sel_hi:[1,0]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[17:18]
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v5
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v5
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v7
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v49, 8, v7
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v55, 24, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v9
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v64, 8, v9
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v69, 24, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v67, 8, v11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v13
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v13
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v87, 24, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v17
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v17
|
|
; GFX11-NEXT: s_branch .LBB97_5
|
|
; GFX11-NEXT: .LBB97_3:
|
|
; GFX11-NEXT: ; implicit-def: $sgpr49
|
|
; GFX11-NEXT: ; implicit-def: $sgpr39
|
|
; GFX11-NEXT: ; implicit-def: $sgpr4
|
|
; GFX11-NEXT: ; implicit-def: $sgpr48
|
|
; GFX11-NEXT: ; implicit-def: $sgpr38
|
|
; GFX11-NEXT: ; implicit-def: $sgpr37
|
|
; GFX11-NEXT: ; implicit-def: $sgpr36
|
|
; GFX11-NEXT: ; implicit-def: $sgpr34
|
|
; GFX11-NEXT: ; implicit-def: $sgpr6
|
|
; GFX11-NEXT: ; implicit-def: $sgpr35
|
|
; GFX11-NEXT: ; implicit-def: $sgpr31
|
|
; GFX11-NEXT: ; implicit-def: $sgpr30
|
|
; GFX11-NEXT: ; implicit-def: $vcc_hi
|
|
; GFX11-NEXT: ; implicit-def: $sgpr94
|
|
; GFX11-NEXT: ; implicit-def: $sgpr8
|
|
; GFX11-NEXT: ; implicit-def: $sgpr95
|
|
; GFX11-NEXT: ; implicit-def: $sgpr93
|
|
; GFX11-NEXT: ; implicit-def: $sgpr92
|
|
; GFX11-NEXT: ; implicit-def: $sgpr91
|
|
; GFX11-NEXT: ; implicit-def: $sgpr89
|
|
; GFX11-NEXT: ; implicit-def: $sgpr10
|
|
; GFX11-NEXT: ; implicit-def: $sgpr90
|
|
; GFX11-NEXT: ; implicit-def: $sgpr88
|
|
; GFX11-NEXT: ; implicit-def: $sgpr79
|
|
; GFX11-NEXT: ; implicit-def: $sgpr78
|
|
; GFX11-NEXT: ; implicit-def: $sgpr76
|
|
; GFX11-NEXT: ; implicit-def: $sgpr12
|
|
; GFX11-NEXT: ; implicit-def: $sgpr77
|
|
; GFX11-NEXT: ; implicit-def: $sgpr75
|
|
; GFX11-NEXT: ; implicit-def: $sgpr74
|
|
; GFX11-NEXT: ; implicit-def: $sgpr73
|
|
; GFX11-NEXT: ; implicit-def: $sgpr63
|
|
; GFX11-NEXT: ; implicit-def: $sgpr14
|
|
; GFX11-NEXT: ; implicit-def: $sgpr72
|
|
; GFX11-NEXT: ; implicit-def: $sgpr62
|
|
; GFX11-NEXT: ; implicit-def: $sgpr61
|
|
; GFX11-NEXT: ; implicit-def: $sgpr60
|
|
; GFX11-NEXT: ; implicit-def: $sgpr58
|
|
; GFX11-NEXT: ; implicit-def: $sgpr28
|
|
; GFX11-NEXT: ; implicit-def: $sgpr59
|
|
; GFX11-NEXT: ; implicit-def: $sgpr57
|
|
; GFX11-NEXT: ; implicit-def: $sgpr56
|
|
; GFX11-NEXT: ; implicit-def: $sgpr47
|
|
; GFX11-NEXT: ; implicit-def: $sgpr45
|
|
; GFX11-NEXT: ; implicit-def: $sgpr40
|
|
; GFX11-NEXT: ; implicit-def: $sgpr46
|
|
; GFX11-NEXT: ; implicit-def: $sgpr44
|
|
; GFX11-NEXT: ; implicit-def: $sgpr43
|
|
; GFX11-NEXT: s_branch .LBB97_2
|
|
; GFX11-NEXT: .LBB97_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v17, s0 :: v_dual_mov_b32 v18, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v14, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v12, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v8, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v4, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
|
|
; GFX11-NEXT: v_dual_mov_b32 v85, s49 :: v_dual_mov_b32 v96, s39
|
|
; GFX11-NEXT: v_dual_mov_b32 v83, s48 :: v_dual_mov_b32 v86, s38
|
|
; GFX11-NEXT: v_dual_mov_b32 v87, s37 :: v_dual_mov_b32 v82, s36
|
|
; GFX11-NEXT: v_dual_mov_b32 v84, s34 :: v_dual_mov_b32 v71, s35
|
|
; GFX11-NEXT: v_dual_mov_b32 v80, s31 :: v_dual_mov_b32 v81, s30
|
|
; GFX11-NEXT: v_dual_mov_b32 v67, vcc_hi :: v_dual_mov_b32 v70, s94
|
|
; GFX11-NEXT: v_dual_mov_b32 v65, s95 :: v_dual_mov_b32 v68, s93
|
|
; GFX11-NEXT: v_dual_mov_b32 v69, s92 :: v_dual_mov_b32 v64, s91
|
|
; GFX11-NEXT: v_dual_mov_b32 v66, s89 :: v_dual_mov_b32 v53, s90
|
|
; GFX11-NEXT: v_dual_mov_b32 v54, s88 :: v_dual_mov_b32 v55, s79
|
|
; GFX11-NEXT: v_dual_mov_b32 v49, s78 :: v_dual_mov_b32 v52, s76
|
|
; GFX11-NEXT: v_dual_mov_b32 v39, s77 :: v_dual_mov_b32 v50, s75
|
|
; GFX11-NEXT: v_dual_mov_b32 v51, s74 :: v_dual_mov_b32 v38, s73
|
|
; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v37, s61
|
|
; GFX11-NEXT: v_dual_mov_b32 v34, s72 :: v_dual_mov_b32 v33, s60
|
|
; GFX11-NEXT: v_dual_mov_b32 v36, s62 :: v_dual_mov_b32 v35, s58
|
|
; GFX11-NEXT: v_dual_mov_b32 v29, s59 :: v_dual_mov_b32 v32, s56
|
|
; GFX11-NEXT: v_dual_mov_b32 v31, s57 :: v_dual_mov_b32 v26, s47
|
|
; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v27, s44
|
|
; GFX11-NEXT: v_dual_mov_b32 v16, s46 :: v_dual_mov_b32 v15, s40
|
|
; GFX11-NEXT: v_dual_mov_b32 v28, s43 :: v_dual_mov_b32 v19, s28
|
|
; GFX11-NEXT: v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v21, s12
|
|
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
|
|
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
|
|
; GFX11-NEXT: .LBB97_5: ; %end
|
|
; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
|
|
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
|
|
; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
|
|
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
|
|
; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
|
|
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
|
|
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
|
|
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
|
|
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
|
|
; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
|
|
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
|
|
; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
|
|
; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
|
|
; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
|
|
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
|
|
; GFX11-NEXT: s_clause 0x3
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:16
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:32
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
|
|
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
|
|
; GFX11-NEXT: v_readlane_b32 s49, v40, 7
|
|
; GFX11-NEXT: v_readlane_b32 s48, v40, 6
|
|
; GFX11-NEXT: v_readlane_b32 s39, v40, 5
|
|
; GFX11-NEXT: v_readlane_b32 s38, v40, 4
|
|
; GFX11-NEXT: v_readlane_b32 s37, v40, 3
|
|
; GFX11-NEXT: v_readlane_b32 s36, v40, 2
|
|
; GFX11-NEXT: v_readlane_b32 s35, v40, 1
|
|
; GFX11-NEXT: v_readlane_b32 s34, v40, 0
|
|
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
|
|
; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s0
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <32 x i16> %a, splat (i16 3)
|
|
%a2 = bitcast <32 x i16> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x i16> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v32i16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
|
|
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:80
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
|
|
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112
|
|
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:104
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:92
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v44, 24, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v47, 8, v25
|
|
; SI-NEXT: ; kill: killed $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; kill: killed $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v6
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v12
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v63, 24, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v28
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v31
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v32
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v33
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v35
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v36
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:108
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:100
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB98_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v52
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v16, v16, v13
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v1, v6, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v39, v46, v9
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v29, v5, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_or_b32_e32 v23, v0, v29
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v39
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_or_b32_e32 v14, v5, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v36, v5, v0
|
|
; SI-NEXT: v_alignbit_b32 v0, v23, v14, 16
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v0, v36
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v17, v5, v0
|
|
; SI-NEXT: v_alignbit_b32 v0, v3, v17, 16
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v55
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v37, v7, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v0, v37
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v37
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v19, v54, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v38, v42, v7
|
|
; SI-NEXT: v_alignbit_b32 v53, v5, v19, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v56
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v7, v0, v38
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v38
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v25, v44, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v45, v7, v25, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v60
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v9, v0, v39
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v20, v57, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v62
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v12, v59, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v0, v12
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v26, v63, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v40
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v18
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v13, v0, v16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v8
|
|
; SI-NEXT: v_or_b32_e32 v15, v0, v4
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v8, v27, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v32, v9, v20, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v11, v26, 16
|
|
; SI-NEXT: v_alignbit_b32 v21, v13, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v33, v15, v8, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v18
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v14
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v18
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v17
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v18
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v61, v17, v19
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_or_b32_e32 v19, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v51
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v47
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v43, v17, v25
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v31
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v48, v17, v20
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: v_or_b32_e32 v10, v17, v10
|
|
; SI-NEXT: v_or_b32_e32 v17, v1, v8
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_or_b32_e32 v25, v10, v26
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: .LBB98_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB98_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v58
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
|
|
; SI-NEXT: v_or_b32_e32 v0, v51, v0
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_or_b32_e32 v3, v27, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v34, v3
|
|
; SI-NEXT: s_movk_i32 s6, 0x300
|
|
; SI-NEXT: s_mov_b32 s7, 0x3000000
|
|
; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v3
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v41
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v40
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v52
|
|
; SI-NEXT: v_or_b32_e32 v0, v18, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v63, v1
|
|
; SI-NEXT: v_alignbit_b32 v21, v13, v19, 16
|
|
; SI-NEXT: v_alignbit_b32 v33, v15, v17, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v15
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v10, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v12
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
|
|
; SI-NEXT: v_or_b32_e32 v0, v62, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v59, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v57, v1
|
|
; SI-NEXT: v_alignbit_b32 v22, v11, v25, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v31, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v60, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v46, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v32, v9, v48, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v47, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v44, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v43, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v56, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v42, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v45, v7, v43, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v7
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v54, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v61, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v55, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v53, v5, v61, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v4, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v1
|
|
; SI-NEXT: v_alignbit_b32 v1, v23, v0, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v3, v14, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
|
|
; SI-NEXT: .LBB98_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v61
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v25
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v32i16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; VI-NEXT: buffer_load_ushort v55, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:128
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:124
|
|
; VI-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:120
|
|
; VI-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:116
|
|
; VI-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:112
|
|
; VI-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:108
|
|
; VI-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:104
|
|
; VI-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:100
|
|
; VI-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:96
|
|
; VI-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:92
|
|
; VI-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:88
|
|
; VI-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:84
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:80
|
|
; VI-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: v_mov_b32_e32 v17, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB98_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; kill: killed $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v0, v1, v0, s6
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
|
|
; VI-NEXT: v_perm_b32 v16, v32, v54, s6
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; VI-NEXT: v_perm_b32 v15, v53, v52, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: .LBB98_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB98_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v32
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v54
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v53
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v52
|
|
; VI-NEXT: v_or_b32_sdwa v15, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v51
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v50
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v39
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v38
|
|
; VI-NEXT: v_or_b32_sdwa v14, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(12)
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v49
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v48
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_mov_b32_e32 v3, 0x300
|
|
; VI-NEXT: v_add_u16_sdwa v32, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v38, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(10)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v37
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v36
|
|
; VI-NEXT: v_or_b32_sdwa v36, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(8)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v35
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v34
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v12, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(6)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v31
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v63
|
|
; VI-NEXT: v_or_b32_sdwa v31, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v33
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v62
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v11, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v59
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v56
|
|
; VI-NEXT: v_or_b32_sdwa v33, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v58
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v47
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v10, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v61
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v60
|
|
; VI-NEXT: v_or_b32_sdwa v34, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v57
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v46
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v9, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v45
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v43
|
|
; VI-NEXT: v_or_b32_sdwa v35, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v44
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v42
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v8, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v41
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v40
|
|
; VI-NEXT: v_or_b32_sdwa v37, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v30
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v55
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v7, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v28
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v29
|
|
; VI-NEXT: v_or_b32_sdwa v28, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v26
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v27
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v6, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v24
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v25
|
|
; VI-NEXT: v_or_b32_sdwa v24, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v22
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v23
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v5, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v20
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v21
|
|
; VI-NEXT: v_or_b32_sdwa v20, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v18
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v19
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_sdwa v4, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v16
|
|
; VI-NEXT: v_add_u16_sdwa v13, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; VI-NEXT: v_add_u16_e32 v15, 0x300, v15
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v38
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v32
|
|
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v16, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v17
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v16
|
|
; VI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v20
|
|
; VI-NEXT: v_or_b32_e32 v5, v16, v5
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v24
|
|
; VI-NEXT: v_or_b32_e32 v6, v16, v6
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v28
|
|
; VI-NEXT: v_or_b32_e32 v7, v16, v7
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v37
|
|
; VI-NEXT: v_or_b32_e32 v8, v16, v8
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v35
|
|
; VI-NEXT: v_or_b32_e32 v9, v16, v9
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v34
|
|
; VI-NEXT: v_or_b32_e32 v10, v16, v10
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v33
|
|
; VI-NEXT: v_or_b32_e32 v11, v16, v11
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v31
|
|
; VI-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v36
|
|
; VI-NEXT: v_or_b32_e32 v13, v16, v13
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v21, 8, v21
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v17, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v18, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v2, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v19, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v1, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: v_or_b32_sdwa v21, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: v_or_b32_sdwa v0, v22, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v3
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; VI-NEXT: v_or_b32_sdwa v3, v22, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v21
|
|
; VI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v19
|
|
; VI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v18
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: .LBB98_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v32i16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:124
|
|
; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:120
|
|
; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:116
|
|
; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, v12
|
|
; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
|
|
; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
|
|
; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
|
|
; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
|
|
; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:108
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:100
|
|
; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:92
|
|
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
|
|
; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: s_waitcnt vmcnt(23)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(22)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v56, 8, v1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(21)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v45, 8, v2
|
|
; GFX9-NEXT: s_waitcnt vmcnt(20)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v61, 8, v3
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(18)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v33, 8, v5
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(15)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v8
|
|
; GFX9-NEXT: s_waitcnt vmcnt(14)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v9
|
|
; GFX9-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v10
|
|
; GFX9-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
|
|
; GFX9-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v32, 8, v12
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB98_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
|
|
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v26, v27, s6
|
|
; GFX9-NEXT: v_perm_b32 v8, v30, v36, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v47, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v55, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v12, v42, v41, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v43, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v14, v58, v57, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v34, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: ; implicit-def: $vgpr22
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v2, s7
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s7
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v3, v19, v3, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v16, v52, v54, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v5, v18, v5, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s7
|
|
; GFX9-NEXT: v_perm_b32 v6, v24, v25, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
|
|
; GFX9-NEXT: v_perm_b32 v7, v28, v29, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v59, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v60, v61 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v48, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v40, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v44, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v46, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v31, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v53, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; kill: killed $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: .LBB98_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB98_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v52
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v54
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 3, v53
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(9)
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v31
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v57
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v50, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v51, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v43
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v35, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v55
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v33, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v63
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v62
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v60
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v61, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v38, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v59
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v56, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v47
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v29
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v36
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v25
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v27
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v23
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
|
|
; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v3
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v2
|
|
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
|
|
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s6
|
|
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v33, v10, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v37, v11, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s6
|
|
; GFX9-NEXT: v_perm_b32 v14, v32, v14, s6
|
|
; GFX9-NEXT: v_perm_b32 v15, v31, v15, s6
|
|
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v19
|
|
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v4, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v3, v17, v3, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v18, v2, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v19, v1, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v21
|
|
; GFX9-NEXT: v_perm_b32 v0, v21, v0, s6
|
|
; GFX9-NEXT: .LBB98_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32i16:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1f
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB98_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB98_4
|
|
; GFX11-TRUE16-NEXT: .LBB98_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB98_3: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB98_2
|
|
; GFX11-TRUE16-NEXT: .LBB98_4: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.h, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v16.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v16.h
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32i16:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v33, v12
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v37, v11
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v49, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v9 :: v_dual_mov_b32 v34, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v32, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v36, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v5 :: v_dual_mov_b32 v38, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v4 :: v_dual_mov_b32 v50, v1
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1f
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:128
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:124
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:120
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:116
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:112
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:108
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:104
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:100
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:96
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:92
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:88
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:84
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:80
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:76
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:72
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:68
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v6, off, s32 offset:132
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:64
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v119, 8, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v117, 8, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v118, 8, v2
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v115, 8, v3
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v114, 8, v4
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v116, 8, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v84, 8, v7
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(15)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v65, 8, v8
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(14)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v80, 8, v9
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v112, 8, v10
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v113, 8, v11
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v103, 8, v12
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB98_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB98_4
|
|
; GFX11-FAKE16-NEXT: .LBB98_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB98_3: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v39, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v37, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v33, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v54, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v16, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v22, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v28, v29, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v30, v55, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v83
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v7, v6, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v66
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v84
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v101
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v96
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v70
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v65
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v69, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v112
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v113
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v80
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v98
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v82
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v12, v11, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v85
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v86
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v100
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v114
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v102
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v103
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v116
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v115
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v81, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v11, v118
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v117
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v18, v119
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v99, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v14, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v16, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v19, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v20, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v18, v21, 0x5040100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB98_2
|
|
; GFX11-FAKE16-NEXT: .LBB98_4: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v99, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v100, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v87
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v102, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v81, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v119, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v118, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v81, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v64
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v85, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v117, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v68, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v115, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v64, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v116, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v97, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v98, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v114, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v71
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v101, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v71, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v103, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v69, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v69, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v112, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v113, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v67
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v66, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v28, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v80, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v84, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v29
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v30, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v65, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v55
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v26, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v25
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v27
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v20, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v22, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v6, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v33, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v31, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v52
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v54, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v53
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v48
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v18, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v49, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v19, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v51, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v34, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v38, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v36, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v39
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v50
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v32
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v35
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v37
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v23, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v26, v21
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v27, v22
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v29, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v30, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v22, v21, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v3, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v16, v2, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v23, v19, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v26, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v17, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v25, v7, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v8, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v9, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v67, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v69, v11, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v12, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v68, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v64, v14, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v81, v15, 0x5040100
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v32i16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_writelane_b32 v40, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v40, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v40, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v40, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v40, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v40, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v40, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v40, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v40, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v40, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v40, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v40, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v40, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v40, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v40, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v40, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v40, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v40, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v40, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v40, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v40, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v40, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v40, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v40, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v40, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v40, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v40, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v40, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v40, s86, 28
|
|
; SI-NEXT: v_writelane_b32 v40, s87, 29
|
|
; SI-NEXT: v_writelane_b32 v40, s96, 30
|
|
; SI-NEXT: v_writelane_b32 v40, s97, 31
|
|
; SI-NEXT: v_writelane_b32 v40, s98, 32
|
|
; SI-NEXT: v_writelane_b32 v40, s99, 33
|
|
; SI-NEXT: v_writelane_b32 v40, s30, 34
|
|
; SI-NEXT: v_writelane_b32 v40, s31, 35
|
|
; SI-NEXT: v_readfirstlane_b32 s79, v28
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: s_mov_b32 s31, s16
|
|
; SI-NEXT: v_readfirstlane_b32 s89, v30
|
|
; SI-NEXT: v_readfirstlane_b32 s36, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s94, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s55, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s30, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s16, v24
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
|
|
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
|
|
; SI-NEXT: v_readfirstlane_b32 s95, v23
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v41, s29, 0
|
|
; SI-NEXT: v_writelane_b32 v41, s28, 1
|
|
; SI-NEXT: v_writelane_b32 v41, s23, 2
|
|
; SI-NEXT: v_writelane_b32 v41, s22, 3
|
|
; SI-NEXT: v_writelane_b32 v41, s21, 4
|
|
; SI-NEXT: v_writelane_b32 v41, s20, 5
|
|
; SI-NEXT: v_readfirstlane_b32 s64, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s66, v21
|
|
; SI-NEXT: v_readfirstlane_b32 s81, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s82, v19
|
|
; SI-NEXT: v_readfirstlane_b32 s68, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s39, v17
|
|
; SI-NEXT: v_readfirstlane_b32 s52, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s65, v15
|
|
; SI-NEXT: v_readfirstlane_b32 s48, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s50, v13
|
|
; SI-NEXT: v_readfirstlane_b32 s70, v12
|
|
; SI-NEXT: v_readfirstlane_b32 s71, v11
|
|
; SI-NEXT: v_readfirstlane_b32 s37, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s29, v9
|
|
; SI-NEXT: v_readfirstlane_b32 s93, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s28, v7
|
|
; SI-NEXT: v_readfirstlane_b32 s38, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s49, v5
|
|
; SI-NEXT: v_readfirstlane_b32 s51, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s53, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s67, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s90, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s91, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_readfirstlane_b32 s47, v24
|
|
; SI-NEXT: v_readfirstlane_b32 s86, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s99, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v29
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_readfirstlane_b32 s78, v30
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_readfirstlane_b32 s88, v31
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_readfirstlane_b32 s21, v32
|
|
; SI-NEXT: s_waitcnt vmcnt(10)
|
|
; SI-NEXT: v_readfirstlane_b32 s98, v33
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_readfirstlane_b32 s96, v34
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
|
|
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_readfirstlane_b32 s34, v35
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_readfirstlane_b32 s83, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_readfirstlane_b32 s20, v37
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_readfirstlane_b32 s84, v38
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v39
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_readfirstlane_b32 s87, v48
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_readfirstlane_b32 s85, v49
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_readfirstlane_b32 s69, v50
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s35, v51
|
|
; SI-NEXT: v_writelane_b32 v41, s47, 6
|
|
; SI-NEXT: v_writelane_b32 v41, s58, 7
|
|
; SI-NEXT: s_cbranch_scc0 .LBB99_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s31, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_or_b32 s12, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xff
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 16
|
|
; SI-NEXT: s_lshl_b32 s5, s19, 24
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s25, 8
|
|
; SI-NEXT: s_or_b32 s13, s5, s6
|
|
; SI-NEXT: s_and_b32 s5, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s27, 24
|
|
; SI-NEXT: s_or_b32 s6, s6, s5
|
|
; SI-NEXT: s_and_b32 s5, s67, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s53, 8
|
|
; SI-NEXT: s_or_b32 s14, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s51, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s49, 24
|
|
; SI-NEXT: s_or_b32 s8, s7, s5
|
|
; SI-NEXT: s_and_b32 s5, s37, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s71, 8
|
|
; SI-NEXT: s_or_b32 s15, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s70, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s50, 24
|
|
; SI-NEXT: s_or_b32 s10, s7, s5
|
|
; SI-NEXT: s_and_b32 s5, s68, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s82, 8
|
|
; SI-NEXT: s_or_b32 s40, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s81, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s66, 24
|
|
; SI-NEXT: s_or_b32 s60, s7, s5
|
|
; SI-NEXT: s_and_b32 s5, s55, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s94, 8
|
|
; SI-NEXT: s_or_b32 s41, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s79, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s36, 24
|
|
; SI-NEXT: s_or_b32 s62, s7, s5
|
|
; SI-NEXT: s_and_b32 s5, s87, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s44, 8
|
|
; SI-NEXT: s_or_b32 s42, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s21, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s88, 8
|
|
; SI-NEXT: s_or_b32 s43, s5, s7
|
|
; SI-NEXT: v_readlane_b32 s5, v41, 5
|
|
; SI-NEXT: v_readlane_b32 s7, v41, 4
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 8
|
|
; SI-NEXT: s_or_b32 s5, s5, s7
|
|
; SI-NEXT: v_readlane_b32 s7, v41, 3
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xff
|
|
; SI-NEXT: v_readlane_b32 s9, v41, 2
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 24
|
|
; SI-NEXT: s_or_b32 s57, s9, s7
|
|
; SI-NEXT: v_readlane_b32 s7, v41, 1
|
|
; SI-NEXT: v_readlane_b32 s9, v41, 0
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s91, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s90, 24
|
|
; SI-NEXT: s_or_b32 s77, s11, s9
|
|
; SI-NEXT: s_and_b32 s9, s38, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s28, 8
|
|
; SI-NEXT: s_or_b32 s9, s9, s11
|
|
; SI-NEXT: s_and_b32 s11, s93, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 16
|
|
; SI-NEXT: v_writelane_b32 v41, s44, 12
|
|
; SI-NEXT: s_lshl_b32 s44, s29, 24
|
|
; SI-NEXT: s_or_b32 vcc_lo, s44, s11
|
|
; SI-NEXT: s_and_b32 s11, s48, 0xff
|
|
; SI-NEXT: s_lshl_b32 s44, s65, 8
|
|
; SI-NEXT: s_or_b32 s11, s11, s44
|
|
; SI-NEXT: s_and_b32 s44, s52, 0xff
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: s_lshl_b32 s45, s39, 24
|
|
; SI-NEXT: s_or_b32 vcc_hi, s45, s44
|
|
; SI-NEXT: s_and_b32 s44, s64, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s95, 8
|
|
; SI-NEXT: s_or_b32 s44, s44, s45
|
|
; SI-NEXT: s_and_b32 s45, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_mov_b32 s59, s46
|
|
; SI-NEXT: s_lshl_b32 s46, s30, 24
|
|
; SI-NEXT: v_writelane_b32 v41, s55, 13
|
|
; SI-NEXT: s_and_b32 s44, s44, 0xffff
|
|
; SI-NEXT: v_writelane_b32 v41, s79, 14
|
|
; SI-NEXT: s_or_b32 s79, s46, s45
|
|
; SI-NEXT: s_or_b32 s61, s44, s79
|
|
; SI-NEXT: s_and_b32 s44, s89, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s35, 8
|
|
; SI-NEXT: s_or_b32 s44, s44, s45
|
|
; SI-NEXT: s_and_b32 s45, s69, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s85, 24
|
|
; SI-NEXT: s_and_b32 s44, s44, 0xffff
|
|
; SI-NEXT: s_mov_b32 s23, s21
|
|
; SI-NEXT: s_mov_b32 s21, s87
|
|
; SI-NEXT: s_mov_b32 s87, s18
|
|
; SI-NEXT: s_or_b32 s18, s46, s45
|
|
; SI-NEXT: s_or_b32 s63, s44, s18
|
|
; SI-NEXT: s_and_b32 s44, s83, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s34, 8
|
|
; SI-NEXT: s_or_b32 s44, s44, s45
|
|
; SI-NEXT: s_and_b32 s45, s96, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s98, 24
|
|
; SI-NEXT: s_mov_b32 s56, s83
|
|
; SI-NEXT: s_mov_b32 s83, s64
|
|
; SI-NEXT: s_mov_b32 s64, s39
|
|
; SI-NEXT: s_mov_b32 s39, s91
|
|
; SI-NEXT: s_mov_b32 s91, s19
|
|
; SI-NEXT: s_or_b32 s19, s46, s45
|
|
; SI-NEXT: s_and_b32 s45, s84, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s20, 24
|
|
; SI-NEXT: s_and_b32 s44, s44, 0xffff
|
|
; SI-NEXT: s_or_b32 s72, s46, s45
|
|
; SI-NEXT: s_or_b32 s73, s44, s19
|
|
; SI-NEXT: s_and_b32 s44, s99, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s58, 8
|
|
; SI-NEXT: s_or_b32 s44, s44, s45
|
|
; SI-NEXT: s_and_b32 s45, s86, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s47, 24
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_mov_b32 s76, s20
|
|
; SI-NEXT: s_mov_b32 s20, s84
|
|
; SI-NEXT: s_mov_b32 s84, s81
|
|
; SI-NEXT: s_mov_b32 s81, s70
|
|
; SI-NEXT: s_mov_b32 s70, s65
|
|
; SI-NEXT: s_mov_b32 s65, s49
|
|
; SI-NEXT: s_mov_b32 s49, s90
|
|
; SI-NEXT: s_mov_b32 s90, s17
|
|
; SI-NEXT: s_or_b32 s17, s46, s45
|
|
; SI-NEXT: s_and_b32 s45, s78, 0xff
|
|
; SI-NEXT: s_or_b32 s5, s5, s57
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s59, 24
|
|
; SI-NEXT: s_and_b32 s44, s44, 0xffff
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s74, s46, s45
|
|
; SI-NEXT: s_or_b32 s75, s44, s17
|
|
; SI-NEXT: s_mov_b32 s46, s28
|
|
; SI-NEXT: s_and_b32 s28, s42, 0xffff
|
|
; SI-NEXT: s_mov_b32 s44, s30
|
|
; SI-NEXT: s_mov_b32 s30, s26
|
|
; SI-NEXT: s_and_b32 s26, s43, 0xffff
|
|
; SI-NEXT: s_or_b32 s42, s12, s4
|
|
; SI-NEXT: s_mov_b32 s43, s5
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s77
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 8
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 9
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
|
|
; SI-NEXT: s_or_b32 s9, s9, vcc_lo
|
|
; SI-NEXT: s_or_b32 s11, s11, vcc_hi
|
|
; SI-NEXT: s_mov_b32 s92, s16
|
|
; SI-NEXT: s_mov_b32 s97, s48
|
|
; SI-NEXT: s_mov_b32 s48, s29
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: s_and_b32 s58, s15, 0xffff
|
|
; SI-NEXT: s_and_b32 s16, s40, 0xffff
|
|
; SI-NEXT: s_and_b32 s29, s41, 0xffff
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 10
|
|
; SI-NEXT: s_mov_b32 s22, s51
|
|
; SI-NEXT: s_mov_b32 s51, s93
|
|
; SI-NEXT: s_mov_b32 s45, s99
|
|
; SI-NEXT: s_mov_b32 s99, s96
|
|
; SI-NEXT: s_mov_b32 s96, s82
|
|
; SI-NEXT: s_mov_b32 s82, s95
|
|
; SI-NEXT: s_mov_b32 s95, s94
|
|
; SI-NEXT: s_mov_b32 s94, s92
|
|
; SI-NEXT: s_or_b32 s40, s13, s6
|
|
; SI-NEXT: s_mov_b32 s41, s7
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 11
|
|
; SI-NEXT: s_or_b32 s14, s14, s8
|
|
; SI-NEXT: s_mov_b32 s15, s9
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
|
|
; SI-NEXT: s_or_b32 s12, s58, s10
|
|
; SI-NEXT: s_mov_b32 s13, s11
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[10:11], 16
|
|
; SI-NEXT: s_or_b32 s10, s16, s60
|
|
; SI-NEXT: s_mov_b32 s11, s61
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
|
|
; SI-NEXT: s_or_b32 s8, s29, s62
|
|
; SI-NEXT: s_mov_b32 s9, s63
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[62:63], 16
|
|
; SI-NEXT: s_or_b32 s6, s28, s72
|
|
; SI-NEXT: s_mov_b32 s7, s73
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[72:73], 16
|
|
; SI-NEXT: s_or_b32 s4, s26, s74
|
|
; SI-NEXT: s_mov_b32 s5, s75
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16
|
|
; SI-NEXT: s_mov_b32 s16, s94
|
|
; SI-NEXT: s_mov_b32 s94, s95
|
|
; SI-NEXT: s_mov_b32 s95, s82
|
|
; SI-NEXT: s_mov_b32 s82, s96
|
|
; SI-NEXT: s_mov_b32 s96, s99
|
|
; SI-NEXT: s_mov_b32 s99, s45
|
|
; SI-NEXT: s_mov_b32 s28, s46
|
|
; SI-NEXT: s_mov_b32 s46, s59
|
|
; SI-NEXT: s_mov_b32 s26, s30
|
|
; SI-NEXT: s_mov_b32 s30, s44
|
|
; SI-NEXT: v_readlane_b32 s44, v41, 12
|
|
; SI-NEXT: s_lshr_b32 s47, s57, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s77, 16
|
|
; SI-NEXT: s_lshr_b32 s59, vcc_lo, 16
|
|
; SI-NEXT: s_lshr_b32 s61, vcc_hi, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s79, 16
|
|
; SI-NEXT: v_readlane_b32 s79, v41, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v41, 13
|
|
; SI-NEXT: s_lshr_b32 s73, s18, 16
|
|
; SI-NEXT: s_mov_b32 s18, s87
|
|
; SI-NEXT: s_mov_b32 s29, s48
|
|
; SI-NEXT: s_mov_b32 s48, s97
|
|
; SI-NEXT: s_mov_b32 s87, s21
|
|
; SI-NEXT: s_mov_b32 s21, s23
|
|
; SI-NEXT: s_mov_b32 s93, s51
|
|
; SI-NEXT: s_mov_b32 s51, s22
|
|
; SI-NEXT: s_lshr_b32 s75, s19, 16
|
|
; SI-NEXT: s_mov_b32 s19, s91
|
|
; SI-NEXT: s_mov_b32 s91, s39
|
|
; SI-NEXT: s_mov_b32 s39, s64
|
|
; SI-NEXT: s_mov_b32 s64, s83
|
|
; SI-NEXT: s_mov_b32 s83, s56
|
|
; SI-NEXT: s_lshr_b32 s45, s17, 16
|
|
; SI-NEXT: s_mov_b32 s17, s90
|
|
; SI-NEXT: s_mov_b32 s90, s49
|
|
; SI-NEXT: s_mov_b32 s49, s65
|
|
; SI-NEXT: s_mov_b32 s65, s70
|
|
; SI-NEXT: s_mov_b32 s70, s81
|
|
; SI-NEXT: s_mov_b32 s81, s84
|
|
; SI-NEXT: s_mov_b32 s84, s20
|
|
; SI-NEXT: s_mov_b32 s20, s76
|
|
; SI-NEXT: s_mov_b64 s[76:77], 0
|
|
; SI-NEXT: s_branch .LBB99_3
|
|
; SI-NEXT: .LBB99_2:
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: s_mov_b64 s[76:77], -1
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 8
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 9
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 10
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 11
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: .LBB99_3: ; %Flow
|
|
; SI-NEXT: s_andn2_b64 vcc, exec, s[76:77]
|
|
; SI-NEXT: v_readlane_b32 s76, v41, 8
|
|
; SI-NEXT: v_readlane_b32 s77, v41, 9
|
|
; SI-NEXT: s_mov_b32 s22, s76
|
|
; SI-NEXT: v_readlane_b32 s76, v41, 10
|
|
; SI-NEXT: s_mov_b32 s56, s76
|
|
; SI-NEXT: v_readlane_b32 s77, v41, 11
|
|
; SI-NEXT: s_cbranch_vccnz .LBB99_5
|
|
; SI-NEXT: ; %bb.4: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s88, 8
|
|
; SI-NEXT: s_add_i32 s78, s78, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s6, s78, 0xff
|
|
; SI-NEXT: s_addk_i32 s4, 0x300
|
|
; SI-NEXT: s_lshl_b32 s5, s46, 24
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s5, s6
|
|
; SI-NEXT: s_add_i32 s99, s99, 3
|
|
; SI-NEXT: v_readlane_b32 s6, v41, 7
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s99, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 8
|
|
; SI-NEXT: s_add_i32 s86, s86, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: v_readlane_b32 s6, v41, 6
|
|
; SI-NEXT: s_and_b32 s7, s86, 0xff
|
|
; SI-NEXT: s_addk_i32 s5, 0x300
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 24
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: s_add_i32 s97, s87, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: s_and_b32 s6, s97, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s44, 8
|
|
; SI-NEXT: s_add_i32 s84, s84, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s8, s84, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s20, 24
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s8
|
|
; SI-NEXT: s_add_i32 s83, s83, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s7, s83, 0xff
|
|
; SI-NEXT: s_lshl_b32 s8, s34, 8
|
|
; SI-NEXT: s_add_i32 s80, s96, 3
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: s_and_b32 s9, s80, 0xff
|
|
; SI-NEXT: s_addk_i32 s7, 0x300
|
|
; SI-NEXT: s_lshl_b32 s8, s98, 24
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: s_add_i32 s55, s55, 3
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: s_and_b32 s8, s55, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s94, 8
|
|
; SI-NEXT: s_add_i32 s88, s79, 3
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_and_b32 s10, s88, 0xff
|
|
; SI-NEXT: s_addk_i32 s8, 0x300
|
|
; SI-NEXT: s_lshl_b32 s9, s36, 24
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s9, s10
|
|
; SI-NEXT: s_add_i32 s20, s89, 3
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_and_b32 s9, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s10, s35, 8
|
|
; SI-NEXT: s_add_i32 s69, s69, 3
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: s_and_b32 s11, s69, 0xff
|
|
; SI-NEXT: s_addk_i32 s9, 0x300
|
|
; SI-NEXT: s_lshl_b32 s10, s85, 24
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 16
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_or_b32 s10, s10, s11
|
|
; SI-NEXT: s_add_i32 s68, s68, 3
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: s_and_b32 s10, s68, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s82, 8
|
|
; SI-NEXT: s_or_b32 s10, s11, s10
|
|
; SI-NEXT: s_lshl_b32 s11, s66, 24
|
|
; SI-NEXT: s_add_i32 s66, s81, 3
|
|
; SI-NEXT: s_and_b32 s12, s66, 0xff
|
|
; SI-NEXT: s_addk_i32 s10, 0x300
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xffff
|
|
; SI-NEXT: s_or_b32 s11, s11, s12
|
|
; SI-NEXT: s_add_i32 s64, s64, 3
|
|
; SI-NEXT: s_or_b32 s10, s11, s10
|
|
; SI-NEXT: s_and_b32 s11, s64, 0xff
|
|
; SI-NEXT: s_lshl_b32 s12, s95, 8
|
|
; SI-NEXT: s_add_i32 s94, s16, 3
|
|
; SI-NEXT: s_or_b32 s11, s12, s11
|
|
; SI-NEXT: s_and_b32 s13, s94, 0xff
|
|
; SI-NEXT: s_addk_i32 s11, 0x300
|
|
; SI-NEXT: s_lshl_b32 s12, s30, 24
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; SI-NEXT: s_or_b32 s12, s12, s13
|
|
; SI-NEXT: s_add_i32 s54, s37, 3
|
|
; SI-NEXT: s_or_b32 s11, s12, s11
|
|
; SI-NEXT: s_and_b32 s12, s54, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s71, 8
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: s_lshl_b32 s13, s50, 24
|
|
; SI-NEXT: s_add_i32 s50, s70, 3
|
|
; SI-NEXT: s_and_b32 s14, s50, 0xff
|
|
; SI-NEXT: s_addk_i32 s12, 0x300
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_or_b32 s13, s13, s14
|
|
; SI-NEXT: s_add_i32 s48, s48, 3
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: s_and_b32 s13, s48, 0xff
|
|
; SI-NEXT: s_lshl_b32 s14, s65, 8
|
|
; SI-NEXT: s_add_i32 s36, s52, 3
|
|
; SI-NEXT: s_or_b32 s13, s14, s13
|
|
; SI-NEXT: s_and_b32 s15, s36, 0xff
|
|
; SI-NEXT: s_addk_i32 s13, 0x300
|
|
; SI-NEXT: s_lshl_b32 s14, s39, 24
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 16
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_or_b32 s14, s14, s15
|
|
; SI-NEXT: s_add_i32 s39, s67, 3
|
|
; SI-NEXT: s_or_b32 s13, s14, s13
|
|
; SI-NEXT: s_and_b32 s14, s39, 0xff
|
|
; SI-NEXT: s_lshl_b32 s15, s53, 8
|
|
; SI-NEXT: s_add_i32 s34, s51, 3
|
|
; SI-NEXT: s_or_b32 s14, s15, s14
|
|
; SI-NEXT: s_and_b32 s20, s34, 0xff
|
|
; SI-NEXT: s_addk_i32 s14, 0x300
|
|
; SI-NEXT: s_lshl_b32 s15, s49, 24
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: s_or_b32 s15, s15, s20
|
|
; SI-NEXT: s_add_i32 s30, s38, 3
|
|
; SI-NEXT: s_or_b32 s14, s15, s14
|
|
; SI-NEXT: s_and_b32 s15, s30, 0xff
|
|
; SI-NEXT: s_lshl_b32 s20, s28, 8
|
|
; SI-NEXT: s_add_i32 s92, s93, 3
|
|
; SI-NEXT: s_or_b32 s15, s20, s15
|
|
; SI-NEXT: s_and_b32 s21, s92, 0xff
|
|
; SI-NEXT: s_addk_i32 s15, 0x300
|
|
; SI-NEXT: s_lshl_b32 s20, s29, 24
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_or_b32 s15, s20, s15
|
|
; SI-NEXT: s_and_b32 s20, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s21, s25, 8
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s24, s26, 0xff
|
|
; SI-NEXT: s_add_i32 s16, s31, 3
|
|
; SI-NEXT: s_addk_i32 s20, 0x300
|
|
; SI-NEXT: s_lshl_b32 s21, s27, 24
|
|
; SI-NEXT: s_lshl_b32 s24, s24, 16
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_and_b32 s20, s20, 0xffff
|
|
; SI-NEXT: s_or_b32 s21, s21, s24
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xff
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_addk_i32 s16, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s19, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_add_i32 s40, s20, 0x3000000
|
|
; SI-NEXT: v_readlane_b32 s20, v41, 1
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s28, s20, 3
|
|
; SI-NEXT: v_readlane_b32 s21, v41, 0
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s20, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 8
|
|
; SI-NEXT: s_add_i32 s42, s16, 0x3000000
|
|
; SI-NEXT: v_readlane_b32 s16, v41, 5
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_lshl_b32 s21, s90, 24
|
|
; SI-NEXT: s_add_i32 s90, s91, 3
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: v_readlane_b32 s17, v41, 4
|
|
; SI-NEXT: v_readlane_b32 s18, v41, 3
|
|
; SI-NEXT: s_and_b32 s24, s90, 0xff
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_addk_i32 s20, 0x300
|
|
; SI-NEXT: s_lshl_b32 s24, s24, 16
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: v_readlane_b32 s17, v41, 2
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xff
|
|
; SI-NEXT: s_and_b32 s20, s20, 0xffff
|
|
; SI-NEXT: s_or_b32 s21, s21, s24
|
|
; SI-NEXT: s_addk_i32 s16, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
|
|
; SI-NEXT: s_add_i32 s6, s6, 0x3000000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
|
|
; SI-NEXT: s_add_i32 s8, s8, 0x3000000
|
|
; SI-NEXT: s_add_i32 s9, s9, 0x3000000
|
|
; SI-NEXT: s_add_i32 s10, s10, 0x3000000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
|
|
; SI-NEXT: s_add_i32 s41, s20, 0x3000000
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
|
|
; SI-NEXT: s_add_i32 s13, s13, 0x3000000
|
|
; SI-NEXT: s_add_i32 s14, s14, 0x3000000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
|
|
; SI-NEXT: s_add_i32 s43, s16, 0x3000000
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[8:9], 16
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[22:23], s[42:43], 16
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[14:15], 16
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b32 s47, s43, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s41, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s15, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s13, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s11, 16
|
|
; SI-NEXT: s_lshr_b32 s73, s9, 16
|
|
; SI-NEXT: s_lshr_b32 s75, s7, 16
|
|
; SI-NEXT: s_lshr_b32 s45, s5, 16
|
|
; SI-NEXT: .LBB99_5: ; %end
|
|
; SI-NEXT: s_and_b32 s16, s42, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s17, s22, 16
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s43, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s18, s47, 16
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_and_b32 s18, s40, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s19, s56, 16
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_and_b32 s19, s41, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s57, 16
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s54, 16
|
|
; SI-NEXT: s_or_b32 s14, s14, s20
|
|
; SI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s59, 16
|
|
; SI-NEXT: s_or_b32 s15, s15, s20
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s92, 16
|
|
; SI-NEXT: s_or_b32 s12, s12, s20
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s61, 16
|
|
; SI-NEXT: s_or_b32 s13, s13, s20
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s60, 16
|
|
; SI-NEXT: s_or_b32 s10, s10, s20
|
|
; SI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s63, 16
|
|
; SI-NEXT: s_or_b32 s11, s11, s20
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s62, 16
|
|
; SI-NEXT: s_or_b32 s8, s8, s20
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s73, 16
|
|
; SI-NEXT: s_or_b32 s9, s9, s20
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s72, 16
|
|
; SI-NEXT: s_or_b32 s6, s6, s20
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s75, 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s20
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s74, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s20
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s45, 16
|
|
; SI-NEXT: s_or_b32 s5, s5, s20
|
|
; SI-NEXT: v_readlane_b32 s30, v40, 34
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s14
|
|
; SI-NEXT: v_mov_b32_e32 v5, s15
|
|
; SI-NEXT: v_mov_b32_e32 v6, s12
|
|
; SI-NEXT: v_mov_b32_e32 v7, s13
|
|
; SI-NEXT: v_mov_b32_e32 v8, s10
|
|
; SI-NEXT: v_mov_b32_e32 v9, s11
|
|
; SI-NEXT: v_mov_b32_e32 v10, s8
|
|
; SI-NEXT: v_mov_b32_e32 v11, s9
|
|
; SI-NEXT: v_mov_b32_e32 v12, s6
|
|
; SI-NEXT: v_mov_b32_e32 v13, s7
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: v_readlane_b32 s31, v40, 35
|
|
; SI-NEXT: v_readlane_b32 s99, v40, 33
|
|
; SI-NEXT: v_readlane_b32 s98, v40, 32
|
|
; SI-NEXT: v_readlane_b32 s97, v40, 31
|
|
; SI-NEXT: v_readlane_b32 s96, v40, 30
|
|
; SI-NEXT: v_readlane_b32 s87, v40, 29
|
|
; SI-NEXT: v_readlane_b32 s86, v40, 28
|
|
; SI-NEXT: v_readlane_b32 s85, v40, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v40, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v40, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v40, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v40, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v40, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v40, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v40, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v40, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v40, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v40, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v40, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v40, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v40, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v40, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v40, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v40, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v40, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v40, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v40, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v40, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v40, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v40, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v40, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v40, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v40, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v40, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v40, 0
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v32i16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s41, v30
|
|
; VI-NEXT: v_readfirstlane_b32 s14, v29
|
|
; VI-NEXT: v_readfirstlane_b32 s40, v28
|
|
; VI-NEXT: v_readfirstlane_b32 s12, v27
|
|
; VI-NEXT: v_readfirstlane_b32 s15, v26
|
|
; VI-NEXT: v_readfirstlane_b32 s10, v25
|
|
; VI-NEXT: v_readfirstlane_b32 s13, v24
|
|
; VI-NEXT: v_readfirstlane_b32 s8, v23
|
|
; VI-NEXT: v_readfirstlane_b32 s11, v22
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v21
|
|
; VI-NEXT: v_readfirstlane_b32 s9, v20
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v19
|
|
; VI-NEXT: v_readfirstlane_b32 s44, v18
|
|
; VI-NEXT: v_readfirstlane_b32 s42, v17
|
|
; VI-NEXT: v_readfirstlane_b32 s43, v16
|
|
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: v_readfirstlane_b32 s74, v15
|
|
; VI-NEXT: v_readfirstlane_b32 s76, v14
|
|
; VI-NEXT: v_readfirstlane_b32 s72, v13
|
|
; VI-NEXT: v_readfirstlane_b32 s75, v12
|
|
; VI-NEXT: v_readfirstlane_b32 s62, v11
|
|
; VI-NEXT: v_readfirstlane_b32 s73, v10
|
|
; VI-NEXT: v_readfirstlane_b32 s60, v9
|
|
; VI-NEXT: v_readfirstlane_b32 s63, v8
|
|
; VI-NEXT: v_readfirstlane_b32 s58, v7
|
|
; VI-NEXT: v_readfirstlane_b32 s61, v6
|
|
; VI-NEXT: v_readfirstlane_b32 s47, v5
|
|
; VI-NEXT: v_readfirstlane_b32 s59, v4
|
|
; VI-NEXT: v_readfirstlane_b32 s46, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s56, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s45, v1
|
|
; VI-NEXT: v_readfirstlane_b32 s57, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; VI-NEXT: s_cbranch_scc0 .LBB99_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_mov_b32_e32 v3, s23
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_mov_b32_e32 v2, s21
|
|
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s45
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: v_perm_b32 v4, s57, v4, v11
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_mov_b32_e32 v5, s47
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_mov_b32_e32 v4, s46
|
|
; VI-NEXT: v_perm_b32 v5, s59, v5, v11
|
|
; VI-NEXT: v_perm_b32 v4, s56, v4, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_mov_b32_e32 v6, s60
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_mov_b32_e32 v5, s58
|
|
; VI-NEXT: v_perm_b32 v6, s63, v6, v11
|
|
; VI-NEXT: v_perm_b32 v5, s61, v5, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_mov_b32_e32 v7, s72
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_mov_b32_e32 v6, s62
|
|
; VI-NEXT: v_perm_b32 v7, s75, v7, v11
|
|
; VI-NEXT: v_perm_b32 v6, s73, v6, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_mov_b32_e32 v8, s42
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_mov_b32_e32 v7, s74
|
|
; VI-NEXT: v_perm_b32 v8, s43, v8, v11
|
|
; VI-NEXT: v_perm_b32 v7, s76, v7, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_mov_b32_e32 v9, s7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_mov_b32_e32 v8, s6
|
|
; VI-NEXT: v_perm_b32 v9, s9, v9, v11
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_mov_b32_e32 v10, s10
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_mov_b32_e32 v9, s8
|
|
; VI-NEXT: v_perm_b32 v10, s13, v10, v11
|
|
; VI-NEXT: v_perm_b32 v9, s11, v9, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_mov_b32_e32 v12, s14
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_mov_b32_e32 v10, s12
|
|
; VI-NEXT: v_perm_b32 v12, s40, v12, v11
|
|
; VI-NEXT: v_perm_b32 v10, s15, v10, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; VI-NEXT: v_perm_b32 v12, v18, v17, s4
|
|
; VI-NEXT: v_perm_b32 v11, s41, v16, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
|
|
; VI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
|
|
; VI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
|
|
; VI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
|
|
; VI-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; VI-NEXT: s_cbranch_execnz .LBB99_3
|
|
; VI-NEXT: .LBB99_2: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v8, v0, v31, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(12)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v33
|
|
; VI-NEXT: v_perm_b32 v9, v0, v28, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(10)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v32
|
|
; VI-NEXT: v_perm_b32 v10, v0, v26, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(8)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v29
|
|
; VI-NEXT: v_perm_b32 v11, v0, v23, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(6)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v30
|
|
; VI-NEXT: v_perm_b32 v12, v0, v24, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v27
|
|
; VI-NEXT: v_perm_b32 v13, v0, v21, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v25
|
|
; VI-NEXT: v_perm_b32 v14, v0, v20, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v22
|
|
; VI-NEXT: v_perm_b32 v15, v0, v19, s4
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v18
|
|
; VI-NEXT: v_perm_b32 v17, v0, v17, s4
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
|
|
; VI-NEXT: s_add_i32 s40, s40, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s14
|
|
; VI-NEXT: v_perm_b32 v18, s40, v1, v0
|
|
; VI-NEXT: s_add_i32 s15, s15, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s12
|
|
; VI-NEXT: v_perm_b32 v19, s15, v1, v0
|
|
; VI-NEXT: s_add_i32 s13, s13, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s10
|
|
; VI-NEXT: v_perm_b32 v20, s13, v1, v0
|
|
; VI-NEXT: s_add_i32 s11, s11, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s8
|
|
; VI-NEXT: v_perm_b32 v21, s11, v1, v0
|
|
; VI-NEXT: s_add_i32 s9, s9, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
; VI-NEXT: v_perm_b32 v22, s9, v1, v0
|
|
; VI-NEXT: s_add_i32 s44, s44, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s6
|
|
; VI-NEXT: v_perm_b32 v23, s44, v1, v0
|
|
; VI-NEXT: s_add_i32 s43, s43, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s42
|
|
; VI-NEXT: v_perm_b32 v7, s43, v1, v0
|
|
; VI-NEXT: s_add_i32 s76, s76, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s74
|
|
; VI-NEXT: v_perm_b32 v24, s76, v1, v0
|
|
; VI-NEXT: s_add_i32 s75, s75, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s72
|
|
; VI-NEXT: v_perm_b32 v6, s75, v1, v0
|
|
; VI-NEXT: s_add_i32 s73, s73, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s62
|
|
; VI-NEXT: v_perm_b32 v25, s73, v1, v0
|
|
; VI-NEXT: s_add_i32 s63, s63, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s60
|
|
; VI-NEXT: v_perm_b32 v5, s63, v1, v0
|
|
; VI-NEXT: s_add_i32 s61, s61, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s58
|
|
; VI-NEXT: v_perm_b32 v26, s61, v1, v0
|
|
; VI-NEXT: s_add_i32 s59, s59, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s47
|
|
; VI-NEXT: v_perm_b32 v4, s59, v1, v0
|
|
; VI-NEXT: s_add_i32 s56, s56, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s46
|
|
; VI-NEXT: v_perm_b32 v27, s56, v1, v0
|
|
; VI-NEXT: s_add_i32 s57, s57, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s45
|
|
; VI-NEXT: v_perm_b32 v3, s57, v1, v0
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s29
|
|
; VI-NEXT: v_perm_b32 v28, s28, v1, v0
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s27
|
|
; VI-NEXT: v_perm_b32 v2, s26, v1, v0
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s25
|
|
; VI-NEXT: s_add_i32 s41, s41, 3
|
|
; VI-NEXT: v_perm_b32 v29, s24, v1, v0
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s23
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: v_mov_b32_e32 v30, s21
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: v_mov_b32_e32 v31, s19
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: v_mov_b32_e32 v32, s17
|
|
; VI-NEXT: v_perm_b32 v16, s41, v16, v0
|
|
; VI-NEXT: v_perm_b32 v1, s22, v1, v0
|
|
; VI-NEXT: v_perm_b32 v30, s20, v30, v0
|
|
; VI-NEXT: v_perm_b32 v31, s18, v31, v0
|
|
; VI-NEXT: v_perm_b32 v0, s16, v32, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, 0x300, v28
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, 0x300, v27
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, 0x300, v26
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x300, v25
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, 0x300, v24
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, 0x300, v30
|
|
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x300, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, 0x300, v29
|
|
; VI-NEXT: v_or_b32_sdwa v3, v3, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v4, v4, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v5, v5, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v6, v6, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v7, v7, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v8
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x300, v9
|
|
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, 0x300, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x300, v13
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v14
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x300, v15
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v17
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x300, v16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v18
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x300, v19
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v20
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x300, v21
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x300, v23
|
|
; VI-NEXT: v_or_b32_sdwa v0, v31, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v1, v1, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v2, v2, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v8, v8, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v9, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v10, v10, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v11, v11, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v12, v12, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v13, v28, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v14, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v15, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x3000000, v3
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x3000000, v4
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x3000000, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x3000000, v6
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x3000000, v10
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x3000000, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x3000000, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x3000000, v13
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x3000000, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x3000000, v15
|
|
; VI-NEXT: .LBB99_3: ; %end
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB99_4:
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_branch .LBB99_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v32i16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s72, v30
|
|
; GFX9-NEXT: v_readfirstlane_b32 s56, v29
|
|
; GFX9-NEXT: v_readfirstlane_b32 s57, v28
|
|
; GFX9-NEXT: v_readfirstlane_b32 s61, v27
|
|
; GFX9-NEXT: v_readfirstlane_b32 s63, v26
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v25
|
|
; GFX9-NEXT: v_readfirstlane_b32 s47, v24
|
|
; GFX9-NEXT: v_readfirstlane_b32 s58, v23
|
|
; GFX9-NEXT: v_readfirstlane_b32 s60, v22
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v21
|
|
; GFX9-NEXT: v_readfirstlane_b32 s8, v20
|
|
; GFX9-NEXT: v_readfirstlane_b32 s9, v19
|
|
; GFX9-NEXT: v_readfirstlane_b32 s10, v18
|
|
; GFX9-NEXT: v_readfirstlane_b32 s11, v17
|
|
; GFX9-NEXT: v_readfirstlane_b32 s12, v16
|
|
; GFX9-NEXT: v_readfirstlane_b32 s15, v12
|
|
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s13, v15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s73, v14
|
|
; GFX9-NEXT: v_readfirstlane_b32 s14, v13
|
|
; GFX9-NEXT: v_readfirstlane_b32 s40, v11
|
|
; GFX9-NEXT: v_readfirstlane_b32 s76, v10
|
|
; GFX9-NEXT: v_readfirstlane_b32 s41, v9
|
|
; GFX9-NEXT: v_readfirstlane_b32 s42, v8
|
|
; GFX9-NEXT: v_readfirstlane_b32 s43, v7
|
|
; GFX9-NEXT: v_readfirstlane_b32 s75, v6
|
|
; GFX9-NEXT: v_readfirstlane_b32 s44, v5
|
|
; GFX9-NEXT: v_readfirstlane_b32 s45, v4
|
|
; GFX9-NEXT: v_readfirstlane_b32 s46, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s74, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s59, v1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s62, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
|
|
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB99_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s59
|
|
; GFX9-NEXT: v_perm_b32 v4, s62, v4, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s46
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s44
|
|
; GFX9-NEXT: v_perm_b32 v5, s45, v5, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s43
|
|
; GFX9-NEXT: v_perm_b32 v5, s75, v5, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s41
|
|
; GFX9-NEXT: v_perm_b32 v6, s42, v6, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s40
|
|
; GFX9-NEXT: v_perm_b32 v6, s76, v6, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s14
|
|
; GFX9-NEXT: v_perm_b32 v7, s15, v7, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s13
|
|
; GFX9-NEXT: v_perm_b32 v7, s73, v7, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s11
|
|
; GFX9-NEXT: v_perm_b32 v9, s12, v9, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(18)
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v16
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v10, s72, v18, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v26
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v29, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v19
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v21, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v20
|
|
; GFX9-NEXT: v_perm_b32 v10, v31, v28, s4
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v23, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v30
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v33, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v22
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v25, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v24
|
|
; GFX9-NEXT: v_perm_b32 v10, v34, v32, s4
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v27, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s58
|
|
; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
|
|
; GFX9-NEXT: s_and_b32 s4, s47, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s5, s7, 8
|
|
; GFX9-NEXT: s_or_b32 s4, s4, s5
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
|
|
; GFX9-NEXT: s_and_b32 s4, s10, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s5, s9, 8
|
|
; GFX9-NEXT: s_or_b32 s4, s4, s5
|
|
; GFX9-NEXT: s_and_b32 s5, s8, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s77, s6, 8
|
|
; GFX9-NEXT: s_or_b32 s5, s5, s77
|
|
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
|
|
; GFX9-NEXT: s_and_b32 s5, s63, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s77, s61, 8
|
|
; GFX9-NEXT: s_or_b32 s5, s5, s77
|
|
; GFX9-NEXT: s_and_b32 s77, s57, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s78, s56, 8
|
|
; GFX9-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s5
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
|
|
; GFX9-NEXT: .LBB99_2: ; %cmp.true
|
|
; GFX9-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v34
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v8, v0, v32, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v27
|
|
; GFX9-NEXT: v_perm_b32 v9, v0, v24, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v33
|
|
; GFX9-NEXT: v_perm_b32 v10, v0, v30, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v25
|
|
; GFX9-NEXT: v_perm_b32 v11, v0, v22, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v31
|
|
; GFX9-NEXT: v_perm_b32 v12, v0, v28, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v23
|
|
; GFX9-NEXT: v_perm_b32 v13, v0, v20, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v29
|
|
; GFX9-NEXT: v_perm_b32 v14, v0, v26, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v21
|
|
; GFX9-NEXT: v_perm_b32 v15, v0, v19, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v17
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v16, v0, v16, s4
|
|
; GFX9-NEXT: s_add_i32 s63, s63, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s61
|
|
; GFX9-NEXT: v_perm_b32 v17, s63, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s57, s57, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s56
|
|
; GFX9-NEXT: v_perm_b32 v20, s57, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s58
|
|
; GFX9-NEXT: v_perm_b32 v21, s60, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s21
|
|
; GFX9-NEXT: v_perm_b32 v0, s20, v0, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 0x300, v0
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s23
|
|
; GFX9-NEXT: v_perm_b32 v0, s22, v0, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v0
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_perm_b32 v3, s18, v3, v19
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v19
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v19
|
|
; GFX9-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s59
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_perm_b32 v4, s62, v4, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX9-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s46
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v19
|
|
; GFX9-NEXT: s_add_i32 s45, s45, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s44
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_perm_b32 v5, s45, v5, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX9-NEXT: s_add_i32 s75, s75, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s43
|
|
; GFX9-NEXT: v_perm_b32 v5, s75, v5, v19
|
|
; GFX9-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s41
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_perm_b32 v6, s42, v6, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX9-NEXT: s_add_i32 s76, s76, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s40
|
|
; GFX9-NEXT: v_perm_b32 v6, s76, v6, v19
|
|
; GFX9-NEXT: s_add_i32 s15, s15, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s14
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_perm_b32 v7, s15, v7, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX9-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s13
|
|
; GFX9-NEXT: v_perm_b32 v7, s73, v7, v19
|
|
; GFX9-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s11
|
|
; GFX9-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_perm_b32 v22, s12, v22, v19
|
|
; GFX9-NEXT: v_perm_b32 v18, s72, v18, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v22, 0x300, v22
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX9-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v23, s9
|
|
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v14
|
|
; GFX9-NEXT: s_add_i32 s47, s47, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v22, 16, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s7
|
|
; GFX9-NEXT: v_perm_b32 v23, s10, v23, v19
|
|
; GFX9-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v24, s6
|
|
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v18
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX9-NEXT: v_perm_b32 v22, s47, v22, v19
|
|
; GFX9-NEXT: v_perm_b32 v19, s8, v24, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v24, 0x300, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v26, 0x300, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v16
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 0x300, v21
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 0x300, v23
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v14, 16, v12
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff, v28
|
|
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v20
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x300, v22
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x300, v19
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v15, 16, v11
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff, v26
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff, v24
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v18, 16, v8
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v17, 16, v9
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v16, 16, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v27, 16, v14
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v25, 16, v15
|
|
; GFX9-NEXT: .LBB99_3: ; %end
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB99_4:
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_branch .LBB99_2
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32i16_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0xf
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB99_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
|
|
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
|
|
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB99_3
|
|
; GFX11-TRUE16-NEXT: .LBB99_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v29, s2, s3, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v30, s18, s19, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v31, s16, s17, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v32, s0, s1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v24
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v29
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v31
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v29.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v30.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v27.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v28.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v24.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v26.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v25.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v23.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v22.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v21.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v20.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v19.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v18.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v17.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
|
|
; GFX11-TRUE16-NEXT: .LBB99_3: ; %end
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB99_4:
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB99_2
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32i16_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_clause 0xf
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v30
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v29
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v28
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v27
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v26
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v25
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v24
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v23
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v22
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v21
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v20
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v19
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v18
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v16
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v15
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v14
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v13
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v12
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v11
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v10
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v9
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v8
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v7
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v6
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v5
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v3
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v2
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB99_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s41, 8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s77, s44, 0xff
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s40, s13, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
|
|
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v16, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB99_3
|
|
; GFX11-FAKE16-NEXT: .LBB99_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v52
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v50
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v49
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s43, s43, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s74, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s56, s45, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s73, s63, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s44, s41, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s72, s62, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s60, s57, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s61, s61, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s43, s15, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s7, s5, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s61, s59, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s46, s42, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s12, s9, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s26, s27, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v28, s0, s1, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s58, s47, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s40, s13, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s24, s25, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s20, s21, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v29, s16, s17, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v30, s2, s3, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s10, s8, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s28, s29, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v29
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v31, s22, s23, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s18, s19, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v30, 16, v28
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v32
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v27, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v26, 16, v32
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v23, 16, v22
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v21, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v28
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v31, 16, v29
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v30
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v25, 16, v24
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v9, 16, v26
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v10, 16, v27
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v20, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v18, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v14, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v22
|
|
; GFX11-FAKE16-NEXT: .LBB99_3: ; %end
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB99_4:
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB99_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <32 x i16>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <32 x i16>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x i16> %phi
|
|
}
|
|
|
|
define <32 x bfloat> @bitcast_v32f16_to_v32bf16(<32 x half> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v32bf16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v57, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v56, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v45, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v44, 16, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v42, 16, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v41, 16, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB100_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v54
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v41
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v43
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v44
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v45
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v46
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v47
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v56
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v57
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v59
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v60
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v61
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v62
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v63
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: .LBB100_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB100_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v63
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v62
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v14
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v61
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v50, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v13
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v60
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v48, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v12
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v59
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v38, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v11
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v58
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v6
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v36, v16
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v39, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v57
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v34, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v56
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v54
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v32, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v47
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v30, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v46
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v28, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v45
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v26, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v44
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v24, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v43
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v52, v18
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v22, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v42
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v20, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v41
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v18, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v37, 16, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v39, 16, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 16, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 16, v38
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 16, v48
|
|
; SI-NEXT: v_lshlrev_b32_e32 v53, 16, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v50, 16, v50
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v52
|
|
; SI-NEXT: v_lshlrev_b32_e32 v40, 16, v15
|
|
; SI-NEXT: .LBB100_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v16
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v17
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v18
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v20
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v22
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v24
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v26
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v33
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v28
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v35
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v30
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v32
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v34
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v36
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v51
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v38
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v53
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v48
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v50
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v40
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v52
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v32bf16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB100_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v17, 0x200
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v15
|
|
; VI-NEXT: v_add_f16_sdwa v15, v15, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v15, v19, v15
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v14
|
|
; VI-NEXT: v_add_f16_sdwa v14, v14, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v14, v19, v14
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v13
|
|
; VI-NEXT: v_add_f16_sdwa v13, v13, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v13, v19, v13
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v12
|
|
; VI-NEXT: v_add_f16_sdwa v12, v12, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v12, v19, v12
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v11
|
|
; VI-NEXT: v_add_f16_sdwa v11, v11, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v11, v19, v11
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v10
|
|
; VI-NEXT: v_add_f16_sdwa v10, v10, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v10, v19, v10
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v9
|
|
; VI-NEXT: v_add_f16_sdwa v9, v9, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v9, v19, v9
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v8
|
|
; VI-NEXT: v_add_f16_sdwa v8, v8, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v8, v19, v8
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v7
|
|
; VI-NEXT: v_add_f16_sdwa v7, v7, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v7, v19, v7
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v6
|
|
; VI-NEXT: v_add_f16_sdwa v6, v6, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v6, v19, v6
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v5
|
|
; VI-NEXT: v_add_f16_sdwa v5, v5, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v5, v19, v5
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v4
|
|
; VI-NEXT: v_add_f16_sdwa v4, v4, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v16, 0x200, v0
|
|
; VI-NEXT: v_add_f16_sdwa v0, v0, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v18, 0x200, v1
|
|
; VI-NEXT: v_add_f16_sdwa v1, v1, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v4, v19, v4
|
|
; VI-NEXT: v_add_f16_e32 v19, 0x200, v2
|
|
; VI-NEXT: v_add_f16_sdwa v2, v2, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_sdwa v17, v3, v17 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: v_or_b32_e32 v2, v19, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v18, v1
|
|
; VI-NEXT: v_or_b32_e32 v0, v16, v0
|
|
; VI-NEXT: .LBB100_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v32bf16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB100_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: .LBB100_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v32bf16:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-NEXT: s_cbranch_execz .LBB100_2
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: .LBB100_2: ; %end
|
|
; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define inreg <32 x bfloat> @bitcast_v32f16_to_v32bf16_scalar(<32 x half> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v32bf16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v40, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v40, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v40, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v40, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v40, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v40, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v40, s30, 6
|
|
; SI-NEXT: v_writelane_b32 v40, s31, 7
|
|
; SI-NEXT: v_readfirstlane_b32 s60, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s56, v0
|
|
; SI-NEXT: s_lshr_b32 s43, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s42, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s41, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s40, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s15, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s14, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s13, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s12, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s11, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s10, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s9, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s8, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s7, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s6, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s60, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s56, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: s_cbranch_scc0 .LBB101_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_lshl_b32 s44, s16, 16
|
|
; SI-NEXT: s_lshl_b32 s45, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s17, 16
|
|
; SI-NEXT: s_lshl_b32 s47, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s57, s18, 16
|
|
; SI-NEXT: s_lshl_b32 s58, s8, 16
|
|
; SI-NEXT: s_lshl_b32 s61, s19, 16
|
|
; SI-NEXT: s_lshl_b32 s62, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s72, s20, 16
|
|
; SI-NEXT: s_lshl_b32 s73, s10, 16
|
|
; SI-NEXT: s_lshl_b32 s74, s21, 16
|
|
; SI-NEXT: s_lshl_b32 s75, s11, 16
|
|
; SI-NEXT: s_lshl_b32 s76, s22, 16
|
|
; SI-NEXT: s_lshl_b32 s77, s12, 16
|
|
; SI-NEXT: s_lshl_b32 s78, s23, 16
|
|
; SI-NEXT: s_lshl_b32 s79, s13, 16
|
|
; SI-NEXT: s_lshl_b32 s88, s24, 16
|
|
; SI-NEXT: s_lshl_b32 s89, s14, 16
|
|
; SI-NEXT: s_lshl_b32 s90, s25, 16
|
|
; SI-NEXT: s_lshl_b32 s91, s15, 16
|
|
; SI-NEXT: s_lshl_b32 s92, s26, 16
|
|
; SI-NEXT: s_lshl_b32 s93, s40, 16
|
|
; SI-NEXT: s_lshl_b32 s94, s27, 16
|
|
; SI-NEXT: s_lshl_b32 s95, s41, 16
|
|
; SI-NEXT: s_lshl_b32 s30, s28, 16
|
|
; SI-NEXT: s_lshl_b32 s31, s42, 16
|
|
; SI-NEXT: s_lshl_b32 s34, s29, 16
|
|
; SI-NEXT: s_lshl_b32 s35, s43, 16
|
|
; SI-NEXT: s_lshl_b32 s36, s56, 16
|
|
; SI-NEXT: s_lshl_b32 s37, s59, 16
|
|
; SI-NEXT: s_lshl_b32 s38, s60, 16
|
|
; SI-NEXT: s_lshl_b32 s39, s63, 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB101_4
|
|
; SI-NEXT: .LBB101_2: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v0, s63
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s60
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s59
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s42
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s40
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s56
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s28
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v0
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v0, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s43
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s29
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, s41
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s27
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, s26
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v32, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s15
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, s25
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, s14
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, s24
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, s13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, s23
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, s12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v18, s22
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v19, s11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v20, s21
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v21, s10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v22, s20
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v23, s9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v24, s19
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v25, s8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v26, s18
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v27, s7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v28, s17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v29, s6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v30, s16
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
|
|
; SI-NEXT: v_add_f32_e32 v19, 0x38000000, v19
|
|
; SI-NEXT: v_add_f32_e32 v20, 0x38000000, v20
|
|
; SI-NEXT: v_add_f32_e32 v21, 0x38000000, v21
|
|
; SI-NEXT: v_add_f32_e32 v22, 0x38000000, v22
|
|
; SI-NEXT: v_add_f32_e32 v23, 0x38000000, v23
|
|
; SI-NEXT: v_add_f32_e32 v24, 0x38000000, v24
|
|
; SI-NEXT: v_add_f32_e32 v25, 0x38000000, v25
|
|
; SI-NEXT: v_add_f32_e32 v26, 0x38000000, v26
|
|
; SI-NEXT: v_add_f32_e32 v27, 0x38000000, v27
|
|
; SI-NEXT: v_add_f32_e32 v28, 0x38000000, v28
|
|
; SI-NEXT: v_add_f32_e32 v29, 0x38000000, v29
|
|
; SI-NEXT: v_add_f32_e32 v30, 0x38000000, v30
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v19, v19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v20, v20
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v21, v21
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v22, v22
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v23, v23
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v24, v24
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v25, v25
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v26, v26
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v30, v30
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v29, v29
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v28, v28
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v27, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 16, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: s_branch .LBB101_5
|
|
; SI-NEXT: .LBB101_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr44
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr79
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: ; implicit-def: $sgpr89
|
|
; SI-NEXT: ; implicit-def: $sgpr90
|
|
; SI-NEXT: ; implicit-def: $sgpr91
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr93
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr95
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: ; implicit-def: $sgpr31
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr35
|
|
; SI-NEXT: ; implicit-def: $sgpr36
|
|
; SI-NEXT: ; implicit-def: $sgpr37
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr39
|
|
; SI-NEXT: s_branch .LBB101_2
|
|
; SI-NEXT: .LBB101_4:
|
|
; SI-NEXT: v_mov_b32_e32 v1, s39
|
|
; SI-NEXT: v_mov_b32_e32 v0, s38
|
|
; SI-NEXT: v_mov_b32_e32 v3, s37
|
|
; SI-NEXT: v_mov_b32_e32 v2, s36
|
|
; SI-NEXT: v_mov_b32_e32 v5, s35
|
|
; SI-NEXT: v_mov_b32_e32 v4, s34
|
|
; SI-NEXT: v_mov_b32_e32 v7, s31
|
|
; SI-NEXT: v_mov_b32_e32 v6, s30
|
|
; SI-NEXT: v_mov_b32_e32 v9, s95
|
|
; SI-NEXT: v_mov_b32_e32 v8, s94
|
|
; SI-NEXT: v_mov_b32_e32 v11, s93
|
|
; SI-NEXT: v_mov_b32_e32 v10, s92
|
|
; SI-NEXT: v_mov_b32_e32 v13, s91
|
|
; SI-NEXT: v_mov_b32_e32 v12, s90
|
|
; SI-NEXT: v_mov_b32_e32 v15, s89
|
|
; SI-NEXT: v_mov_b32_e32 v14, s88
|
|
; SI-NEXT: v_mov_b32_e32 v17, s79
|
|
; SI-NEXT: v_mov_b32_e32 v16, s78
|
|
; SI-NEXT: v_mov_b32_e32 v19, s77
|
|
; SI-NEXT: v_mov_b32_e32 v18, s76
|
|
; SI-NEXT: v_mov_b32_e32 v21, s75
|
|
; SI-NEXT: v_mov_b32_e32 v20, s74
|
|
; SI-NEXT: v_mov_b32_e32 v23, s73
|
|
; SI-NEXT: v_mov_b32_e32 v22, s72
|
|
; SI-NEXT: v_mov_b32_e32 v25, s62
|
|
; SI-NEXT: v_mov_b32_e32 v24, s61
|
|
; SI-NEXT: v_mov_b32_e32 v27, s58
|
|
; SI-NEXT: v_mov_b32_e32 v26, s57
|
|
; SI-NEXT: v_mov_b32_e32 v29, s47
|
|
; SI-NEXT: v_mov_b32_e32 v28, s46
|
|
; SI-NEXT: v_mov_b32_e32 v31, s45
|
|
; SI-NEXT: v_mov_b32_e32 v30, s44
|
|
; SI-NEXT: .LBB101_5: ; %end
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v31, 16, v31
|
|
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v29
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v0
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[30:31], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v27, 16, v27
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v2
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[28:29], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 16, v25
|
|
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v23, 1.0, v23
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[26:27], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v21, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v4
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[24:25], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
|
|
; SI-NEXT: v_mul_f32_e32 v20, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v19, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v5
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[22:23], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_mul_f32_e32 v18, 1.0, v18
|
|
; SI-NEXT: v_mul_f32_e32 v17, 1.0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v6
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[20:21], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v7
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[18:19], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v8
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[16:17], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v9
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[14:15], 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v11
|
|
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v10
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[12:13], 16
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[32:33], 16
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[34:35], 16
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[36:37], 16
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[38:39], 16
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[48:49], 16
|
|
; SI-NEXT: v_readlane_b32 s30, v40, 6
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[50:51], 16
|
|
; SI-NEXT: v_readlane_b32 s31, v40, 7
|
|
; SI-NEXT: v_readlane_b32 s39, v40, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v40, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v40, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v40, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v40, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v40, 0
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v32bf16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v18, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v18, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB101_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB101_4
|
|
; VI-NEXT: .LBB101_2: ; %cmp.true
|
|
; VI-NEXT: s_lshr_b32 s5, s30, 16
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0x200
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: s_lshr_b32 s5, s31, 16
|
|
; VI-NEXT: v_add_f16_e32 v2, s30, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_mov_b32_e32 v5, s5
|
|
; VI-NEXT: s_lshr_b32 s5, s29, 16
|
|
; VI-NEXT: v_or_b32_e32 v14, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s29, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s28, 16
|
|
; VI-NEXT: v_or_b32_e32 v13, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s28, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s27, 16
|
|
; VI-NEXT: v_or_b32_e32 v12, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s27, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s26, 16
|
|
; VI-NEXT: v_or_b32_e32 v11, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s26, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s25, 16
|
|
; VI-NEXT: v_or_b32_e32 v10, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s25, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s24, 16
|
|
; VI-NEXT: v_or_b32_e32 v9, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s24, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s23, 16
|
|
; VI-NEXT: v_or_b32_e32 v8, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s23, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s22, 16
|
|
; VI-NEXT: v_or_b32_e32 v7, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s22, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s21, 16
|
|
; VI-NEXT: v_or_b32_e32 v6, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v4, s31, v1
|
|
; VI-NEXT: v_add_f16_sdwa v5, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v2, s21, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s20, 16
|
|
; VI-NEXT: v_or_b32_e32 v15, v4, v5
|
|
; VI-NEXT: v_or_b32_e32 v5, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: v_add_f16_e32 v2, s20, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_lshr_b32 s5, s19, 16
|
|
; VI-NEXT: v_or_b32_e32 v4, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s5
|
|
; VI-NEXT: s_lshr_b32 s5, s18, 16
|
|
; VI-NEXT: v_add_f16_e32 v2, s19, v1
|
|
; VI-NEXT: v_add_f16_sdwa v3, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_mov_b32_e32 v16, s5
|
|
; VI-NEXT: s_lshr_b32 s4, s16, 16
|
|
; VI-NEXT: v_or_b32_e32 v3, v2, v3
|
|
; VI-NEXT: v_add_f16_e32 v2, s18, v1
|
|
; VI-NEXT: v_add_f16_sdwa v16, v16, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v16
|
|
; VI-NEXT: v_mov_b32_e32 v16, s4
|
|
; VI-NEXT: s_lshr_b32 s4, s17, 16
|
|
; VI-NEXT: v_mov_b32_e32 v17, s4
|
|
; VI-NEXT: v_add_f16_e32 v0, s16, v1
|
|
; VI-NEXT: v_add_f16_sdwa v16, v16, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_sdwa v17, v17, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_e32 v1, s17, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v17
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v16
|
|
; VI-NEXT: s_branch .LBB101_5
|
|
; VI-NEXT: .LBB101_3:
|
|
; VI-NEXT: s_branch .LBB101_2
|
|
; VI-NEXT: .LBB101_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB101_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v18, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v18, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v32bf16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v16, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v16, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB101_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB101_4
|
|
; GFX9-NEXT: .LBB101_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v15, s31, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, s30, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, s29, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, s28, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, s27, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, s26, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, s25, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: s_branch .LBB101_5
|
|
; GFX9-NEXT: .LBB101_3:
|
|
; GFX9-NEXT: s_branch .LBB101_2
|
|
; GFX9-NEXT: .LBB101_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB101_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v16, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v16, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v32bf16_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB101_3
|
|
; GFX11-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB101_4
|
|
; GFX11-NEXT: .LBB101_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s27 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s26 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s25 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s24 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s23 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s22 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s21 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-NEXT: .LBB101_3:
|
|
; GFX11-NEXT: s_branch .LBB101_2
|
|
; GFX11-NEXT: .LBB101_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define <32 x half> @bitcast_v32bf16_to_v32f16(<32 x bfloat> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v32f16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v31
|
|
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v1
|
|
; SI-NEXT: v_mul_f32_e32 v47, 1.0, v32
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v35, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v46, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v27
|
|
; SI-NEXT: v_mul_f32_e32 v37, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v44, 1.0, v28
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v39, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v42, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v48, 1.0, v23
|
|
; SI-NEXT: v_mul_f32_e32 v49, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v41, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v50, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v51, 1.0, v11
|
|
; SI-NEXT: v_mul_f32_e32 v40, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v52, 1.0, v19
|
|
; SI-NEXT: v_mul_f32_e32 v54, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v55, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v43, 1.0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v45, 1.0, v15
|
|
; SI-NEXT: v_mul_f32_e32 v53, 1.0, v18
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e32 v63, 1.0, v0
|
|
; SI-NEXT: v_mul_f32_e32 v62, 1.0, v2
|
|
; SI-NEXT: v_mul_f32_e32 v61, 1.0, v4
|
|
; SI-NEXT: v_mul_f32_e32 v60, 1.0, v6
|
|
; SI-NEXT: v_mul_f32_e32 v59, 1.0, v8
|
|
; SI-NEXT: v_mul_f32_e32 v58, 1.0, v10
|
|
; SI-NEXT: v_mul_f32_e32 v57, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v56, 1.0, v14
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB102_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v31
|
|
; SI-NEXT: v_alignbit_b32 v23, v1, v33, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v47
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v34
|
|
; SI-NEXT: v_alignbit_b32 v24, v23, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v3, v35, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v46
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v36
|
|
; SI-NEXT: v_alignbit_b32 v25, v22, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v21, v5, v37, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v44
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v38
|
|
; SI-NEXT: v_alignbit_b32 v26, v21, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v39, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v42
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v48
|
|
; SI-NEXT: v_alignbit_b32 v27, v20, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v49, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v50
|
|
; SI-NEXT: v_alignbit_b32 v28, v19, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v17, v11, v51, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v40
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v52
|
|
; SI-NEXT: v_alignbit_b32 v29, v17, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v14, v13, v54, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v43
|
|
; SI-NEXT: v_alignbit_b32 v30, v14, v0, 16
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v45, 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v53
|
|
; SI-NEXT: v_alignbit_b32 v32, v16, v0, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v47
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v46
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v44
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v42
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v40
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v53
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v63, 16
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v62, 16
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v61, 16
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v60, 16
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v59, 16
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v58, 16
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v57, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v18, v56, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: .LBB102_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB102_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v47
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v63
|
|
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v1
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v46
|
|
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v62
|
|
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v23
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v44
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v61
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v42
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v60
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v41
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v59
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v40
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v58
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v55
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v53
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v56
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
|
|
; SI-NEXT: v_alignbit_b32 v18, v14, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v43
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v45
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v32, 0xffff0000, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v52
|
|
; SI-NEXT: v_alignbit_b32 v16, v15, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v54
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v50
|
|
; SI-NEXT: v_alignbit_b32 v14, v13, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v51
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v48
|
|
; SI-NEXT: v_alignbit_b32 v17, v11, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v49
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v38
|
|
; SI-NEXT: v_alignbit_b32 v19, v9, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v39
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v36
|
|
; SI-NEXT: v_alignbit_b32 v20, v7, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v3
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v34
|
|
; SI-NEXT: v_alignbit_b32 v21, v5, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v35
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_alignbit_b32 v22, v3, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v33
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v23
|
|
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_alignbit_b32 v23, v1, v23, 16
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
|
|
; SI-NEXT: v_alignbit_b32 v24, v23, v24, 16
|
|
; SI-NEXT: v_alignbit_b32 v25, v22, v25, 16
|
|
; SI-NEXT: v_alignbit_b32 v26, v21, v26, 16
|
|
; SI-NEXT: v_alignbit_b32 v27, v20, v27, 16
|
|
; SI-NEXT: v_alignbit_b32 v28, v19, v28, 16
|
|
; SI-NEXT: v_alignbit_b32 v29, v17, v29, 16
|
|
; SI-NEXT: v_alignbit_b32 v30, v14, v30, 16
|
|
; SI-NEXT: v_alignbit_b32 v32, v16, v32, 16
|
|
; SI-NEXT: .LBB102_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v11, v17, v11
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v30
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_or_b32_e32 v1, v23, v1
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v25
|
|
; SI-NEXT: v_or_b32_e32 v3, v22, v3
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v5, v21, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v27
|
|
; SI-NEXT: v_or_b32_e32 v7, v20, v7
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v28
|
|
; SI-NEXT: v_or_b32_e32 v9, v19, v9
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v17
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v32
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v24
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v23
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v22
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v21
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v20
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v19
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v32f16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB102_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.true
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; VI-NEXT: s_movk_i32 s6, 0x7fff
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v0
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, s6, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; VI-NEXT: v_bfe_u32 v19, v18, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, s6, v19
|
|
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
|
|
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
|
|
; VI-NEXT: v_bfe_u32 v19, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v2
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, s6, v19
|
|
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
|
|
; VI-NEXT: v_bfe_u32 v20, v19, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, s6, v20
|
|
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
|
|
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
|
|
; VI-NEXT: v_bfe_u32 v20, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v3
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, s6, v20
|
|
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v4
|
|
; VI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, s6, v21
|
|
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v20
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
|
|
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
|
|
; VI-NEXT: v_bfe_u32 v21, v4, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v4
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, s6, v21
|
|
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
|
|
; VI-NEXT: v_bfe_u32 v22, v21, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, s6, v22
|
|
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
|
|
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
|
|
; VI-NEXT: v_bfe_u32 v22, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v5
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, s6, v22
|
|
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v22, v23, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v6
|
|
; VI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; VI-NEXT: v_bfe_u32 v23, v22, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, s6, v23
|
|
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
|
|
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc
|
|
; VI-NEXT: v_bfe_u32 v23, v6, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v6
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, s6, v23
|
|
; VI-NEXT: v_or_b32_e32 v24, 0x400000, v6
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v23, v24, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; VI-NEXT: v_bfe_u32 v24, v23, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v23
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, s6, v24
|
|
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v23
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
|
|
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
|
|
; VI-NEXT: v_bfe_u32 v24, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, v24, v7
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, s6, v24
|
|
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v24, v25, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v8
|
|
; VI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
|
|
; VI-NEXT: v_bfe_u32 v25, v24, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, s6, v25
|
|
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v24
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
|
|
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
|
|
; VI-NEXT: v_bfe_u32 v25, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v8
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, s6, v25
|
|
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v25, v26, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
|
|
; VI-NEXT: v_bfe_u32 v26, v25, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v25
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, s6, v26
|
|
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; VI-NEXT: v_or_b32_e32 v27, 0x400000, v25
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
|
|
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
|
|
; VI-NEXT: v_bfe_u32 v26, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, v26, v9
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, s6, v26
|
|
; VI-NEXT: v_or_b32_e32 v27, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v26, v27, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; VI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
|
|
; VI-NEXT: v_bfe_u32 v27, v26, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v26
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, s6, v27
|
|
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; VI-NEXT: v_or_b32_e32 v28, 0x400000, v26
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
|
|
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc
|
|
; VI-NEXT: v_bfe_u32 v27, v10, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, v27, v10
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, s6, v27
|
|
; VI-NEXT: v_or_b32_e32 v28, 0x400000, v10
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v10, v27, v28, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
|
|
; VI-NEXT: v_bfe_u32 v28, v27, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v27
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, s6, v28
|
|
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; VI-NEXT: v_or_b32_e32 v29, 0x400000, v27
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
|
|
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc
|
|
; VI-NEXT: v_bfe_u32 v28, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, v28, v11
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, s6, v28
|
|
; VI-NEXT: v_or_b32_e32 v29, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v12
|
|
; VI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
|
|
; VI-NEXT: v_bfe_u32 v29, v28, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v28
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, s6, v29
|
|
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; VI-NEXT: v_or_b32_e32 v30, 0x400000, v28
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
|
|
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc
|
|
; VI-NEXT: v_bfe_u32 v29, v12, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, v29, v12
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, s6, v29
|
|
; VI-NEXT: v_or_b32_e32 v30, 0x400000, v12
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v12, v29, v30, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
|
|
; VI-NEXT: v_bfe_u32 v30, v29, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v29
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, s6, v30
|
|
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; VI-NEXT: v_or_b32_e32 v31, 0x400000, v29
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
|
|
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc
|
|
; VI-NEXT: v_bfe_u32 v30, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, v30, v13
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, s6, v30
|
|
; VI-NEXT: v_or_b32_e32 v31, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v30, v31, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v14
|
|
; VI-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
|
|
; VI-NEXT: v_bfe_u32 v31, v30, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v30
|
|
; VI-NEXT: v_add_u32_e32 v31, vcc, s6, v31
|
|
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; VI-NEXT: v_or_b32_e32 v32, 0x400000, v30
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
|
|
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v30, v31, v32, vcc
|
|
; VI-NEXT: v_bfe_u32 v31, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v31, vcc, v31, v14
|
|
; VI-NEXT: v_add_u32_e32 v31, vcc, s6, v31
|
|
; VI-NEXT: v_or_b32_e32 v32, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v31, v32, vcc
|
|
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v15
|
|
; VI-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
|
|
; VI-NEXT: v_bfe_u32 v32, v31, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v31
|
|
; VI-NEXT: v_add_u32_e32 v32, vcc, s6, v32
|
|
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; VI-NEXT: v_or_b32_e32 v33, 0x400000, v31
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
|
|
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc
|
|
; VI-NEXT: v_bfe_u32 v32, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v32, vcc, v32, v15
|
|
; VI-NEXT: v_add_u32_e32 v32, vcc, s6, v32
|
|
; VI-NEXT: v_or_b32_e32 v33, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v32, v33, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_alignbit_b32 v15, v15, v31, 16
|
|
; VI-NEXT: v_alignbit_b32 v14, v14, v30, 16
|
|
; VI-NEXT: v_alignbit_b32 v13, v13, v29, 16
|
|
; VI-NEXT: v_alignbit_b32 v12, v12, v28, 16
|
|
; VI-NEXT: v_alignbit_b32 v11, v11, v27, 16
|
|
; VI-NEXT: v_alignbit_b32 v10, v10, v26, 16
|
|
; VI-NEXT: v_alignbit_b32 v9, v9, v25, 16
|
|
; VI-NEXT: v_alignbit_b32 v8, v8, v24, 16
|
|
; VI-NEXT: v_alignbit_b32 v7, v7, v23, 16
|
|
; VI-NEXT: v_alignbit_b32 v6, v6, v22, 16
|
|
; VI-NEXT: v_alignbit_b32 v5, v5, v21, 16
|
|
; VI-NEXT: v_alignbit_b32 v4, v4, v20, 16
|
|
; VI-NEXT: v_alignbit_b32 v3, v3, v19, 16
|
|
; VI-NEXT: v_alignbit_b32 v2, v2, v18, 16
|
|
; VI-NEXT: v_alignbit_b32 v1, v1, v17, 16
|
|
; VI-NEXT: v_alignbit_b32 v0, v0, v16, 16
|
|
; VI-NEXT: .LBB102_2: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v32f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB102_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v17, v0, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v17, v17, v0, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v18, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX9-NEXT: v_add3_u32 v18, v18, v17, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v1, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v18, v18, v1, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; GFX9-NEXT: v_bfe_u32 v19, v18, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX9-NEXT: v_add3_u32 v19, v19, v18, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v19, v2, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v19, v19, v2, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v19, v20, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
|
|
; GFX9-NEXT: v_bfe_u32 v20, v19, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX9-NEXT: v_add3_u32 v20, v20, v19, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v21, 0x400000, v19
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v20, v3, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v20, v20, v3, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v21, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; GFX9-NEXT: v_bfe_u32 v21, v20, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX9-NEXT: v_add3_u32 v21, v21, v20, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v22, 0x400000, v20
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v21, v4, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v21, v21, v4, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v22, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
|
|
; GFX9-NEXT: v_bfe_u32 v22, v21, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX9-NEXT: v_add3_u32 v22, v22, v21, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v23, 0x400000, v21
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v22, v5, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v22, v22, v5, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v23, 0x400000, v5
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v5, v22, v23, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; GFX9-NEXT: v_bfe_u32 v23, v22, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX9-NEXT: v_add3_u32 v23, v23, v22, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v23, v6, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v23, v23, v6, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v24, 0x400000, v6
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v6, v23, v24, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; GFX9-NEXT: v_bfe_u32 v24, v23, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX9-NEXT: v_add3_u32 v24, v24, v23, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v25, 0x400000, v23
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v24, v7, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v24, v24, v7, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v25, 0x400000, v7
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v7, v24, v25, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
|
|
; GFX9-NEXT: v_bfe_u32 v25, v24, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX9-NEXT: v_add3_u32 v25, v25, v24, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v26, 0x400000, v24
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v25, v8, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v25, v25, v8, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v26, 0x400000, v8
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v8, v25, v26, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
|
|
; GFX9-NEXT: v_bfe_u32 v26, v25, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX9-NEXT: v_add3_u32 v26, v26, v25, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v27, 0x400000, v25
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v26, v9, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v26, v26, v9, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v27, 0x400000, v9
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v9, v26, v27, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
|
|
; GFX9-NEXT: v_bfe_u32 v27, v26, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX9-NEXT: v_add3_u32 v27, v27, v26, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v28, 0x400000, v26
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v26, v27, v28, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v27, v10, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v27, v27, v10, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v28, 0x400000, v10
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v10, v27, v28, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
|
|
; GFX9-NEXT: v_bfe_u32 v28, v27, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX9-NEXT: v_add3_u32 v28, v28, v27, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v29, 0x400000, v27
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v27, v28, v29, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v28, v11, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v28, v28, v11, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v29, 0x400000, v11
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v11, v28, v29, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
|
|
; GFX9-NEXT: v_bfe_u32 v29, v28, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX9-NEXT: v_add3_u32 v29, v29, v28, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v30, 0x400000, v28
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v28, v28
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v28, v29, v30, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v29, v12, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v29, v29, v12, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v30, 0x400000, v12
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v12, v29, v30, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
|
|
; GFX9-NEXT: v_bfe_u32 v30, v29, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX9-NEXT: v_add3_u32 v30, v30, v29, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v31, 0x400000, v29
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v29, v29
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v29, v30, v31, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v30, v13, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v30, v30, v13, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v31, 0x400000, v13
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v13, v30, v31, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
|
|
; GFX9-NEXT: v_bfe_u32 v31, v30, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX9-NEXT: v_add3_u32 v31, v31, v30, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v32, 0x400000, v30
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v30, v30
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v30, v31, v32, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v31, v14, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v31, v31, v14, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v32, 0x400000, v14
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v14, v31, v32, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
|
|
; GFX9-NEXT: v_bfe_u32 v32, v31, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX9-NEXT: v_add3_u32 v32, v32, v31, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v33, 0x400000, v31
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v31, v31
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v32, v15, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v32, v32, v15, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v33, 0x400000, v15
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v15, v32, v33, vcc
|
|
; GFX9-NEXT: s_mov_b32 s6, 0x7060302
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v31, s6
|
|
; GFX9-NEXT: v_perm_b32 v14, v14, v30, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v29, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v12, v28, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v27, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v10, v26, s6
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v25, s6
|
|
; GFX9-NEXT: v_perm_b32 v8, v8, v24, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v23, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v6, v22, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v4, v20, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v19, s6
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v18, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v0, v0, v16, s6
|
|
; GFX9-NEXT: .LBB102_2: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v32f16:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, v15 :: v_dual_mov_b32 v31, v14
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, v13 :: v_dual_mov_b32 v29, v12
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, v11 :: v_dual_mov_b32 v27, v10
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, v9 :: v_dual_mov_b32 v25, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, v7 :: v_dual_mov_b32 v23, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, v5 :: v_dual_mov_b32 v21, v4
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, v3 :: v_dual_mov_b32 v19, v2
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v17, v0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB102_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB102_4
|
|
; GFX11-TRUE16-NEXT: .LBB102_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB102_3: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v17 :: v_dual_mov_b32 v1, v18
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v19 :: v_dual_mov_b32 v3, v20
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v21 :: v_dual_mov_b32 v5, v22
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v23 :: v_dual_mov_b32 v7, v24
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v25 :: v_dual_mov_b32 v9, v26
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, v27 :: v_dual_mov_b32 v11, v28
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, v29 :: v_dual_mov_b32 v13, v30
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, v31 :: v_dual_mov_b32 v15, v32
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB102_2
|
|
; GFX11-TRUE16-NEXT: .LBB102_4: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v18
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v19
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v23
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v25
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v31
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v22
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v24
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v26
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v17
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v0, 0x40c00000, v0 :: v_dual_lshlrev_b32 v1, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_cndmask_b32 v0, v5, v6
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v20
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v18
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v7, v9 :: v_dual_add_f32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v20
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v8, v10 :: v_dual_and_b32 v10, 0xffff0000, v21
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v19
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_cndmask_b32 v17, v5, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v17.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v8, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v3, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v10 :: v_dual_lshlrev_b32 v6, 16, v21
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v7, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v22
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_add_f32 v7, 0x40c00000, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v10, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v19.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v5, v9, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v10, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v5, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v12 :: v_dual_lshlrev_b32 v8, 16, v23
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v6, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v9, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v24
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v27
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v18.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v6, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v12, v7, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v21.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v11, v8, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v12, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v7, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v9, 0x40c00000, v14 :: v_dual_lshlrev_b32 v10, 16, v25
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v26
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v8, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_add_f32 v11, 0x40c00000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v8, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v8, v14, v9, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v23.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v9, v13, v10, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v14, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v15
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v9, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v27
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v24
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v13, v15, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v10, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v28
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v26, v10, v15 :: v_dual_add_f32 v13, 0x40c00000, v13
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v10, v24, v11, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xffff0000, v29
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v26.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v11, v15, v12, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v15, v24, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v27
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v25.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v22.h
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v24, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v11, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v13, 0x40c00000, v28 :: v_dual_lshlrev_b32 v14, 16, v29
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v12, v24, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v33.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v15, v27, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v24
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v30
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v30
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v12, v27, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v12, v28, v13, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v28, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v29, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v24.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v13, v28, v14, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v12, v27, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v28, v29, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v30
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v27, v13, v27, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v29, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v34
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v27.h
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v28, v30 :: v_dual_lshlrev_b32 v28, 16, v31
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v29, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v32
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v29
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v30
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v29, v14, v31 :: v_dual_and_b32 v32, 0xffff0000, v32
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v28, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v31, v34, v15, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v30, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v28
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v14, v14, v28, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v32, 0x40c00000, v32
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v34, v34, v30, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v38, 0x400000, v30
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v14, v36, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v37, v32, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v29.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v30, v34, v38, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v36, v37, v32, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v32
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v31, v35, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v32, v32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v28.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v36, v37, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v30.h
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v32f16:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v16
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB102_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v16, 0x40c00000, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v24 :: v_dual_lshlrev_b32 v25, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v16, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v25, 0x40c00000, v25 :: v_dual_add_f32 v6, 0x40c00000, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v19, v22 :: v_dual_lshlrev_b32 v27, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v22, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v26, 0x40c00000, v26 :: v_dual_add_f32 v27, 0x40c00000, v27
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v28, 0x40c00000, v28 :: v_dual_lshlrev_b32 v29, 16, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v20, v0, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_lshlrev_b32 v31, 16, v12
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v0, v20, v23 :: v_dual_lshlrev_b32 v23, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v21, v19, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v20, v1, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v31, 0x40c00000, v31
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v19, v20 :: v_dual_add_f32 v18, 0x40c00000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v2, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v19, v20 :: v_dual_and_b32 v7, 0xffff0000, v7
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v2, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v19, v20 :: v_dual_and_b32 v11, 0xffff0000, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v21, v22, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v22
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v3, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v23, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v21, v3, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v3
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v20, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v22, v23, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v23
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v19, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v21, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v22, v4, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v21, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v23, v24, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v25, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v20, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v21, v22, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v23, v5, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v22, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v24, v25, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v25
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v26, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v21, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v23, v24, v6, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v23, v24, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v23, v25, v26, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v26
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v27, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v22, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v23, v24, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v25, v7, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v26, v27, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v27
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v28, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v23, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v25, v26, v8, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v25, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v25, v27, v28, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v28
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v29, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v24, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v25, v26, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v26, v27, v9, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v26, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v26, v28, v29, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v29
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v30, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v25, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v27, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v27, v28, v10, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v27, v28, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v27, v29, v30, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v30
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v28 :: v_dual_lshlrev_b32 v28, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v31, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v34, v12, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v29, v29, v11, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v30, v30, v33, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v28, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v28
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v31, v33, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v35, v28, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v37, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v26, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v35 :: v_dual_cndmask_b32 v28, v34, v36
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v37, v13, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v34, 0x40c00000, v34
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v38, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v31, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v34, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v48, 0x400000, v34
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v31, v35, v37, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v37, v38, v14, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v39, v39, v34, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v37, v38, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v35, v15, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v31, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v34, v39, v48, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v35, v49, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v34, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v33, v36, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v30, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v28, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v29, v32, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v27, 0x7060302
|
|
; GFX11-FAKE16-NEXT: .LBB102_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define inreg <32 x half> @bitcast_v32bf16_to_v32f16_scalar(<32 x bfloat> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v32f16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_and_b32 s40, s17, 0xffff0000
|
|
; SI-NEXT: s_and_b32 s10, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s26, 16
|
|
; SI-NEXT: s_and_b32 s26, s21, 0xffff0000
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v0
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s40
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff0000
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s26
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v1
|
|
; SI-NEXT: s_and_b32 s45, s44, 0xffff0000
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s8
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s5, s29, 16
|
|
; SI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s28, 16
|
|
; SI-NEXT: s_lshl_b32 s9, s27, 16
|
|
; SI-NEXT: s_and_b32 s12, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s25, 16
|
|
; SI-NEXT: s_and_b32 s14, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s24, 16
|
|
; SI-NEXT: s_and_b32 s24, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_and_b32 s25, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s27, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s28, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: s_and_b32 s29, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s41, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s43, s42, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s42, 16
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v2
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s45
|
|
; SI-NEXT: s_cmp_lg_u32 s46, 0
|
|
; SI-NEXT: v_mul_f32_e64 v43, 1.0, s41
|
|
; SI-NEXT: v_mul_f32_e64 v34, 1.0, s17
|
|
; SI-NEXT: v_mul_f32_e64 v40, 1.0, s29
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s28
|
|
; SI-NEXT: v_mul_f32_e64 v60, 1.0, s19
|
|
; SI-NEXT: v_mul_f32_e64 v47, 1.0, s27
|
|
; SI-NEXT: v_mul_f32_e64 v17, 1.0, s25
|
|
; SI-NEXT: v_mul_f32_e64 v44, 1.0, s24
|
|
; SI-NEXT: v_mul_f32_e64 v28, 1.0, s14
|
|
; SI-NEXT: v_mul_f32_e64 v20, 1.0, s12
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s10
|
|
; SI-NEXT: v_mul_f32_e64 v41, 1.0, s6
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s4
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s43
|
|
; SI-NEXT: v_mul_f32_e64 v48, 1.0, s21
|
|
; SI-NEXT: v_mul_f32_e64 v38, 1.0, s23
|
|
; SI-NEXT: v_mul_f32_e64 v36, 1.0, s13
|
|
; SI-NEXT: v_mul_f32_e64 v62, 1.0, s9
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s5
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s42
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s16
|
|
; SI-NEXT: v_mul_f32_e64 v32, 1.0, s18
|
|
; SI-NEXT: v_mul_f32_e64 v21, 1.0, s20
|
|
; SI-NEXT: v_mul_f32_e64 v45, 1.0, s22
|
|
; SI-NEXT: v_mul_f32_e64 v42, 1.0, s15
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s11
|
|
; SI-NEXT: v_mul_f32_e64 v18, 1.0, s7
|
|
; SI-NEXT: v_mul_f32_e64 v53, 1.0, s44
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_cbranch_scc0 .LBB103_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_mov_b32_e32 v8, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v8
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_mov_b32_e32 v62, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v43
|
|
; SI-NEXT: v_mov_b32_e32 v13, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
|
|
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v44
|
|
; SI-NEXT: v_lshr_b64 v[24:25], v[38:39], 16
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v14
|
|
; SI-NEXT: v_mov_b32_e32 v55, v14
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v20
|
|
; SI-NEXT: v_lshr_b64 v[51:52], v[36:37], 16
|
|
; SI-NEXT: s_waitcnt expcnt(2)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v43
|
|
; SI-NEXT: v_mov_b32_e32 v25, v8
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v41
|
|
; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v47
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v41
|
|
; SI-NEXT: v_mov_b32_e32 v29, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v33, 16, v40
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v47
|
|
; SI-NEXT: v_lshrrev_b32_e32 v46, 16, v17
|
|
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v0
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[34:35], 16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v40
|
|
; SI-NEXT: v_mov_b32_e32 v31, v2
|
|
; SI-NEXT: v_mov_b32_e32 v30, v1
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[60:61], 16
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[0:1], 16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshr_b64 v[57:58], v[48:49], 16
|
|
; SI-NEXT: v_and_b32_e32 v58, 0xffff0000, v12
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshr_b64 v[59:60], v[2:3], 16
|
|
; SI-NEXT: v_mov_b32_e32 v2, v28
|
|
; SI-NEXT: v_lshr_b64 v[27:28], v[15:16], 16
|
|
; SI-NEXT: v_mov_b32_e32 v28, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_mov_b32_e32 v3, v13
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[5:6], 16
|
|
; SI-NEXT: v_mov_b32_e32 v6, v43
|
|
; SI-NEXT: v_lshrrev_b32_e32 v43, 16, v28
|
|
; SI-NEXT: v_mov_b32_e32 v16, v12
|
|
; SI-NEXT: v_mov_b32_e32 v61, v49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v16
|
|
; SI-NEXT: v_mov_b32_e32 v60, v48
|
|
; SI-NEXT: v_mov_b32_e32 v49, v39
|
|
; SI-NEXT: v_mov_b32_e32 v48, v38
|
|
; SI-NEXT: v_mov_b32_e32 v39, v37
|
|
; SI-NEXT: v_mov_b32_e32 v38, v36
|
|
; SI-NEXT: v_lshr_b64 v[36:37], v[30:31], 16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[23:24], 16
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[26:27], 16
|
|
; SI-NEXT: v_mov_b32_e32 v30, v40
|
|
; SI-NEXT: v_mov_b32_e32 v40, v17
|
|
; SI-NEXT: v_mov_b32_e32 v5, v32
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v54, 16, v2
|
|
; SI-NEXT: v_mov_b32_e32 v2, v24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_mov_b32_e32 v2, v51
|
|
; SI-NEXT: v_mov_b32_e32 v24, v19
|
|
; SI-NEXT: v_mov_b32_e32 v23, v18
|
|
; SI-NEXT: v_lshr_b64 v[19:20], v[50:51], 16
|
|
; SI-NEXT: v_lshr_b64 v[50:51], v[58:59], 16
|
|
; SI-NEXT: v_lshr_b64 v[51:52], v[14:15], 16
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[62:63], 16
|
|
; SI-NEXT: v_mov_b32_e32 v17, v53
|
|
; SI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v18, v54
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v14, v55
|
|
; SI-NEXT: v_lshr_b64 v[54:55], v[21:22], 16
|
|
; SI-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_lshr_b64 v[52:53], v[32:33], 16
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshr_b64 v[54:55], v[45:46], 16
|
|
; SI-NEXT: v_mov_b32_e32 v20, v29
|
|
; SI-NEXT: v_mov_b32_e32 v13, v25
|
|
; SI-NEXT: v_mov_b32_e32 v25, v12
|
|
; SI-NEXT: v_mov_b32_e32 v12, v16
|
|
; SI-NEXT: v_mov_b32_e32 v16, v17
|
|
; SI-NEXT: v_lshr_b64 v[55:56], v[17:18], 16
|
|
; SI-NEXT: v_mov_b32_e32 v29, v59
|
|
; SI-NEXT: v_mov_b32_e32 v53, v51
|
|
; SI-NEXT: v_mov_b32_e32 v17, v40
|
|
; SI-NEXT: v_mov_b32_e32 v40, v30
|
|
; SI-NEXT: v_mov_b32_e32 v22, v4
|
|
; SI-NEXT: v_mov_b32_e32 v18, v19
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v10, v3
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[42:43], 16
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[7:8], 16
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[23:24], 16
|
|
; SI-NEXT: v_mov_b32_e32 v24, v36
|
|
; SI-NEXT: v_mov_b32_e32 v36, v38
|
|
; SI-NEXT: v_mov_b32_e32 v37, v39
|
|
; SI-NEXT: v_mov_b32_e32 v38, v48
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v39, v49
|
|
; SI-NEXT: v_mov_b32_e32 v48, v60
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_mov_b32_e32 v2, v62
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_mov_b32_e32 v49, v61
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_mov_b32_e32 v43, v6
|
|
; SI-NEXT: v_mov_b32_e32 v8, v23
|
|
; SI-NEXT: s_cbranch_execnz .LBB103_3
|
|
; SI-NEXT: .LBB103_2: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v43
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v2
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v5
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v40
|
|
; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v0
|
|
; SI-NEXT: v_lshr_b64 v[52:53], v[1:2], 16
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v47
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v21
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v4
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v17
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v45
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v5
|
|
; SI-NEXT: v_lshr_b64 v[17:18], v[1:2], 16
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v28
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v42
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v6
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v12
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v7
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v7
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v41
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v8
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v8
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v16
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v8
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v9
|
|
; SI-NEXT: v_lshr_b64 v[55:56], v[1:2], 16
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v56, 0xffff0000, v4
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v14
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v1
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v9
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[11:12], 16
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v10
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v1
|
|
; SI-NEXT: v_mov_b32_e32 v1, v12
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v62
|
|
; SI-NEXT: v_add_f32_e32 v62, 0x40c00000, v1
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshr_b64 v[27:28], v[11:12], 16
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v7
|
|
; SI-NEXT: v_lshr_b64 v[53:54], v[14:15], 16
|
|
; SI-NEXT: v_mov_b32_e32 v54, v17
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v36
|
|
; SI-NEXT: v_add_f32_e32 v36, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v20
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v38
|
|
; SI-NEXT: v_add_f32_e32 v38, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v44
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v48
|
|
; SI-NEXT: v_add_f32_e32 v48, 0x40c00000, v1
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[38:39], 16
|
|
; SI-NEXT: v_lshr_b64 v[29:30], v[62:63], 16
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v3
|
|
; SI-NEXT: v_lshr_b64 v[19:20], v[36:37], 16
|
|
; SI-NEXT: v_lshr_b64 v[22:23], v[6:7], 16
|
|
; SI-NEXT: v_lshr_b64 v[50:51], v[28:29], 16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v60
|
|
; SI-NEXT: v_add_f32_e32 v60, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v13
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v1
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[60:61], 16
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v34
|
|
; SI-NEXT: v_add_f32_e32 v34, 0x40c00000, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[0:1], 16
|
|
; SI-NEXT: v_lshr_b64 v[57:58], v[48:49], 16
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[56:57], 16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v2
|
|
; SI-NEXT: v_mov_b32_e32 v2, v7
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_lshr_b64 v[31:32], v[34:35], 16
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_mov_b32_e32 v2, v19
|
|
; SI-NEXT: v_lshr_b64 v[24:25], v[30:31], 16
|
|
; SI-NEXT: v_lshr_b64 v[18:19], v[18:19], 16
|
|
; SI-NEXT: v_lshr_b64 v[25:26], v[26:27], 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: .LBB103_3: ; %end
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v1
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v31
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v52
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v49
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v53
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v35
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v61
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v17
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v57
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v54
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v8
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v18
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v29
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v50
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v63
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v25
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v27
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v55
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v17
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB103_4:
|
|
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_mov_b32_e32 v5, v32
|
|
; SI-NEXT: v_mov_b32_e32 v8, v18
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mov_b32_e32 v16, v53
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: s_branch .LBB103_2
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v32f16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: v_writelane_b32 v20, s30, 0
|
|
; VI-NEXT: v_writelane_b32 v20, s31, 1
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s31, v1
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s30, v0
|
|
; VI-NEXT: s_cbranch_scc0 .LBB103_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_cbranch_execnz .LBB103_4
|
|
; VI-NEXT: .LBB103_2: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v16, 0x40c00000
|
|
; VI-NEXT: s_lshl_b32 s4, s26, 16
|
|
; VI-NEXT: v_add_f32_e32 v4, s4, v16
|
|
; VI-NEXT: s_lshl_b32 s4, s28, 16
|
|
; VI-NEXT: v_add_f32_e32 v0, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v1, v0, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; VI-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
|
|
; VI-NEXT: v_add_f32_e32 v1, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: s_lshl_b32 s4, s30, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; VI-NEXT: v_add_f32_e32 v2, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: s_and_b32 s4, s30, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
|
|
; VI-NEXT: v_add_f32_e32 v3, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: s_and_b32 s6, s26, 0xffff0000
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[2:3]
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[12:13], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v4, 16, 1
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v4
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v4, v4
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s24, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s24, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s22, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s22, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s20, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[6:7], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s20, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: s_lshl_b32 s6, s18, 16
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v2, 16, 1
|
|
; VI-NEXT: s_and_b32 s6, s18, 0xffff0000
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e64 s[4:5], v2, v2
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v16
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
|
|
; VI-NEXT: s_and_b32 s7, s16, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e64 v0, v0, v1, s[4:5]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v5, s7, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v0, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v5
|
|
; VI-NEXT: s_lshl_b32 s6, s16, 16
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_or_b32_e32 v1, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc
|
|
; VI-NEXT: v_bfe_u32 v0, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v3
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7fff, v0
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: s_and_b32 s5, s17, 0xffff0000
|
|
; VI-NEXT: v_add_f32_e32 v3, s5, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]
|
|
; VI-NEXT: v_bfe_u32 v1, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v3
|
|
; VI-NEXT: s_lshl_b32 s4, s17, 16
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: s_and_b32 s5, s19, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s5, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v5, v7, vcc
|
|
; VI-NEXT: v_bfe_u32 v5, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v3
|
|
; VI-NEXT: s_lshl_b32 s4, s19, 16
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_add_f32_e32 v3, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
|
|
; VI-NEXT: v_bfe_u32 v7, v3, 16, 1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v3
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: s_and_b32 s5, s21, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v5, s5, v16
|
|
; VI-NEXT: v_mov_b32_e32 v1, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v7, v9, vcc
|
|
; VI-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v5
|
|
; VI-NEXT: s_lshl_b32 s4, s21, 16
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_add_f32_e32 v5, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
|
|
; VI-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v5
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: s_and_b32 s5, s23, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v7, s5, v16
|
|
; VI-NEXT: v_mov_b32_e32 v3, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v9, v11, vcc
|
|
; VI-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v7
|
|
; VI-NEXT: s_lshl_b32 s4, s23, 16
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_add_f32_e32 v7, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
|
|
; VI-NEXT: v_bfe_u32 v11, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v7
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: s_and_b32 s5, s25, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v9, s5, v16
|
|
; VI-NEXT: v_mov_b32_e32 v5, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v11, v13, vcc
|
|
; VI-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v9
|
|
; VI-NEXT: s_lshl_b32 s4, s25, 16
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_add_f32_e32 v9, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc
|
|
; VI-NEXT: v_bfe_u32 v13, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v9
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: s_and_b32 s5, s27, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v11, s5, v16
|
|
; VI-NEXT: v_mov_b32_e32 v7, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v13, v15, vcc
|
|
; VI-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v11
|
|
; VI-NEXT: s_lshl_b32 s4, s27, 16
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_add_f32_e32 v11, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc
|
|
; VI-NEXT: v_bfe_u32 v15, v11, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v11
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: s_and_b32 s5, s29, 0xffff0000
|
|
; VI-NEXT: v_mov_b32_e32 v9, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s5, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v15, v17, vcc
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: s_lshl_b32 s4, s29, 16
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_mov_b32_e32 v11, v17
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc
|
|
; VI-NEXT: v_bfe_u32 v17, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v13
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: s_and_b32 s4, s31, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_add_f32_e32 v13, s4, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v15
|
|
; VI-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v13
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: s_lshl_b32 s4, s31, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v15, v19, vcc
|
|
; VI-NEXT: v_add_f32_e32 v15, s4, v16
|
|
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_lshrrev_b64 v[15:16], 16, v[15:16]
|
|
; VI-NEXT: v_mov_b32_e32 v13, v17
|
|
; VI-NEXT: s_branch .LBB103_5
|
|
; VI-NEXT: .LBB103_3:
|
|
; VI-NEXT: s_branch .LBB103_2
|
|
; VI-NEXT: .LBB103_4:
|
|
; VI-NEXT: v_mov_b32_e32 v0, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v2, s18
|
|
; VI-NEXT: v_mov_b32_e32 v3, s19
|
|
; VI-NEXT: v_mov_b32_e32 v4, s20
|
|
; VI-NEXT: v_mov_b32_e32 v5, s21
|
|
; VI-NEXT: v_mov_b32_e32 v6, s22
|
|
; VI-NEXT: v_mov_b32_e32 v7, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s24
|
|
; VI-NEXT: v_mov_b32_e32 v9, s25
|
|
; VI-NEXT: v_mov_b32_e32 v10, s26
|
|
; VI-NEXT: v_mov_b32_e32 v11, s27
|
|
; VI-NEXT: v_mov_b32_e32 v12, s28
|
|
; VI-NEXT: v_mov_b32_e32 v13, s29
|
|
; VI-NEXT: v_mov_b32_e32 v14, s30
|
|
; VI-NEXT: v_mov_b32_e32 v15, s31
|
|
; VI-NEXT: .LBB103_5: ; %end
|
|
; VI-NEXT: v_readlane_b32 s30, v20, 0
|
|
; VI-NEXT: v_readlane_b32 s31, v20, 1
|
|
; VI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v32f16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: v_writelane_b32 v20, s30, 0
|
|
; GFX9-NEXT: v_writelane_b32 v20, s31, 1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s31, v1
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s30, v0
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB103_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB103_4
|
|
; GFX9-NEXT: .LBB103_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000
|
|
; GFX9-NEXT: s_and_b32 s5, s30, 0xffff0000
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s5, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s5, s30, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s5, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: s_and_b32 s5, s31, 0xffff0000
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v3, s5, v0
|
|
; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: s_lshl_b32 s5, s31, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v4, s5, v0
|
|
; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, 0xffff
|
|
; GFX9-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_and_b32_sdwa v4, v16, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v3, 16, v4
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s29, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s28, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s28, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s27, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s27, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s26, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s26, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s25, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s25, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s24, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s24, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s23, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s23, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s22, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s22, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s21, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s21, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s20, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s20, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s19, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s19, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v17, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s18, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s18, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v17, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v18, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s17, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v2, v16, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v1, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v17, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, v17, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: s_lshl_b32 s4, s17, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v18, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: s_and_b32 s4, s16, 0xffff0000
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_and_b32_sdwa v17, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v17, s4, v0
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v17
|
|
; GFX9-NEXT: s_lshl_b32 s4, s16, 16
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v0, s4, v0
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v0, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v18, v18, v0
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x7fff, v18
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v0
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v17
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_and_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v16
|
|
; GFX9-NEXT: s_branch .LBB103_5
|
|
; GFX9-NEXT: .LBB103_3:
|
|
; GFX9-NEXT: s_branch .LBB103_2
|
|
; GFX9-NEXT: .LBB103_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s31
|
|
; GFX9-NEXT: .LBB103_5: ; %end
|
|
; GFX9-NEXT: v_readlane_b32 s30, v20, 0
|
|
; GFX9-NEXT: v_readlane_b32 s31, v20, 1
|
|
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v32f16_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB103_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB103_4
|
|
; GFX11-TRUE16-NEXT: .LBB103_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s12, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s12, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s13, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s2, s14, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s25, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v0, v2, v6 :: v_dual_add_nc_u32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s27, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v1, v6, v2 :: v_dual_add_nc_u32 v2, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, v4, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s15, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, 0x400000, v29
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s16, 16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v34, v33, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v17.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v2, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, v34, v33
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v18.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v6, v7 :: v_dual_add_nc_u32 v4, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v4, v6 :: v_dual_add_nc_u32 v4, v7, v9
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v10, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v9 :: v_dual_add_nc_u32 v8, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v4, v7
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v8, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v6, v8 :: v_dual_add_nc_u32 v6, v9, v11
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v12, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v11 :: v_dual_add_nc_u32 v10, 0x7fff, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v6, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v7
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v12
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v10, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v22.l
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v8, v10 :: v_dual_add_nc_u32 v8, v11, v13
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v12
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v14, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v13 :: v_dual_add_nc_u32 v12, 0x7fff, v14
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v8, v11
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v9
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v14
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v12, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v15, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v24.l
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v10, v12 :: v_dual_add_nc_u32 v10, v13, v15
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v15
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v14
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v26, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, v26, v12
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v11, v15 :: v_dual_add_nc_u32 v14, 0x7fff, v26
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, v10, v13
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v26
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v14, v15, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v28, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v27.l
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v12, v12, v14 :: v_dual_add_nc_u32 v13, v15, v28
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v26, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v29, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v25.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v28
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v14, v26
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v29
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v26
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v30.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v32, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v14, v14, v28, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s26, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, v32, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v31, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v31, v26, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v28
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v26
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, v31, v26
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v31, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v29.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v31, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v28
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v36, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v31
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v37, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v28, v35, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v35, 0x400000, v33
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, v36, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v36, 0x400000, v31
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v34, v35, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x7fff, v28
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v32.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v23.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v33
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v36, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v21.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v20.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v19.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v28, v37, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v26.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v16.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v28
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v31.l
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB103_3:
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB103_2
|
|
; GFX11-TRUE16-NEXT: .LBB103_4:
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v32f16_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s15, s3
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s14, s2
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s13, s1
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s12, s0
|
|
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s0, 0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB103_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB103_4
|
|
; GFX11-FAKE16-NEXT: .LBB103_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s12, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s12, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v0, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s13, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s13, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x7fff, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s2, s14, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s14, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s27, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v33, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v9, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s15, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_add_nc_u32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s15, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v38, 0x400000, v33
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v2, v3, v4 :: v_dual_add_nc_u32 v3, v6, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v4, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v33, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v4, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v3, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v9, v4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v4, v6, v7 :: v_dual_add_nc_u32 v7, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v9
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v5, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v8 :: v_dual_add_nc_u32 v8, 0x7fff, v10
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v10, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v9, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v8, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v12, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v9, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v13, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v9, v9, v11 :: v_dual_add_nc_u32 v10, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v12, v13
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v9
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v10, v14 :: v_dual_add_nc_u32 v11, 0x7fff, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v11, v14, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v10, v13
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v14, v15
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v11
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, v26, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v13, v15, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v26
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, v27, v12
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v27, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v13, v13, v15 :: v_dual_add_nc_u32 v14, 0x7fff, v26
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v27, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s25, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v27
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v12, v14, v15, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v26, v27
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v13
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v26, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v27, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v29 :: v_dual_add_nc_u32 v15, 0x7fff, v15
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, v30, v26
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v27, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v27
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v15, v29, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v30
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v26
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v30, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v14, v27
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v29, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v29, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s26, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v35, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v29, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v37, 0x400000, v29
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v30, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v32, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v34, v29
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v35, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, v36, v33
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, v26, v30
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x7fff, v27
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, v32, v35
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v34, 0x7fff, v34
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v36, 0x400000, v30
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v27, v27, v37 :: v_dual_add_nc_u32 v26, 0x7fff, v26
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v33, v33
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v29, 0x7fff, v32
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v35
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v27
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v33, v34, v38, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v35, v35
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v34, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v27
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v29, v29, v32, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v33
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v33, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v29
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v26, v26, v36, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v30, 16, v27
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v28, 16, v33
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v29
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v26
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v31, 16, v30
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v10, 16, v34
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v26, 16, v27
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v32, 16, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v5, 16, v28
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v24, 16, v25
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v23, 16, v26
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v22, 16, v27
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v21, 16, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v18, 16, v19
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v17, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v16, 16, v22
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v23
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB103_3:
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB103_2
|
|
; GFX11-FAKE16-NEXT: .LBB103_4:
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s21
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s23
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s25
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s27
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v64i8:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v18, 16, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 16, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v14
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v21, 16, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 16, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 16, v8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 16, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v23, 16, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 16, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v24, 16, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 16, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 16, v2
|
|
; SI-NEXT: v_lshrrev_b32_e32 v58, 16, v1
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; kill: killed $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; kill: killed $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; kill: killed $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB104_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v58
|
|
; SI-NEXT: v_or_b32_e32 v57, v1, v17
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v45, v1, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v59
|
|
; SI-NEXT: v_or_b32_e32 v38, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v24
|
|
; SI-NEXT: v_or_b32_e32 v37, v1, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v37, v38, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v37, v38, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v37, v38, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v60
|
|
; SI-NEXT: v_or_b32_e32 v35, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
|
|
; SI-NEXT: v_or_b32_e32 v36, v1, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v36, v35, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v36, v35, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v36, v35, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v61
|
|
; SI-NEXT: v_or_b32_e32 v33, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
|
|
; SI-NEXT: v_or_b32_e32 v34, v1, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v34, v33, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v34, v33, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v34, v33, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v62
|
|
; SI-NEXT: v_or_b32_e32 v31, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v32, v1, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v32, v31, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v32, v31, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v32, v31, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v29, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
|
|
; SI-NEXT: v_or_b32_e32 v30, v1, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v30, v29, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v30, v29, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v30, v29, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v63
|
|
; SI-NEXT: v_or_b32_e32 v27, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
|
|
; SI-NEXT: v_or_b32_e32 v28, v1, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v27, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v27, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v27, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v48
|
|
; SI-NEXT: v_or_b32_e32 v17, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v18
|
|
; SI-NEXT: v_or_b32_e32 v25, v1, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v17, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v17, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v17, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 8, v45
|
|
; SI-NEXT: v_lshrrev_b32_e32 v43, 8, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 8, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 8, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 8, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 8, v28
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_bfe_u32 v56, v26, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v46, v24, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v44, v23, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v42, v22, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v40, v21, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v54, v20, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v52, v19, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v50, v18, 8, 8
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: .LBB104_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB104_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v17, v48
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v15
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v18, v18
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v17, v17
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_add_f32_e32 v18, 0x38000000, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v18, v18
|
|
; SI-NEXT: v_or_b32_e32 v17, v15, v17
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v63
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v16, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v18
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v13
|
|
; SI-NEXT: v_or_b32_e32 v25, v16, v25
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v16, v19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v13, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v14, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v16
|
|
; SI-NEXT: v_or_b32_e32 v27, v13, v15
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v15, v39
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v19, v16
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v14
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v15, v15
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_or_b32_e32 v28, v14, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v15
|
|
; SI-NEXT: v_or_b32_e32 v29, v11, v14
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v11, v12
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v13, v62
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v20, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v9
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v13
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v11, v11
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v20
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_or_b32_e32 v30, v11, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v12
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v12, v21
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v10
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v12
|
|
; SI-NEXT: v_or_b32_e32 v31, v9, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v61
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v21, v12
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v10, v10
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v21
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_or_b32_e32 v32, v10, v11
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, v22
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v10
|
|
; SI-NEXT: v_or_b32_e32 v33, v7, v9
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v9, v60
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v22, v10
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v22
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v9
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_or_b32_e32 v34, v8, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v35, v5, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, v6
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, v59
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v23, v6
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v23
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
|
|
; SI-NEXT: v_or_b32_e32 v36, v5, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, v24
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v24, v6
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_or_b32_e32 v38, v3, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, v58
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v24
|
|
; SI-NEXT: v_or_b32_e32 v37, v4, v5
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, v26
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v26, v4
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v57, v1, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
|
|
; SI-NEXT: v_or_b32_e32 v45, v2, v1
|
|
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v45, v57, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v37, v38, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v37, v38, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v37, v38, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v36, v35, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v36, v35, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v36, v35, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v34, v33, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v34, v33, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v34, v33, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v32, v31, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v32, v31, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v32, v31, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v30, v29, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v30, v29, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v30, v29, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v27, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v27, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v28, v27, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v17, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v17, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v25, v17, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_lshrrev_b32_e32 v47, 8, v45
|
|
; SI-NEXT: v_lshrrev_b32_e32 v43, 8, v37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v41, 8, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v55, 8, v34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v53, 8, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v51, 8, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 8, v28
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v25
|
|
; SI-NEXT: v_bfe_u32 v56, v26, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v46, v24, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v44, v23, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v42, v22, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v40, v21, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v54, v20, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v52, v19, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v50, v18, 8, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: .LBB104_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v57
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v45
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v47
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v56
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v38
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 8, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v37
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v43
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v46
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v35
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 16, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v41
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v44
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v33
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 24, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v55
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v42
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v31
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 32, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v32
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v53
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v40
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v29
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 40, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v30
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v51
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v54
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v27
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 48, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v49
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v52
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v17
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v25
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v50
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v64i8:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 16, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v1
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB104_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v15
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 8, v2
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v26, 8, v1
|
|
; VI-NEXT: .LBB104_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB104_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_mov_b32_e32 v17, 0x200
|
|
; VI-NEXT: v_add_f16_sdwa v49, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v49
|
|
; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
|
|
; VI-NEXT: v_add_f16_sdwa v52, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v28, v2, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v52
|
|
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
|
|
; VI-NEXT: v_add_f16_sdwa v39, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v27, v1, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
|
|
; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
|
|
; VI-NEXT: v_add_f16_sdwa v51, v3, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v23, v4, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v51
|
|
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
|
|
; VI-NEXT: v_add_f16_sdwa v37, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v22, v3, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v37
|
|
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
|
|
; VI-NEXT: v_add_f16_sdwa v50, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v54, v6, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v50
|
|
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
|
|
; VI-NEXT: v_add_f16_sdwa v35, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v53, v5, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v35
|
|
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
|
|
; VI-NEXT: v_add_f16_sdwa v48, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v25, v8, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
|
|
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
|
|
; VI-NEXT: v_add_f16_sdwa v33, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v24, v7, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v33
|
|
; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
|
|
; VI-NEXT: v_add_f16_sdwa v38, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v46, v10, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v38
|
|
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
|
|
; VI-NEXT: v_add_f16_sdwa v31, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v45, v9, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
|
|
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
|
|
; VI-NEXT: v_add_f16_sdwa v36, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v21, v12, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v36
|
|
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
|
|
; VI-NEXT: v_add_f16_sdwa v30, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v20, v11, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
|
|
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
|
|
; VI-NEXT: v_add_f16_sdwa v34, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v41, v14, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v34
|
|
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
|
|
; VI-NEXT: v_add_f16_sdwa v29, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_add_f16_sdwa v32, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v40, v13, v18
|
|
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
|
|
; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v32
|
|
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
|
|
; VI-NEXT: v_or_b32_e32 v43, v16, v18
|
|
; VI-NEXT: v_or_b32_e32 v42, v15, v17
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[42:43]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[40:41]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v43
|
|
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v42
|
|
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v20
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[20:21]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v41
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v21
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[45:46]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v46
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v25
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v24
|
|
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[24:25]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v22
|
|
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[22:23]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[53:54]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v23
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[27:28]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v40
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v45
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v54
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v53
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 8, v28
|
|
; VI-NEXT: v_lshrrev_b32_e32 v26, 8, v27
|
|
; VI-NEXT: v_bfe_u32 v27, v29, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v28, v30, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v45, v31, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v56, v33, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v59, v35, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v61, v37, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v53, v39, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v54, v49, 8, 8
|
|
; VI-NEXT: .LBB104_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v22, v52, v22, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v26, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v22
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v49, v54, s4
|
|
; VI-NEXT: v_perm_b32 v2, v2, v63, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v51, v21, s4
|
|
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v39, v53, s4
|
|
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v50, v25, s4
|
|
; VI-NEXT: v_perm_b32 v1, v5, v58, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v37, v61, s4
|
|
; VI-NEXT: v_perm_b32 v1, v6, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v48, v24, s4
|
|
; VI-NEXT: v_perm_b32 v1, v7, v47, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v35, v59, s4
|
|
; VI-NEXT: v_perm_b32 v1, v8, v46, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v38, v20, s4
|
|
; VI-NEXT: v_perm_b32 v1, v9, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v33, v56, s4
|
|
; VI-NEXT: v_perm_b32 v1, v10, v43, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v36, v19, s4
|
|
; VI-NEXT: v_perm_b32 v1, v11, v42, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v31, v45, s4
|
|
; VI-NEXT: v_perm_b32 v1, v12, v41, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v34, v18, s4
|
|
; VI-NEXT: v_perm_b32 v1, v13, v40, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v30, v28, s4
|
|
; VI-NEXT: v_perm_b32 v1, v14, v55, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v32, v17, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v15, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v29, v27, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v64i8:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB104_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v16
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, v22
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: .LBB104_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB104_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v16, v16, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v15, v15, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, v14, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, v13, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, v12, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, v11, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, v10, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, v9, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: .LBB104_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v22, v30, v24, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v22, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v21, v62, v21, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v61, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v21, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v43, v23, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v54, v20, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v27, v25, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32f16_to_v64i8:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB104_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB104_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB104_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-TRUE16-NEXT: .LBB104_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v1.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v3.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v2.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v65, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v4.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v4, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v55, v66, v55, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v5, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v7.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v25, v52, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v6.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v23, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v51, v21, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v6, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v25, v49, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v11.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v9.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v8.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v23, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v24, v19, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v21, v20, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v23, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v13.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v12.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v21, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v19, v18, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v30, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v28, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v19, v17, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v22, v26, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v55, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v19, 16, v16
|
|
; GFX11-TRUE16-NEXT: s_clause 0x3
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32f16_to_v64i8:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB104_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB104_2: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB104_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v16, 0x200, v16 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v15, 0x200, v15 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v14, 0x200, v14 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v13, 0x200, v13 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v12, 0x200, v12 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v11, 0x200, v11 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v10, 0x200, v10 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v9, 0x200, v9 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB104_4: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v24, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v70, v22, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v83, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v65, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v52, v20, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v86, v85, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v81, v80, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v69, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v67, v68, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v54, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v50, v49, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v37, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v18, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v29, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v28, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v27, v26, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v67, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
|
|
; GFX11-FAKE16-NEXT: s_clause 0x3
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32f16_to_v64i8_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_writelane_b32 v18, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v18, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v18, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v18, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v18, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v18, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v18, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v18, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v18, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v18, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v18, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v18, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v18, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v18, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v18, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v18, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v18, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v18, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v18, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v18, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v18, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v18, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v18, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v18, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v18, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v18, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v18, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v18, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v18, s86, 28
|
|
; SI-NEXT: v_writelane_b32 v18, s87, 29
|
|
; SI-NEXT: v_writelane_b32 v18, s96, 30
|
|
; SI-NEXT: v_writelane_b32 v18, s97, 31
|
|
; SI-NEXT: v_writelane_b32 v18, s98, 32
|
|
; SI-NEXT: v_writelane_b32 v18, s99, 33
|
|
; SI-NEXT: v_writelane_b32 v18, s30, 34
|
|
; SI-NEXT: v_writelane_b32 v18, s31, 35
|
|
; SI-NEXT: v_readfirstlane_b32 s98, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v1
|
|
; SI-NEXT: s_lshr_b32 s96, s29, 16
|
|
; SI-NEXT: s_lshr_b32 s97, s28, 16
|
|
; SI-NEXT: s_lshr_b32 s86, s27, 16
|
|
; SI-NEXT: s_lshr_b32 s87, s26, 16
|
|
; SI-NEXT: s_lshr_b32 s84, s25, 16
|
|
; SI-NEXT: s_lshr_b32 s85, s24, 16
|
|
; SI-NEXT: s_lshr_b32 s82, s23, 16
|
|
; SI-NEXT: s_lshr_b32 s83, s22, 16
|
|
; SI-NEXT: s_lshr_b32 s80, s21, 16
|
|
; SI-NEXT: s_lshr_b32 s81, s20, 16
|
|
; SI-NEXT: s_lshr_b32 s70, s19, 16
|
|
; SI-NEXT: s_lshr_b32 s71, s18, 16
|
|
; SI-NEXT: s_lshr_b32 s68, s17, 16
|
|
; SI-NEXT: s_lshr_b32 s69, s16, 16
|
|
; SI-NEXT: s_lshr_b32 s99, s98, 16
|
|
; SI-NEXT: s_lshr_b32 s46, s44, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; SI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; SI-NEXT: ; implicit-def: $vgpr19 : SGPR spill to VGPR lane
|
|
; SI-NEXT: s_cbranch_scc0 .LBB105_3
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s69, 16
|
|
; SI-NEXT: s_or_b32 s42, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s17, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s68, 16
|
|
; SI-NEXT: s_or_b32 s43, s4, s5
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 24
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v19, s4, 4
|
|
; SI-NEXT: v_writelane_b32 v19, s5, 5
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 16
|
|
; SI-NEXT: v_writelane_b32 v19, s4, 2
|
|
; SI-NEXT: v_writelane_b32 v19, s5, 3
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[42:43], 8
|
|
; SI-NEXT: v_writelane_b32 v19, s4, 0
|
|
; SI-NEXT: v_writelane_b32 v19, s5, 1
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s71, 16
|
|
; SI-NEXT: s_or_b32 s40, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s19, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s70, 16
|
|
; SI-NEXT: s_or_b32 s41, s4, s5
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[40:41], 24
|
|
; SI-NEXT: v_writelane_b32 v19, s4, 6
|
|
; SI-NEXT: v_writelane_b32 v19, s5, 7
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s81, 16
|
|
; SI-NEXT: s_or_b32 s14, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s80, 16
|
|
; SI-NEXT: s_or_b32 s15, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s22, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s83, 16
|
|
; SI-NEXT: s_or_b32 s12, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s23, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s82, 16
|
|
; SI-NEXT: s_or_b32 s13, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s24, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s85, 16
|
|
; SI-NEXT: s_or_b32 s10, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s25, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s84, 16
|
|
; SI-NEXT: s_or_b32 s11, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s26, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s87, 16
|
|
; SI-NEXT: s_or_b32 s8, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s27, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s86, 16
|
|
; SI-NEXT: s_or_b32 s9, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s28, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s97, 16
|
|
; SI-NEXT: s_or_b32 s6, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s96, 16
|
|
; SI-NEXT: s_or_b32 s7, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s44, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s5, s46, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s98, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s45, s99, 16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 8
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[14:15], 24
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[14:15], 16
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[14:15], 8
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[12:13], 24
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[12:13], 8
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[10:11], 24
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[10:11], 16
|
|
; SI-NEXT: s_or_b32 s5, s5, s45
|
|
; SI-NEXT: s_lshr_b32 s75, s43, 8
|
|
; SI-NEXT: s_lshr_b32 s73, s41, 8
|
|
; SI-NEXT: s_lshr_b32 s63, s15, 8
|
|
; SI-NEXT: s_lshr_b32 s61, s13, 8
|
|
; SI-NEXT: s_lshr_b32 s59, s11, 8
|
|
; SI-NEXT: s_lshr_b32 s57, s9, 8
|
|
; SI-NEXT: s_lshr_b32 s47, s7, 8
|
|
; SI-NEXT: s_lshr_b32 s45, s5, 8
|
|
; SI-NEXT: s_bfe_u32 s77, s68, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s79, s70, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s89, s80, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s91, s82, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s93, s84, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s95, s86, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s56, s96, 0x80008
|
|
; SI-NEXT: s_bfe_u32 s58, s99, 0x80008
|
|
; SI-NEXT: s_lshr_b64 s[66:67], s[10:11], 8
|
|
; SI-NEXT: s_lshr_b64 s[52:53], s[8:9], 24
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
|
|
; SI-NEXT: s_lshr_b64 s[64:65], s[8:9], 8
|
|
; SI-NEXT: s_lshr_b64 s[38:39], s[6:7], 24
|
|
; SI-NEXT: s_lshr_b64 s[48:49], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[50:51], s[6:7], 8
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[4:5], 8
|
|
; SI-NEXT: s_cbranch_execnz .LBB105_4
|
|
; SI-NEXT: .LBB105_2: ; %cmp.true
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s44
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v1, s46
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s99
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s16
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v1
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v1
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s98
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s97
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v4
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 16
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: v_readfirstlane_b32 s5, v1
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v2
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v2, s28
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: v_readfirstlane_b32 s6, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s96
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v2
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v2
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s29
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s87
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v2, v2
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v3
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v3, s26
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v2
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s86
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v3
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v3
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s27
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s85
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v3, v3
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: v_readfirstlane_b32 s9, v3
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v4
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v4, s24
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s84
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v4
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v4
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s25
|
|
; SI-NEXT: v_readfirstlane_b32 s11, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s83
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v4, v4
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: s_or_b32 s10, s11, s10
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v5
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v5, s22
|
|
; SI-NEXT: v_readfirstlane_b32 s11, v4
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 16
|
|
; SI-NEXT: s_or_b32 s11, s12, s11
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s82
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v5
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v5
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s23
|
|
; SI-NEXT: v_readfirstlane_b32 s13, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s81
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v5, v5
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: v_readfirstlane_b32 s13, v5
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s14, v6
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v6, s20
|
|
; SI-NEXT: s_or_b32 s13, s14, s13
|
|
; SI-NEXT: v_readfirstlane_b32 s14, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s80
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v6
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v6
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s21
|
|
; SI-NEXT: v_readfirstlane_b32 s15, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s71
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v6, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: s_or_b32 s14, s15, s14
|
|
; SI-NEXT: v_readfirstlane_b32 s20, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s18
|
|
; SI-NEXT: v_readfirstlane_b32 s18, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s70
|
|
; SI-NEXT: v_readfirstlane_b32 s15, v6
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 16
|
|
; SI-NEXT: s_or_b32 s15, s20, s15
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s20, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v7, s19
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v9, v8
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s69
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v7
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v8, v8
|
|
; SI-NEXT: s_or_b32 s40, s20, s18
|
|
; SI-NEXT: v_readfirstlane_b32 s18, v9
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s16, v7
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v10
|
|
; SI-NEXT: s_or_b32 s41, s16, s18
|
|
; SI-NEXT: v_readfirstlane_b32 s16, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v8, s68
|
|
; SI-NEXT: v_cvt_f32_f16_e32 v10, s17
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s17, v7
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v8
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v12, v7
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v10
|
|
; SI-NEXT: v_cvt_f16_f32_e32 v7, v7
|
|
; SI-NEXT: s_or_b32 s42, s17, s16
|
|
; SI-NEXT: v_readfirstlane_b32 s16, v12
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s17, v7
|
|
; SI-NEXT: s_or_b32 s43, s17, s16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[40:41], 8
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[14:15], 24
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[14:15], 16
|
|
; SI-NEXT: s_lshr_b64 s[18:19], s[42:43], 24
|
|
; SI-NEXT: s_lshr_b64 s[20:21], s[42:43], 16
|
|
; SI-NEXT: s_lshr_b64 s[24:25], s[42:43], 8
|
|
; SI-NEXT: s_lshr_b64 s[22:23], s[40:41], 24
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[14:15], 8
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[12:13], 24
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[12:13], 8
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[10:11], 24
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b64 s[66:67], s[10:11], 8
|
|
; SI-NEXT: s_lshr_b64 s[52:53], s[8:9], 24
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
|
|
; SI-NEXT: s_lshr_b64 s[64:65], s[8:9], 8
|
|
; SI-NEXT: s_lshr_b64 s[38:39], s[6:7], 24
|
|
; SI-NEXT: s_lshr_b64 s[48:49], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[50:51], s[6:7], 8
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[4:5], 24
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[4:5], 8
|
|
; SI-NEXT: s_lshr_b32 s75, s43, 8
|
|
; SI-NEXT: s_lshr_b32 s73, s41, 8
|
|
; SI-NEXT: s_lshr_b32 s63, s15, 8
|
|
; SI-NEXT: s_lshr_b32 s61, s13, 8
|
|
; SI-NEXT: s_lshr_b32 s59, s11, 8
|
|
; SI-NEXT: s_lshr_b32 s57, s9, 8
|
|
; SI-NEXT: s_lshr_b32 s47, s7, 8
|
|
; SI-NEXT: s_lshr_b32 s45, s5, 8
|
|
; SI-NEXT: v_bfe_u32 v16, v12, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v15, v9, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v14, v6, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v13, v5, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v11, v4, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v10, v3, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v8, v2, 8, 8
|
|
; SI-NEXT: v_bfe_u32 v7, v1, 8, 8
|
|
; SI-NEXT: s_branch .LBB105_5
|
|
; SI-NEXT: .LBB105_3:
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v19, s4, 0
|
|
; SI-NEXT: v_writelane_b32 v19, s5, 1
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr79
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr89
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr91
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr93
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr95
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $sgpr58
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr90
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr66
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr64
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr52
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr50
|
|
; SI-NEXT: ; implicit-def: $sgpr48
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr36
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: v_writelane_b32 v19, s4, 2
|
|
; SI-NEXT: v_writelane_b32 v19, s5, 3
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: v_writelane_b32 v19, s4, 4
|
|
; SI-NEXT: v_writelane_b32 v19, s5, 5
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: v_writelane_b32 v19, s4, 6
|
|
; SI-NEXT: v_writelane_b32 v19, s5, 7
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: s_branch .LBB105_2
|
|
; SI-NEXT: .LBB105_4:
|
|
; SI-NEXT: v_readlane_b32 s18, v19, 4
|
|
; SI-NEXT: v_readlane_b32 s20, v19, 2
|
|
; SI-NEXT: v_readlane_b32 s22, v19, 6
|
|
; SI-NEXT: v_readlane_b32 s24, v19, 0
|
|
; SI-NEXT: v_mov_b32_e32 v1, s99
|
|
; SI-NEXT: v_mov_b32_e32 v2, s96
|
|
; SI-NEXT: v_mov_b32_e32 v3, s86
|
|
; SI-NEXT: v_mov_b32_e32 v4, s84
|
|
; SI-NEXT: v_mov_b32_e32 v5, s82
|
|
; SI-NEXT: v_mov_b32_e32 v6, s80
|
|
; SI-NEXT: v_mov_b32_e32 v9, s70
|
|
; SI-NEXT: v_mov_b32_e32 v12, s68
|
|
; SI-NEXT: v_mov_b32_e32 v7, s58
|
|
; SI-NEXT: v_mov_b32_e32 v8, s56
|
|
; SI-NEXT: v_mov_b32_e32 v10, s95
|
|
; SI-NEXT: v_mov_b32_e32 v11, s93
|
|
; SI-NEXT: v_mov_b32_e32 v13, s91
|
|
; SI-NEXT: v_mov_b32_e32 v14, s89
|
|
; SI-NEXT: v_mov_b32_e32 v15, s79
|
|
; SI-NEXT: v_mov_b32_e32 v16, s77
|
|
; SI-NEXT: v_readlane_b32 s19, v19, 5
|
|
; SI-NEXT: v_readlane_b32 s21, v19, 3
|
|
; SI-NEXT: v_readlane_b32 s23, v19, 7
|
|
; SI-NEXT: v_readlane_b32 s25, v19, 1
|
|
; SI-NEXT: .LBB105_5: ; %end
|
|
; SI-NEXT: s_and_b32 s16, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s24, 8
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 24
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: v_mov_b32_e32 v17, s16
|
|
; SI-NEXT: s_and_b32 s16, s43, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s75, 8
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v16
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, s16, v12
|
|
; SI-NEXT: s_and_b32 s16, s40, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s74, 8
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s60, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_lshl_b32 s18, s22, 24
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s18, s17
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 4, v0
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_store_dword v12, v16, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 8, v0
|
|
; SI-NEXT: v_mov_b32_e32 v16, s16
|
|
; SI-NEXT: s_and_b32 s16, s41, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s73, 8
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: buffer_store_dword v16, v12, s[0:3], 0 offen
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v15
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v9, v12, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, s16, v9
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s16, s76, 8
|
|
; SI-NEXT: s_or_b32 s14, s14, s16
|
|
; SI-NEXT: s_and_b32 s16, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s62, 24
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 12, v0
|
|
; SI-NEXT: s_or_b32 s14, s14, s16
|
|
; SI-NEXT: buffer_store_dword v9, v12, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 16, v0
|
|
; SI-NEXT: v_mov_b32_e32 v12, s14
|
|
; SI-NEXT: s_and_b32 s14, s15, 0xff
|
|
; SI-NEXT: s_lshl_b32 s15, s63, 8
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: buffer_store_dword v12, v9, s[0:3], 0 offen
|
|
; SI-NEXT: s_or_b32 s14, s14, s15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v14
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v6, v9, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, s14, v6
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xff
|
|
; SI-NEXT: s_lshl_b32 s14, s94, 8
|
|
; SI-NEXT: s_or_b32 s12, s12, s14
|
|
; SI-NEXT: s_and_b32 s14, s90, 0xff
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_lshl_b32 s15, s78, 24
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_or_b32 s14, s15, s14
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 20, v0
|
|
; SI-NEXT: s_or_b32 s12, s12, s14
|
|
; SI-NEXT: buffer_store_dword v6, v9, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 24, v0
|
|
; SI-NEXT: v_mov_b32_e32 v9, s12
|
|
; SI-NEXT: s_and_b32 s12, s13, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s61, 8
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: buffer_store_dword v9, v6, s[0:3], 0 offen
|
|
; SI-NEXT: s_or_b32 s12, s12, s13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v13
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, s12, v5
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s12, s66, 8
|
|
; SI-NEXT: s_or_b32 s10, s10, s12
|
|
; SI-NEXT: s_and_b32 s12, s92, 0xff
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_lshl_b32 s13, s88, 24
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xffff
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 28, v0
|
|
; SI-NEXT: s_or_b32 s10, s10, s12
|
|
; SI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 32, v0
|
|
; SI-NEXT: v_mov_b32_e32 v6, s10
|
|
; SI-NEXT: s_and_b32 s10, s11, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s59, 8
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: buffer_store_dword v6, v5, s[0:3], 0 offen
|
|
; SI-NEXT: s_or_b32 s10, s10, s11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v11
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, s10, v4
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xff
|
|
; SI-NEXT: s_lshl_b32 s10, s64, 8
|
|
; SI-NEXT: s_or_b32 s8, s8, s10
|
|
; SI-NEXT: s_and_b32 s10, s54, 0xff
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s52, 24
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s10, s11, s10
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 36, v0
|
|
; SI-NEXT: s_or_b32 s8, s8, s10
|
|
; SI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 40, v0
|
|
; SI-NEXT: v_mov_b32_e32 v5, s8
|
|
; SI-NEXT: s_and_b32 s8, s9, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s57, 8
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: buffer_store_dword v5, v4, s[0:3], 0 offen
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v10
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, s8, v3
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xff
|
|
; SI-NEXT: s_lshl_b32 s8, s50, 8
|
|
; SI-NEXT: s_or_b32 s6, s6, s8
|
|
; SI-NEXT: s_and_b32 s8, s48, 0xff
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_lshl_b32 s9, s38, 24
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 44, v0
|
|
; SI-NEXT: s_or_b32 s6, s6, s8
|
|
; SI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 48, v0
|
|
; SI-NEXT: v_mov_b32_e32 v4, s6
|
|
; SI-NEXT: s_and_b32 s6, s7, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s47, 8
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v8
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, s6, v2
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s36, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: s_and_b32 s6, s34, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s30, 24
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 52, v0
|
|
; SI-NEXT: s_or_b32 s4, s4, s6
|
|
; SI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 56, v0
|
|
; SI-NEXT: v_mov_b32_e32 v3, s4
|
|
; SI-NEXT: s_and_b32 s4, s5, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s45, 8
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v7
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, s4, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: v_readlane_b32 s30, v18, 34
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: v_readlane_b32 s31, v18, 35
|
|
; SI-NEXT: v_readlane_b32 s99, v18, 33
|
|
; SI-NEXT: v_readlane_b32 s98, v18, 32
|
|
; SI-NEXT: v_readlane_b32 s97, v18, 31
|
|
; SI-NEXT: v_readlane_b32 s96, v18, 30
|
|
; SI-NEXT: v_readlane_b32 s87, v18, 29
|
|
; SI-NEXT: v_readlane_b32 s86, v18, 28
|
|
; SI-NEXT: v_readlane_b32 s85, v18, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v18, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v18, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v18, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v18, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v18, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v18, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v18, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v18, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v18, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v18, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v18, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v18, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v18, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v18, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v18, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v18, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v18, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v18, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v18, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v18, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v18, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v18, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v18, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v18, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v18, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v18, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v18, 0
|
|
; SI-NEXT: s_xor_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32f16_to_v64i8_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_writelane_b32 v63, s34, 0
|
|
; VI-NEXT: v_writelane_b32 v63, s35, 1
|
|
; VI-NEXT: v_writelane_b32 v63, s36, 2
|
|
; VI-NEXT: v_writelane_b32 v63, s37, 3
|
|
; VI-NEXT: v_writelane_b32 v63, s38, 4
|
|
; VI-NEXT: v_writelane_b32 v63, s39, 5
|
|
; VI-NEXT: v_writelane_b32 v63, s48, 6
|
|
; VI-NEXT: v_writelane_b32 v63, s49, 7
|
|
; VI-NEXT: v_writelane_b32 v63, s50, 8
|
|
; VI-NEXT: v_writelane_b32 v63, s51, 9
|
|
; VI-NEXT: v_writelane_b32 v63, s52, 10
|
|
; VI-NEXT: v_writelane_b32 v63, s53, 11
|
|
; VI-NEXT: v_writelane_b32 v63, s54, 12
|
|
; VI-NEXT: v_writelane_b32 v63, s55, 13
|
|
; VI-NEXT: v_writelane_b32 v63, s64, 14
|
|
; VI-NEXT: v_writelane_b32 v63, s65, 15
|
|
; VI-NEXT: v_writelane_b32 v63, s66, 16
|
|
; VI-NEXT: v_writelane_b32 v63, s67, 17
|
|
; VI-NEXT: v_writelane_b32 v63, s30, 18
|
|
; VI-NEXT: v_writelane_b32 v63, s31, 19
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; VI-NEXT: s_cbranch_scc0 .LBB105_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_lshr_b32 s88, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s36, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s63, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s37, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s79, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s89, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s62, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s39, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s78, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s90, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s48, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s61, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s49, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s77, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s91, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s50, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s60, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s51, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s76, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s30, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s52, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s59, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s53, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s75, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s31, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s54, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s58, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s55, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s74, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s34, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s57, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s65, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s73, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s35, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s66, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s56, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s67, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s72, s16, 8
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; VI-NEXT: s_cbranch_execnz .LBB105_4
|
|
; VI-NEXT: .LBB105_2: ; %cmp.true
|
|
; VI-NEXT: s_lshr_b32 s6, s17, 16
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0x200
|
|
; VI-NEXT: v_add_f16_e32 v11, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s16, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
|
|
; VI-NEXT: v_add_f16_e32 v25, s17, v1
|
|
; VI-NEXT: v_add_f16_e32 v18, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s19, 16
|
|
; VI-NEXT: v_or_b32_e32 v10, v25, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v18
|
|
; VI-NEXT: v_add_f16_e32 v33, s16, v1
|
|
; VI-NEXT: v_add_f16_e32 v12, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s18, 16
|
|
; VI-NEXT: v_or_b32_e32 v9, v33, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
|
|
; VI-NEXT: v_add_f16_e32 v27, s19, v1
|
|
; VI-NEXT: v_add_f16_e32 v20, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s21, 16
|
|
; VI-NEXT: v_or_b32_e32 v52, v27, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
|
|
; VI-NEXT: v_add_f16_e32 v35, s18, v1
|
|
; VI-NEXT: v_add_f16_e32 v13, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s20, 16
|
|
; VI-NEXT: v_or_b32_e32 v51, v35, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
|
|
; VI-NEXT: v_add_f16_e32 v28, s21, v1
|
|
; VI-NEXT: v_add_f16_e32 v21, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s23, 16
|
|
; VI-NEXT: v_or_b32_e32 v8, v28, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
|
|
; VI-NEXT: v_add_f16_e32 v37, s20, v1
|
|
; VI-NEXT: v_add_f16_e32 v14, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s22, 16
|
|
; VI-NEXT: v_or_b32_e32 v7, v37, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
|
|
; VI-NEXT: v_add_f16_e32 v30, s23, v1
|
|
; VI-NEXT: v_add_f16_e32 v22, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s25, 16
|
|
; VI-NEXT: v_or_b32_e32 v57, v30, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
|
|
; VI-NEXT: v_add_f16_e32 v38, s22, v1
|
|
; VI-NEXT: v_add_f16_e32 v15, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s24, 16
|
|
; VI-NEXT: v_or_b32_e32 v56, v38, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
|
|
; VI-NEXT: v_add_f16_e32 v31, s25, v1
|
|
; VI-NEXT: v_add_f16_e32 v23, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s27, 16
|
|
; VI-NEXT: v_or_b32_e32 v6, v31, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
|
|
; VI-NEXT: v_add_f16_e32 v39, s24, v1
|
|
; VI-NEXT: v_add_f16_e32 v16, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s26, 16
|
|
; VI-NEXT: v_or_b32_e32 v5, v39, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
|
|
; VI-NEXT: v_add_f16_e32 v32, s27, v1
|
|
; VI-NEXT: v_add_f16_e32 v24, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s29, 16
|
|
; VI-NEXT: v_or_b32_e32 v42, v32, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v24
|
|
; VI-NEXT: v_add_f16_e32 v48, s26, v1
|
|
; VI-NEXT: v_add_f16_e32 v17, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s28, 16
|
|
; VI-NEXT: v_or_b32_e32 v41, v48, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
|
|
; VI-NEXT: v_add_f16_e32 v34, s29, v1
|
|
; VI-NEXT: v_add_f16_e32 v26, s6, v1
|
|
; VI-NEXT: s_lshr_b32 s6, s5, 16
|
|
; VI-NEXT: v_or_b32_e32 v55, v34, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
|
|
; VI-NEXT: v_add_f16_e32 v49, s28, v1
|
|
; VI-NEXT: v_add_f16_e32 v19, s6, v1
|
|
; VI-NEXT: v_add_f16_e32 v36, s5, v1
|
|
; VI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; VI-NEXT: v_or_b32_e32 v54, v49, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
|
|
; VI-NEXT: v_add_f16_e32 v29, s5, v1
|
|
; VI-NEXT: v_or_b32_e32 v44, v36, v2
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
|
|
; VI-NEXT: v_add_f16_e32 v50, s4, v1
|
|
; VI-NEXT: v_or_b32_e32 v43, v50, v2
|
|
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[43:44]
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[54:55]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v43
|
|
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[41:42]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v44
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v5
|
|
; VI-NEXT: v_lshrrev_b64 v[4:5], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v55
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v42
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v6
|
|
; VI-NEXT: v_lshrrev_b64 v[5:6], 24, v[56:57]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v7
|
|
; VI-NEXT: v_lshrrev_b64 v[6:7], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v57
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v8
|
|
; VI-NEXT: v_lshrrev_b64 v[7:8], 24, v[51:52]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v52
|
|
; VI-NEXT: v_mov_b32_e32 v52, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v9
|
|
; VI-NEXT: v_lshrrev_b64 v[8:9], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 8, v54
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 8, v41
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v56
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 8, v51
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 8, v10
|
|
; VI-NEXT: v_bfe_u32 v9, v19, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v10, v17, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v41, v16, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v43, v15, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v46, v14, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v56, v13, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v59, v12, 8, 8
|
|
; VI-NEXT: v_bfe_u32 v62, v11, 8, 8
|
|
; VI-NEXT: s_branch .LBB105_5
|
|
; VI-NEXT: .LBB105_3:
|
|
; VI-NEXT: ; implicit-def: $sgpr72
|
|
; VI-NEXT: ; implicit-def: $sgpr67
|
|
; VI-NEXT: ; implicit-def: $sgpr6
|
|
; VI-NEXT: ; implicit-def: $sgpr56
|
|
; VI-NEXT: ; implicit-def: $sgpr66
|
|
; VI-NEXT: ; implicit-def: $sgpr35
|
|
; VI-NEXT: ; implicit-def: $sgpr73
|
|
; VI-NEXT: ; implicit-def: $sgpr65
|
|
; VI-NEXT: ; implicit-def: $sgpr8
|
|
; VI-NEXT: ; implicit-def: $sgpr57
|
|
; VI-NEXT: ; implicit-def: $sgpr64
|
|
; VI-NEXT: ; implicit-def: $sgpr34
|
|
; VI-NEXT: ; implicit-def: $sgpr74
|
|
; VI-NEXT: ; implicit-def: $sgpr55
|
|
; VI-NEXT: ; implicit-def: $sgpr10
|
|
; VI-NEXT: ; implicit-def: $sgpr58
|
|
; VI-NEXT: ; implicit-def: $sgpr54
|
|
; VI-NEXT: ; implicit-def: $sgpr31
|
|
; VI-NEXT: ; implicit-def: $sgpr75
|
|
; VI-NEXT: ; implicit-def: $sgpr53
|
|
; VI-NEXT: ; implicit-def: $sgpr12
|
|
; VI-NEXT: ; implicit-def: $sgpr59
|
|
; VI-NEXT: ; implicit-def: $sgpr52
|
|
; VI-NEXT: ; implicit-def: $sgpr30
|
|
; VI-NEXT: ; implicit-def: $sgpr76
|
|
; VI-NEXT: ; implicit-def: $sgpr51
|
|
; VI-NEXT: ; implicit-def: $sgpr14
|
|
; VI-NEXT: ; implicit-def: $sgpr60
|
|
; VI-NEXT: ; implicit-def: $sgpr50
|
|
; VI-NEXT: ; implicit-def: $sgpr91
|
|
; VI-NEXT: ; implicit-def: $sgpr77
|
|
; VI-NEXT: ; implicit-def: $sgpr49
|
|
; VI-NEXT: ; implicit-def: $sgpr40
|
|
; VI-NEXT: ; implicit-def: $sgpr61
|
|
; VI-NEXT: ; implicit-def: $sgpr48
|
|
; VI-NEXT: ; implicit-def: $sgpr90
|
|
; VI-NEXT: ; implicit-def: $sgpr78
|
|
; VI-NEXT: ; implicit-def: $sgpr39
|
|
; VI-NEXT: ; implicit-def: $sgpr42
|
|
; VI-NEXT: ; implicit-def: $sgpr62
|
|
; VI-NEXT: ; implicit-def: $sgpr38
|
|
; VI-NEXT: ; implicit-def: $sgpr89
|
|
; VI-NEXT: ; implicit-def: $sgpr79
|
|
; VI-NEXT: ; implicit-def: $sgpr37
|
|
; VI-NEXT: ; implicit-def: $sgpr44
|
|
; VI-NEXT: ; implicit-def: $sgpr63
|
|
; VI-NEXT: ; implicit-def: $sgpr36
|
|
; VI-NEXT: ; implicit-def: $sgpr88
|
|
; VI-NEXT: s_branch .LBB105_2
|
|
; VI-NEXT: .LBB105_4:
|
|
; VI-NEXT: v_mov_b32_e32 v2, s44
|
|
; VI-NEXT: v_mov_b32_e32 v1, s79
|
|
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v18, s67
|
|
; VI-NEXT: v_mov_b32_e32 v11, s66
|
|
; VI-NEXT: v_mov_b32_e32 v20, s65
|
|
; VI-NEXT: v_mov_b32_e32 v12, s64
|
|
; VI-NEXT: v_mov_b32_e32 v21, s55
|
|
; VI-NEXT: v_mov_b32_e32 v13, s54
|
|
; VI-NEXT: v_mov_b32_e32 v22, s53
|
|
; VI-NEXT: v_mov_b32_e32 v14, s52
|
|
; VI-NEXT: v_mov_b32_e32 v23, s51
|
|
; VI-NEXT: v_mov_b32_e32 v15, s50
|
|
; VI-NEXT: v_mov_b32_e32 v24, s49
|
|
; VI-NEXT: v_mov_b32_e32 v16, s48
|
|
; VI-NEXT: v_mov_b32_e32 v26, s39
|
|
; VI-NEXT: v_mov_b32_e32 v17, s38
|
|
; VI-NEXT: v_mov_b32_e32 v29, s37
|
|
; VI-NEXT: v_mov_b32_e32 v19, s36
|
|
; VI-NEXT: v_mov_b32_e32 v33, s16
|
|
; VI-NEXT: v_mov_b32_e32 v25, s17
|
|
; VI-NEXT: v_mov_b32_e32 v35, s18
|
|
; VI-NEXT: v_mov_b32_e32 v27, s19
|
|
; VI-NEXT: v_mov_b32_e32 v37, s20
|
|
; VI-NEXT: v_mov_b32_e32 v28, s21
|
|
; VI-NEXT: v_mov_b32_e32 v38, s22
|
|
; VI-NEXT: v_mov_b32_e32 v30, s23
|
|
; VI-NEXT: v_mov_b32_e32 v39, s24
|
|
; VI-NEXT: v_mov_b32_e32 v31, s25
|
|
; VI-NEXT: v_mov_b32_e32 v48, s26
|
|
; VI-NEXT: v_mov_b32_e32 v32, s27
|
|
; VI-NEXT: v_mov_b32_e32 v49, s28
|
|
; VI-NEXT: v_mov_b32_e32 v34, s29
|
|
; VI-NEXT: v_mov_b32_e32 v50, s4
|
|
; VI-NEXT: v_mov_b32_e32 v36, s5
|
|
; VI-NEXT: v_mov_b32_e32 v9, s88
|
|
; VI-NEXT: v_mov_b32_e32 v10, s89
|
|
; VI-NEXT: v_mov_b32_e32 v41, s90
|
|
; VI-NEXT: v_mov_b32_e32 v43, s91
|
|
; VI-NEXT: v_mov_b32_e32 v46, s30
|
|
; VI-NEXT: v_mov_b32_e32 v56, s31
|
|
; VI-NEXT: v_mov_b32_e32 v59, s34
|
|
; VI-NEXT: v_mov_b32_e32 v62, s35
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v52, s63
|
|
; VI-NEXT: v_mov_b32_e32 v54, s78
|
|
; VI-NEXT: v_mov_b32_e32 v53, s62
|
|
; VI-NEXT: v_mov_b32_e32 v40, s77
|
|
; VI-NEXT: v_mov_b32_e32 v55, s61
|
|
; VI-NEXT: v_mov_b32_e32 v44, s76
|
|
; VI-NEXT: v_mov_b32_e32 v42, s60
|
|
; VI-NEXT: v_mov_b32_e32 v47, s75
|
|
; VI-NEXT: v_mov_b32_e32 v45, s59
|
|
; VI-NEXT: v_mov_b32_e32 v58, s74
|
|
; VI-NEXT: v_mov_b32_e32 v57, s58
|
|
; VI-NEXT: v_mov_b32_e32 v61, s73
|
|
; VI-NEXT: v_mov_b32_e32 v60, s57
|
|
; VI-NEXT: v_mov_b32_e32 v1, s72
|
|
; VI-NEXT: v_mov_b32_e32 v51, s56
|
|
; VI-NEXT: v_mov_b32_e32 v2, s42
|
|
; VI-NEXT: v_mov_b32_e32 v3, s40
|
|
; VI-NEXT: v_mov_b32_e32 v4, s14
|
|
; VI-NEXT: v_mov_b32_e32 v5, s12
|
|
; VI-NEXT: v_mov_b32_e32 v6, s10
|
|
; VI-NEXT: v_mov_b32_e32 v7, s8
|
|
; VI-NEXT: v_mov_b32_e32 v8, s6
|
|
; VI-NEXT: .LBB105_5: ; %end
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v8, v18, v8, s4
|
|
; VI-NEXT: v_perm_b32 v1, v33, v1, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v8
|
|
; VI-NEXT: v_perm_b32 v8, v11, v62, s4
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v25, v51, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v8
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v8, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v20, v7, s4
|
|
; VI-NEXT: v_perm_b32 v7, v35, v61, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v7, v1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v7, v12, v59, s4
|
|
; VI-NEXT: v_perm_b32 v1, v27, v60, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v7
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 12, v0
|
|
; VI-NEXT: v_perm_b32 v6, v21, v6, s4
|
|
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v37, v58, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v6
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v6, v13, v56, s4
|
|
; VI-NEXT: v_perm_b32 v1, v28, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v6
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 20, v0
|
|
; VI-NEXT: v_perm_b32 v5, v22, v5, s4
|
|
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v38, v47, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v5
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v5, v14, v46, s4
|
|
; VI-NEXT: v_perm_b32 v1, v30, v45, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v5
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 28, v0
|
|
; VI-NEXT: v_perm_b32 v4, v23, v4, s4
|
|
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v39, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v4
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v4, v15, v43, s4
|
|
; VI-NEXT: v_perm_b32 v1, v31, v42, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v4
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
|
|
; VI-NEXT: v_perm_b32 v3, v24, v3, s4
|
|
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v48, v40, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v3, v16, v41, s4
|
|
; VI-NEXT: v_perm_b32 v1, v32, v55, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
|
|
; VI-NEXT: v_perm_b32 v2, v26, v2, s4
|
|
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v49, v54, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v17, v10, s4
|
|
; VI-NEXT: v_perm_b32 v1, v34, v53, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_readlane_b32 s30, v63, 18
|
|
; VI-NEXT: v_readlane_b32 s31, v63, 19
|
|
; VI-NEXT: v_readlane_b32 s67, v63, 17
|
|
; VI-NEXT: v_readlane_b32 s66, v63, 16
|
|
; VI-NEXT: v_readlane_b32 s65, v63, 15
|
|
; VI-NEXT: v_readlane_b32 s64, v63, 14
|
|
; VI-NEXT: v_readlane_b32 s55, v63, 13
|
|
; VI-NEXT: v_readlane_b32 s54, v63, 12
|
|
; VI-NEXT: v_readlane_b32 s53, v63, 11
|
|
; VI-NEXT: v_readlane_b32 s52, v63, 10
|
|
; VI-NEXT: v_readlane_b32 s51, v63, 9
|
|
; VI-NEXT: v_readlane_b32 s50, v63, 8
|
|
; VI-NEXT: v_readlane_b32 s49, v63, 7
|
|
; VI-NEXT: v_readlane_b32 s48, v63, 6
|
|
; VI-NEXT: v_readlane_b32 s39, v63, 5
|
|
; VI-NEXT: v_readlane_b32 s38, v63, 4
|
|
; VI-NEXT: v_readlane_b32 s37, v63, 3
|
|
; VI-NEXT: v_readlane_b32 s36, v63, 2
|
|
; VI-NEXT: v_readlane_b32 s35, v63, 1
|
|
; VI-NEXT: v_readlane_b32 s34, v63, 0
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_perm_b32 v2, v29, v2, s4
|
|
; VI-NEXT: v_perm_b32 v1, v50, v1, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v19, v9, s4
|
|
; VI-NEXT: v_perm_b32 v1, v36, v52, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32f16_to_v64i8_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
|
|
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
|
|
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
|
|
; GFX9-NEXT: v_writelane_b32 v63, s37, 3
|
|
; GFX9-NEXT: v_writelane_b32 v63, s38, 4
|
|
; GFX9-NEXT: v_writelane_b32 v63, s39, 5
|
|
; GFX9-NEXT: v_writelane_b32 v63, s48, 6
|
|
; GFX9-NEXT: v_writelane_b32 v63, s49, 7
|
|
; GFX9-NEXT: v_writelane_b32 v63, s50, 8
|
|
; GFX9-NEXT: v_writelane_b32 v63, s51, 9
|
|
; GFX9-NEXT: v_writelane_b32 v63, s52, 10
|
|
; GFX9-NEXT: v_writelane_b32 v63, s53, 11
|
|
; GFX9-NEXT: v_writelane_b32 v63, s54, 12
|
|
; GFX9-NEXT: v_writelane_b32 v63, s55, 13
|
|
; GFX9-NEXT: v_writelane_b32 v63, s30, 14
|
|
; GFX9-NEXT: v_writelane_b32 v63, s31, 15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB105_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_lshr_b32 s56, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s57, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s59, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s58, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s60, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s61, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s62, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s72, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s63, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s74, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s75, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s77, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s76, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s78, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s79, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s88, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s90, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s89, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s91, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s92, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s93, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s95, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s94, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s30, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s36, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s35, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s37, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s38, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s39, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s49, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s48, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s50, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s52, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s54, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s53, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB105_4
|
|
; GFX9-NEXT: .LBB105_2: ; %cmp.true
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0x200
|
|
; GFX9-NEXT: v_pk_add_f16 v19, s17, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v18, s16, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v14, s19, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v13, s18, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v12, s21, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v11, s20, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v10, s23, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v9, s22, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v8, s25, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v7, s24, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v6, s27, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v5, s26, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v4, s29, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v3, s28, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v2, s5, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_pk_add_f16 v1, s4, v1 op_sel_hi:[1,0]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[25:26], 24, v[18:19]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v18
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v18
|
|
; GFX9-NEXT: s_branch .LBB105_5
|
|
; GFX9-NEXT: .LBB105_3:
|
|
; GFX9-NEXT: ; implicit-def: $sgpr55
|
|
; GFX9-NEXT: ; implicit-def: $sgpr53
|
|
; GFX9-NEXT: ; implicit-def: $sgpr6
|
|
; GFX9-NEXT: ; implicit-def: $sgpr54
|
|
; GFX9-NEXT: ; implicit-def: $sgpr52
|
|
; GFX9-NEXT: ; implicit-def: $sgpr51
|
|
; GFX9-NEXT: ; implicit-def: $sgpr50
|
|
; GFX9-NEXT: ; implicit-def: $sgpr48
|
|
; GFX9-NEXT: ; implicit-def: $sgpr8
|
|
; GFX9-NEXT: ; implicit-def: $sgpr49
|
|
; GFX9-NEXT: ; implicit-def: $sgpr39
|
|
; GFX9-NEXT: ; implicit-def: $sgpr38
|
|
; GFX9-NEXT: ; implicit-def: $sgpr37
|
|
; GFX9-NEXT: ; implicit-def: $sgpr35
|
|
; GFX9-NEXT: ; implicit-def: $sgpr10
|
|
; GFX9-NEXT: ; implicit-def: $sgpr36
|
|
; GFX9-NEXT: ; implicit-def: $sgpr34
|
|
; GFX9-NEXT: ; implicit-def: $sgpr31
|
|
; GFX9-NEXT: ; implicit-def: $sgpr30
|
|
; GFX9-NEXT: ; implicit-def: $sgpr94
|
|
; GFX9-NEXT: ; implicit-def: $sgpr12
|
|
; GFX9-NEXT: ; implicit-def: $sgpr95
|
|
; GFX9-NEXT: ; implicit-def: $sgpr93
|
|
; GFX9-NEXT: ; implicit-def: $sgpr92
|
|
; GFX9-NEXT: ; implicit-def: $sgpr91
|
|
; GFX9-NEXT: ; implicit-def: $sgpr89
|
|
; GFX9-NEXT: ; implicit-def: $sgpr14
|
|
; GFX9-NEXT: ; implicit-def: $sgpr90
|
|
; GFX9-NEXT: ; implicit-def: $sgpr88
|
|
; GFX9-NEXT: ; implicit-def: $sgpr79
|
|
; GFX9-NEXT: ; implicit-def: $sgpr78
|
|
; GFX9-NEXT: ; implicit-def: $sgpr76
|
|
; GFX9-NEXT: ; implicit-def: $sgpr40
|
|
; GFX9-NEXT: ; implicit-def: $sgpr77
|
|
; GFX9-NEXT: ; implicit-def: $sgpr75
|
|
; GFX9-NEXT: ; implicit-def: $sgpr74
|
|
; GFX9-NEXT: ; implicit-def: $sgpr73
|
|
; GFX9-NEXT: ; implicit-def: $sgpr63
|
|
; GFX9-NEXT: ; implicit-def: $sgpr42
|
|
; GFX9-NEXT: ; implicit-def: $sgpr72
|
|
; GFX9-NEXT: ; implicit-def: $sgpr62
|
|
; GFX9-NEXT: ; implicit-def: $sgpr61
|
|
; GFX9-NEXT: ; implicit-def: $sgpr60
|
|
; GFX9-NEXT: ; implicit-def: $sgpr58
|
|
; GFX9-NEXT: ; implicit-def: $sgpr44
|
|
; GFX9-NEXT: ; implicit-def: $sgpr59
|
|
; GFX9-NEXT: ; implicit-def: $sgpr57
|
|
; GFX9-NEXT: ; implicit-def: $sgpr56
|
|
; GFX9-NEXT: s_branch .LBB105_2
|
|
; GFX9-NEXT: .LBB105_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s44
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s42
|
|
; GFX9-NEXT: v_mov_b32_e32 v18, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s5
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s55
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, s53
|
|
; GFX9-NEXT: v_mov_b32_e32 v62, s54
|
|
; GFX9-NEXT: v_mov_b32_e32 v59, s52
|
|
; GFX9-NEXT: v_mov_b32_e32 v60, s51
|
|
; GFX9-NEXT: v_mov_b32_e32 v58, s50
|
|
; GFX9-NEXT: v_mov_b32_e32 v61, s48
|
|
; GFX9-NEXT: v_mov_b32_e32 v57, s49
|
|
; GFX9-NEXT: v_mov_b32_e32 v47, s39
|
|
; GFX9-NEXT: v_mov_b32_e32 v56, s38
|
|
; GFX9-NEXT: v_mov_b32_e32 v46, s37
|
|
; GFX9-NEXT: v_mov_b32_e32 v45, s35
|
|
; GFX9-NEXT: v_mov_b32_e32 v44, s36
|
|
; GFX9-NEXT: v_mov_b32_e32 v42, s34
|
|
; GFX9-NEXT: v_mov_b32_e32 v43, s31
|
|
; GFX9-NEXT: v_mov_b32_e32 v41, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v40, s94
|
|
; GFX9-NEXT: v_mov_b32_e32 v55, s95
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, s93
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, s92
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, s91
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, s89
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, s90
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, s88
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, s79
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, s78
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, s76
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, s77
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, s75
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, s74
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, s73
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, s63
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, s72
|
|
; GFX9-NEXT: v_mov_b32_e32 v30, s62
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, s61
|
|
; GFX9-NEXT: v_mov_b32_e32 v29, s60
|
|
; GFX9-NEXT: v_mov_b32_e32 v28, s58
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, s59
|
|
; GFX9-NEXT: v_mov_b32_e32 v17, s57
|
|
; GFX9-NEXT: v_mov_b32_e32 v26, s56
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s12
|
|
; GFX9-NEXT: v_mov_b32_e32 v23, s10
|
|
; GFX9-NEXT: v_mov_b32_e32 v24, s8
|
|
; GFX9-NEXT: v_mov_b32_e32 v25, s6
|
|
; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s40
|
|
; GFX9-NEXT: v_mov_b32_e32 v21, s14
|
|
; GFX9-NEXT: .LBB105_5: ; %end
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
|
|
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
|
|
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
|
|
; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
|
|
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
|
|
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
|
|
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
|
|
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
|
|
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
|
|
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
|
|
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
|
|
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
|
|
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
|
|
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v34, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v29, s4
|
|
; GFX9-NEXT: v_readlane_b32 s30, v63, 14
|
|
; GFX9-NEXT: v_readlane_b32 s31, v63, 15
|
|
; GFX9-NEXT: v_readlane_b32 s55, v63, 13
|
|
; GFX9-NEXT: v_readlane_b32 s54, v63, 12
|
|
; GFX9-NEXT: v_readlane_b32 s53, v63, 11
|
|
; GFX9-NEXT: v_readlane_b32 s52, v63, 10
|
|
; GFX9-NEXT: v_readlane_b32 s51, v63, 9
|
|
; GFX9-NEXT: v_readlane_b32 s50, v63, 8
|
|
; GFX9-NEXT: v_readlane_b32 s49, v63, 7
|
|
; GFX9-NEXT: v_readlane_b32 s48, v63, 6
|
|
; GFX9-NEXT: v_readlane_b32 s39, v63, 5
|
|
; GFX9-NEXT: v_readlane_b32 s38, v63, 4
|
|
; GFX9-NEXT: v_readlane_b32 s37, v63, 3
|
|
; GFX9-NEXT: v_readlane_b32 s36, v63, 2
|
|
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
|
|
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
|
|
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-LABEL: bitcast_v32f16_to_v64i8_scalar:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-NEXT: s_or_saveexec_b32 s4, -1
|
|
; GFX11-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s4
|
|
; GFX11-NEXT: v_writelane_b32 v40, s34, 0
|
|
; GFX11-NEXT: v_writelane_b32 v40, s35, 1
|
|
; GFX11-NEXT: v_writelane_b32 v40, s36, 2
|
|
; GFX11-NEXT: v_writelane_b32 v40, s37, 3
|
|
; GFX11-NEXT: v_writelane_b32 v40, s38, 4
|
|
; GFX11-NEXT: v_writelane_b32 v40, s39, 5
|
|
; GFX11-NEXT: v_writelane_b32 v40, s48, 6
|
|
; GFX11-NEXT: v_writelane_b32 v40, s49, 7
|
|
; GFX11-NEXT: v_writelane_b32 v40, s30, 8
|
|
; GFX11-NEXT: v_writelane_b32 v40, s31, 9
|
|
; GFX11-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-NEXT: s_mov_b32 s42, 0
|
|
; GFX11-NEXT: s_cbranch_scc0 .LBB105_3
|
|
; GFX11-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-NEXT: s_lshr_b32 s43, s27, 24
|
|
; GFX11-NEXT: s_lshr_b32 s44, s27, 16
|
|
; GFX11-NEXT: s_lshr_b32 s46, s27, 8
|
|
; GFX11-NEXT: s_lshr_b32 s45, s26, 16
|
|
; GFX11-NEXT: s_lshr_b32 s47, s26, 8
|
|
; GFX11-NEXT: s_lshr_b32 s56, s25, 24
|
|
; GFX11-NEXT: s_lshr_b32 s57, s25, 16
|
|
; GFX11-NEXT: s_lshr_b32 s59, s25, 8
|
|
; GFX11-NEXT: s_lshr_b32 s58, s24, 16
|
|
; GFX11-NEXT: s_lshr_b32 s60, s24, 8
|
|
; GFX11-NEXT: s_lshr_b32 s61, s23, 24
|
|
; GFX11-NEXT: s_lshr_b32 s62, s23, 16
|
|
; GFX11-NEXT: s_lshr_b32 s72, s23, 8
|
|
; GFX11-NEXT: s_lshr_b32 s63, s22, 16
|
|
; GFX11-NEXT: s_lshr_b32 s73, s22, 8
|
|
; GFX11-NEXT: s_lshr_b32 s74, s21, 24
|
|
; GFX11-NEXT: s_lshr_b32 s75, s21, 16
|
|
; GFX11-NEXT: s_lshr_b32 s77, s21, 8
|
|
; GFX11-NEXT: s_lshr_b32 s76, s20, 16
|
|
; GFX11-NEXT: s_lshr_b32 s78, s20, 8
|
|
; GFX11-NEXT: s_lshr_b32 s79, s19, 24
|
|
; GFX11-NEXT: s_lshr_b32 s88, s19, 16
|
|
; GFX11-NEXT: s_lshr_b32 s90, s19, 8
|
|
; GFX11-NEXT: s_lshr_b32 s89, s18, 16
|
|
; GFX11-NEXT: s_lshr_b32 s91, s18, 8
|
|
; GFX11-NEXT: s_lshr_b32 s92, s17, 24
|
|
; GFX11-NEXT: s_lshr_b32 s93, s17, 16
|
|
; GFX11-NEXT: s_lshr_b32 s95, s17, 8
|
|
; GFX11-NEXT: s_lshr_b32 s94, s16, 16
|
|
; GFX11-NEXT: s_lshr_b32 vcc_hi, s16, 8
|
|
; GFX11-NEXT: s_lshr_b32 s30, s3, 24
|
|
; GFX11-NEXT: s_lshr_b32 s31, s3, 16
|
|
; GFX11-NEXT: s_lshr_b32 s35, s3, 8
|
|
; GFX11-NEXT: s_lshr_b32 s34, s2, 16
|
|
; GFX11-NEXT: s_lshr_b32 s36, s2, 8
|
|
; GFX11-NEXT: s_lshr_b32 s37, s1, 24
|
|
; GFX11-NEXT: s_lshr_b32 s38, s1, 16
|
|
; GFX11-NEXT: s_lshr_b32 s48, s1, 8
|
|
; GFX11-NEXT: s_lshr_b32 s39, s0, 16
|
|
; GFX11-NEXT: s_lshr_b32 s49, s0, 8
|
|
; GFX11-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[28:29], s[24:25], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[12:13], s[20:21], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[10:11], s[18:19], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[8:9], s[16:17], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[6:7], s[2:3], 24
|
|
; GFX11-NEXT: s_lshr_b64 s[4:5], s[0:1], 24
|
|
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
|
|
; GFX11-NEXT: s_cbranch_vccnz .LBB105_4
|
|
; GFX11-NEXT: .LBB105_2: ; %cmp.true
|
|
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s25 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s24 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s23 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s22 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s21 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s20 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s19 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s18 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s17 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s16 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s3 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s2 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[3:4]
|
|
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s1 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s0 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s27 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s26 op_sel_hi:[0,1]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
|
|
; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[17:18]
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v4
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v6
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v5
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v5
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v8
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v7
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v49, 8, v7
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v55, 24, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v9
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v64, 8, v9
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v69, 24, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v12
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v67, 8, v11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v14
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v13
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v13
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v87, 24, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v18
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v17
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v17
|
|
; GFX11-NEXT: s_branch .LBB105_5
|
|
; GFX11-NEXT: .LBB105_3:
|
|
; GFX11-NEXT: ; implicit-def: $sgpr49
|
|
; GFX11-NEXT: ; implicit-def: $sgpr39
|
|
; GFX11-NEXT: ; implicit-def: $sgpr4
|
|
; GFX11-NEXT: ; implicit-def: $sgpr48
|
|
; GFX11-NEXT: ; implicit-def: $sgpr38
|
|
; GFX11-NEXT: ; implicit-def: $sgpr37
|
|
; GFX11-NEXT: ; implicit-def: $sgpr36
|
|
; GFX11-NEXT: ; implicit-def: $sgpr34
|
|
; GFX11-NEXT: ; implicit-def: $sgpr6
|
|
; GFX11-NEXT: ; implicit-def: $sgpr35
|
|
; GFX11-NEXT: ; implicit-def: $sgpr31
|
|
; GFX11-NEXT: ; implicit-def: $sgpr30
|
|
; GFX11-NEXT: ; implicit-def: $vcc_hi
|
|
; GFX11-NEXT: ; implicit-def: $sgpr94
|
|
; GFX11-NEXT: ; implicit-def: $sgpr8
|
|
; GFX11-NEXT: ; implicit-def: $sgpr95
|
|
; GFX11-NEXT: ; implicit-def: $sgpr93
|
|
; GFX11-NEXT: ; implicit-def: $sgpr92
|
|
; GFX11-NEXT: ; implicit-def: $sgpr91
|
|
; GFX11-NEXT: ; implicit-def: $sgpr89
|
|
; GFX11-NEXT: ; implicit-def: $sgpr10
|
|
; GFX11-NEXT: ; implicit-def: $sgpr90
|
|
; GFX11-NEXT: ; implicit-def: $sgpr88
|
|
; GFX11-NEXT: ; implicit-def: $sgpr79
|
|
; GFX11-NEXT: ; implicit-def: $sgpr78
|
|
; GFX11-NEXT: ; implicit-def: $sgpr76
|
|
; GFX11-NEXT: ; implicit-def: $sgpr12
|
|
; GFX11-NEXT: ; implicit-def: $sgpr77
|
|
; GFX11-NEXT: ; implicit-def: $sgpr75
|
|
; GFX11-NEXT: ; implicit-def: $sgpr74
|
|
; GFX11-NEXT: ; implicit-def: $sgpr73
|
|
; GFX11-NEXT: ; implicit-def: $sgpr63
|
|
; GFX11-NEXT: ; implicit-def: $sgpr14
|
|
; GFX11-NEXT: ; implicit-def: $sgpr72
|
|
; GFX11-NEXT: ; implicit-def: $sgpr62
|
|
; GFX11-NEXT: ; implicit-def: $sgpr61
|
|
; GFX11-NEXT: ; implicit-def: $sgpr60
|
|
; GFX11-NEXT: ; implicit-def: $sgpr58
|
|
; GFX11-NEXT: ; implicit-def: $sgpr28
|
|
; GFX11-NEXT: ; implicit-def: $sgpr59
|
|
; GFX11-NEXT: ; implicit-def: $sgpr57
|
|
; GFX11-NEXT: ; implicit-def: $sgpr56
|
|
; GFX11-NEXT: ; implicit-def: $sgpr47
|
|
; GFX11-NEXT: ; implicit-def: $sgpr45
|
|
; GFX11-NEXT: ; implicit-def: $sgpr40
|
|
; GFX11-NEXT: ; implicit-def: $sgpr46
|
|
; GFX11-NEXT: ; implicit-def: $sgpr44
|
|
; GFX11-NEXT: ; implicit-def: $sgpr43
|
|
; GFX11-NEXT: s_branch .LBB105_2
|
|
; GFX11-NEXT: .LBB105_4:
|
|
; GFX11-NEXT: v_dual_mov_b32 v17, s0 :: v_dual_mov_b32 v18, s1
|
|
; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v14, s3
|
|
; GFX11-NEXT: v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v12, s17
|
|
; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
|
|
; GFX11-NEXT: v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v8, s21
|
|
; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, s23
|
|
; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v4, s25
|
|
; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
|
|
; GFX11-NEXT: v_dual_mov_b32 v85, s49 :: v_dual_mov_b32 v96, s39
|
|
; GFX11-NEXT: v_dual_mov_b32 v83, s48 :: v_dual_mov_b32 v86, s38
|
|
; GFX11-NEXT: v_dual_mov_b32 v87, s37 :: v_dual_mov_b32 v82, s36
|
|
; GFX11-NEXT: v_dual_mov_b32 v84, s34 :: v_dual_mov_b32 v71, s35
|
|
; GFX11-NEXT: v_dual_mov_b32 v80, s31 :: v_dual_mov_b32 v81, s30
|
|
; GFX11-NEXT: v_dual_mov_b32 v67, vcc_hi :: v_dual_mov_b32 v70, s94
|
|
; GFX11-NEXT: v_dual_mov_b32 v65, s95 :: v_dual_mov_b32 v68, s93
|
|
; GFX11-NEXT: v_dual_mov_b32 v69, s92 :: v_dual_mov_b32 v64, s91
|
|
; GFX11-NEXT: v_dual_mov_b32 v66, s89 :: v_dual_mov_b32 v53, s90
|
|
; GFX11-NEXT: v_dual_mov_b32 v54, s88 :: v_dual_mov_b32 v55, s79
|
|
; GFX11-NEXT: v_dual_mov_b32 v49, s78 :: v_dual_mov_b32 v52, s76
|
|
; GFX11-NEXT: v_dual_mov_b32 v39, s77 :: v_dual_mov_b32 v50, s75
|
|
; GFX11-NEXT: v_dual_mov_b32 v51, s74 :: v_dual_mov_b32 v38, s73
|
|
; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v37, s61
|
|
; GFX11-NEXT: v_dual_mov_b32 v34, s72 :: v_dual_mov_b32 v33, s60
|
|
; GFX11-NEXT: v_dual_mov_b32 v36, s62 :: v_dual_mov_b32 v35, s58
|
|
; GFX11-NEXT: v_dual_mov_b32 v29, s59 :: v_dual_mov_b32 v32, s56
|
|
; GFX11-NEXT: v_dual_mov_b32 v31, s57 :: v_dual_mov_b32 v26, s47
|
|
; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v27, s44
|
|
; GFX11-NEXT: v_dual_mov_b32 v16, s46 :: v_dual_mov_b32 v15, s40
|
|
; GFX11-NEXT: v_dual_mov_b32 v28, s43 :: v_dual_mov_b32 v19, s28
|
|
; GFX11-NEXT: v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v21, s12
|
|
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
|
|
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
|
|
; GFX11-NEXT: .LBB105_5: ; %end
|
|
; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
|
|
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
|
|
; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
|
|
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
|
|
; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
|
|
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
|
|
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
|
|
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
|
|
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
|
|
; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
|
|
; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
|
|
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
|
|
; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
|
|
; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
|
|
; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
|
|
; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
|
|
; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
|
|
; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
|
|
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
|
|
; GFX11-NEXT: s_clause 0x3
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:16
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:32
|
|
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
|
|
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
|
|
; GFX11-NEXT: v_readlane_b32 s49, v40, 7
|
|
; GFX11-NEXT: v_readlane_b32 s48, v40, 6
|
|
; GFX11-NEXT: v_readlane_b32 s39, v40, 5
|
|
; GFX11-NEXT: v_readlane_b32 s38, v40, 4
|
|
; GFX11-NEXT: v_readlane_b32 s37, v40, 3
|
|
; GFX11-NEXT: v_readlane_b32 s36, v40, 2
|
|
; GFX11-NEXT: v_readlane_b32 s35, v40, 1
|
|
; GFX11-NEXT: v_readlane_b32 s34, v40, 0
|
|
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
|
|
; GFX11-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
|
|
; GFX11-NEXT: s_mov_b32 exec_lo, s0
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x half> %a, splat (half 0xH0200)
|
|
%a2 = bitcast <32 x half> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x half> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v32f16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
|
|
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:80
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
|
|
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:112
|
|
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:104
|
|
; SI-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:92
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:84
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v13
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v5
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 8, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v56, 8, v29
|
|
; SI-NEXT: v_lshlrev_b32_e32 v44, 24, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v47, 8, v25
|
|
; SI-NEXT: ; kill: killed $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; kill: killed $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 24, v6
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 8, v12
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v63, 24, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v42, 24, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v57, 24, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 8, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 24, v28
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v27, 24, v31
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v31, 8, v32
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v33
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v35
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v36
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:108
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:100
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB106_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v26
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v52
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v16, v16, v13
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v1, v6, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v16
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v39, v46, v9
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v29, v5, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_or_b32_e32 v23, v0, v29
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v29
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v39
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_or_b32_e32 v14, v5, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v36, v5, v0
|
|
; SI-NEXT: v_alignbit_b32 v0, v23, v14, 16
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v0, v36
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v17, v5, v0
|
|
; SI-NEXT: v_alignbit_b32 v0, v3, v17, 16
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v55
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v37, v7, v5
|
|
; SI-NEXT: v_or_b32_e32 v5, v0, v37
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v37
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v19, v54, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v38, v42, v7
|
|
; SI-NEXT: v_alignbit_b32 v53, v5, v19, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v56
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v7, v0, v38
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v38
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v25, v44, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v45, v7, v25, 16
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v60
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v9, v0, v39
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v20
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v20, v57, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v62
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v12, v59, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v0, v12
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v26, v63, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v40
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v18
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v13, v0, v16
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v41
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v30
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v34
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v8
|
|
; SI-NEXT: v_or_b32_e32 v15, v0, v4
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v8, v27, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v32, v9, v20, 16
|
|
; SI-NEXT: v_alignbit_b32 v22, v11, v26, 16
|
|
; SI-NEXT: v_alignbit_b32 v21, v13, v2, 16
|
|
; SI-NEXT: v_alignbit_b32 v33, v15, v8, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v4
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v18
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v14
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v18
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v17
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v18
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v61, v17, v19
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_or_b32_e32 v19, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v58
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v51
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v47
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v43, v17, v25
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v31
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v48, v17, v20
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: v_or_b32_e32 v10, v17, v10
|
|
; SI-NEXT: v_or_b32_e32 v17, v1, v8
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_or_b32_e32 v25, v10, v26
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: .LBB106_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB106_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v58
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v24
|
|
; SI-NEXT: v_or_b32_e32 v0, v51, v0
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x300, v0
|
|
; SI-NEXT: v_or_b32_e32 v3, v27, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v8
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_or_b32_e32 v3, v34, v3
|
|
; SI-NEXT: s_movk_i32 s6, 0x300
|
|
; SI-NEXT: s_mov_b32 s7, 0x3000000
|
|
; SI-NEXT: v_add_i32_e32 v17, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v3
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v30
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v3, v4, v3
|
|
; SI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v6
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v41
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v19, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v40
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v52
|
|
; SI-NEXT: v_or_b32_e32 v0, v18, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v16, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v28
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v63, v1
|
|
; SI-NEXT: v_alignbit_b32 v21, v13, v19, 16
|
|
; SI-NEXT: v_alignbit_b32 v33, v15, v17, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v50, 16, v15
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v10, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v25, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v12
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v26
|
|
; SI-NEXT: v_or_b32_e32 v0, v62, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v59, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v57, v1
|
|
; SI-NEXT: v_alignbit_b32 v22, v11, v25, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 16, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v31, v0
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v48, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v60, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v46, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v32, v9, v48, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v29, 16, v9
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v47, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v44, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v43, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v56, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v42, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v45, v7, v43, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 16, v7
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v54, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v61, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v55, v0
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_alignbit_b32 v53, v5, v61, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v0
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v36, 16, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v1, v0
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v4, v2
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: v_add_i32_e32 v23, vcc, s7, v1
|
|
; SI-NEXT: v_alignbit_b32 v1, v23, v0, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v3, v14, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 16, v23
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
|
|
; SI-NEXT: .LBB106_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v35
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v53
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v32
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v33
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff, v23
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v61
|
|
; SI-NEXT: v_or_b32_e32 v4, v4, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v37
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v43
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_or_b32_e32 v6, v6, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
|
|
; SI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v48
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v29
|
|
; SI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v25
|
|
; SI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v39
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v21
|
|
; SI-NEXT: v_or_b32_e32 v12, v12, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v49
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v50
|
|
; SI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v32f16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; VI-NEXT: buffer_load_ushort v55, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:128
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:124
|
|
; VI-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:120
|
|
; VI-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:116
|
|
; VI-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:112
|
|
; VI-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:108
|
|
; VI-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:104
|
|
; VI-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:100
|
|
; VI-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:96
|
|
; VI-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:92
|
|
; VI-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:88
|
|
; VI-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:84
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:80
|
|
; VI-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: v_mov_b32_e32 v17, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB106_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; kill: killed $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v0, v1, v0, s6
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
|
|
; VI-NEXT: v_perm_b32 v16, v32, v54, s6
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; VI-NEXT: v_perm_b32 v15, v53, v52, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: .LBB106_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB106_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v32
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v54
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v53
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v52
|
|
; VI-NEXT: v_or_b32_sdwa v15, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v51
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v50
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v39
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v38
|
|
; VI-NEXT: v_or_b32_sdwa v14, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(12)
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v49
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v48
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_mov_b32_e32 v3, 0x300
|
|
; VI-NEXT: v_add_u16_sdwa v32, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v38, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(10)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v37
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v36
|
|
; VI-NEXT: v_or_b32_sdwa v36, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(8)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v35
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v34
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v12, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(6)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v31
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v63
|
|
; VI-NEXT: v_or_b32_sdwa v31, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v33
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v62
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v11, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v59
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v56
|
|
; VI-NEXT: v_or_b32_sdwa v33, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v58
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v47
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v10, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v61
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v60
|
|
; VI-NEXT: v_or_b32_sdwa v34, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v57
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v46
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v9, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v45
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v43
|
|
; VI-NEXT: v_or_b32_sdwa v35, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v44
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v42
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v8, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v41
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v40
|
|
; VI-NEXT: v_or_b32_sdwa v37, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v30
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v55
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v7, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v28
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v29
|
|
; VI-NEXT: v_or_b32_sdwa v28, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v26
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v27
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v6, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v24
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v25
|
|
; VI-NEXT: v_or_b32_sdwa v24, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v22
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v23
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v5, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v20
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v21
|
|
; VI-NEXT: v_or_b32_sdwa v20, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v18
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v19
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_sdwa v4, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v16
|
|
; VI-NEXT: v_add_u16_sdwa v13, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; VI-NEXT: v_add_u16_e32 v15, 0x300, v15
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v38
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v32
|
|
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v16, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v17
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v16
|
|
; VI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v20
|
|
; VI-NEXT: v_or_b32_e32 v5, v16, v5
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v24
|
|
; VI-NEXT: v_or_b32_e32 v6, v16, v6
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v28
|
|
; VI-NEXT: v_or_b32_e32 v7, v16, v7
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v37
|
|
; VI-NEXT: v_or_b32_e32 v8, v16, v8
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v35
|
|
; VI-NEXT: v_or_b32_e32 v9, v16, v9
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v34
|
|
; VI-NEXT: v_or_b32_e32 v10, v16, v10
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v33
|
|
; VI-NEXT: v_or_b32_e32 v11, v16, v11
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v31
|
|
; VI-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v36
|
|
; VI-NEXT: v_or_b32_e32 v13, v16, v13
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v21, 8, v21
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v17, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v18, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v2, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v19, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v1, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: v_or_b32_sdwa v21, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: v_or_b32_sdwa v0, v22, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v3
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; VI-NEXT: v_or_b32_sdwa v3, v22, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v21
|
|
; VI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v19
|
|
; VI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v18
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: .LBB106_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v32f16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:124
|
|
; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:120
|
|
; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:116
|
|
; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, v12
|
|
; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
|
|
; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
|
|
; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
|
|
; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
|
|
; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:108
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:100
|
|
; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:92
|
|
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
|
|
; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: s_waitcnt vmcnt(23)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(22)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v56, 8, v1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(21)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v45, 8, v2
|
|
; GFX9-NEXT: s_waitcnt vmcnt(20)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v61, 8, v3
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(18)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v33, 8, v5
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(15)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v8
|
|
; GFX9-NEXT: s_waitcnt vmcnt(14)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v9
|
|
; GFX9-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v10
|
|
; GFX9-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
|
|
; GFX9-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v32, 8, v12
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB106_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
|
|
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v26, v27, s6
|
|
; GFX9-NEXT: v_perm_b32 v8, v30, v36, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v47, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v55, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v12, v42, v41, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v43, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v14, v58, v57, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v34, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: ; implicit-def: $vgpr22
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v2, s7
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s7
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v3, v19, v3, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v16, v52, v54, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v5, v18, v5, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s7
|
|
; GFX9-NEXT: v_perm_b32 v6, v24, v25, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
|
|
; GFX9-NEXT: v_perm_b32 v7, v28, v29, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v59, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v60, v61 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v48, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v40, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v44, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v46, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v31, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v53, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; kill: killed $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: .LBB106_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB106_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v52
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v54
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 3, v53
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(9)
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v31
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v57
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v50, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v51, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v43
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v35, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v55
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v33, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v63
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v62
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v60
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v61, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v38, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v59
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v56, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v47
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v29
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v36
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v25
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v27
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v23
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
|
|
; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v3
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v2
|
|
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
|
|
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s6
|
|
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v33, v10, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v37, v11, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s6
|
|
; GFX9-NEXT: v_perm_b32 v14, v32, v14, s6
|
|
; GFX9-NEXT: v_perm_b32 v15, v31, v15, s6
|
|
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v19
|
|
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v4, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v3, v17, v3, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v18, v2, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v19, v1, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v21
|
|
; GFX9-NEXT: v_perm_b32 v0, v21, v0, s6
|
|
; GFX9-NEXT: .LBB106_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32f16:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1f
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB106_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB106_4
|
|
; GFX11-TRUE16-NEXT: .LBB106_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB106_3: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB106_2
|
|
; GFX11-TRUE16-NEXT: .LBB106_4: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.h, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v16.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v16.h
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32f16:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v33, v12
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v37, v11
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v49, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v9 :: v_dual_mov_b32 v34, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v32, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v36, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v5 :: v_dual_mov_b32 v38, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v4 :: v_dual_mov_b32 v50, v1
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1f
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:128
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:124
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:120
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:116
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:112
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:108
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:104
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:100
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:96
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:92
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:88
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:84
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:80
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:76
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:72
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:68
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v6, off, s32 offset:132
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:64
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v119, 8, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v117, 8, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v118, 8, v2
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v115, 8, v3
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v114, 8, v4
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v116, 8, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v84, 8, v7
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(15)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v65, 8, v8
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(14)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v80, 8, v9
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v112, 8, v10
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v113, 8, v11
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v103, 8, v12
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB106_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB106_4
|
|
; GFX11-FAKE16-NEXT: .LBB106_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB106_3: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v39, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v37, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v33, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v54, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v16, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v22, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v28, v29, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v30, v55, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v83
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v7, v6, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v66
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v84
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v101
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v96
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v70
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v65
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v69, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v112
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v113
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v80
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v98
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v82
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v12, v11, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v85
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v86
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v100
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v114
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v102
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v103
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v116
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v115
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v81, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v11, v118
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v117
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v18, v119
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v99, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v14, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v16, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v19, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v20, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v18, v21, 0x5040100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB106_2
|
|
; GFX11-FAKE16-NEXT: .LBB106_4: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v99, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v100, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v87
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v102, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v81, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v119, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v118, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v81, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v64
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v85, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v117, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v68, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v115, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v64, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v116, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v97, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v98, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v114, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v71
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v101, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v71, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v103, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v69, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v69, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v112, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v113, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v67
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v66, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v28, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v80, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v84, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v29
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v30, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v65, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v55
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v26, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v25
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v27
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v20, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v22, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v6, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v33, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v31, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v52
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v54, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v53
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v48
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v18, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v49, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v19, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v51, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v34, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v38, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v36, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v39
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v50
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v32
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v35
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v37
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v23, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v26, v21
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v27, v22
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v29, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v30, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v22, v21, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v3, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v16, v2, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v23, v19, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v26, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v17, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v25, v7, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v8, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v9, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v67, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v69, v11, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v12, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v68, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v64, v14, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v81, v15, 0x5040100
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v32f16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_writelane_b32 v40, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v40, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v40, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v40, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v40, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v40, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v40, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v40, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v40, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v40, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v40, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v40, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v40, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v40, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v40, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v40, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v40, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v40, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v40, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v40, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v40, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v40, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v40, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v40, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v40, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v40, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v40, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v40, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v40, s86, 28
|
|
; SI-NEXT: v_writelane_b32 v40, s87, 29
|
|
; SI-NEXT: v_writelane_b32 v40, s96, 30
|
|
; SI-NEXT: v_writelane_b32 v40, s97, 31
|
|
; SI-NEXT: v_writelane_b32 v40, s98, 32
|
|
; SI-NEXT: v_writelane_b32 v40, s99, 33
|
|
; SI-NEXT: v_writelane_b32 v40, s30, 34
|
|
; SI-NEXT: v_writelane_b32 v40, s31, 35
|
|
; SI-NEXT: v_readfirstlane_b32 s79, v28
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: s_mov_b32 s31, s16
|
|
; SI-NEXT: v_readfirstlane_b32 s89, v30
|
|
; SI-NEXT: v_readfirstlane_b32 s36, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s94, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s55, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s30, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s16, v24
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
|
|
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
|
|
; SI-NEXT: v_readfirstlane_b32 s95, v23
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v41, s29, 0
|
|
; SI-NEXT: v_writelane_b32 v41, s28, 1
|
|
; SI-NEXT: v_writelane_b32 v41, s23, 2
|
|
; SI-NEXT: v_writelane_b32 v41, s22, 3
|
|
; SI-NEXT: v_writelane_b32 v41, s21, 4
|
|
; SI-NEXT: v_writelane_b32 v41, s20, 5
|
|
; SI-NEXT: v_readfirstlane_b32 s64, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s66, v21
|
|
; SI-NEXT: v_readfirstlane_b32 s81, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s82, v19
|
|
; SI-NEXT: v_readfirstlane_b32 s68, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s39, v17
|
|
; SI-NEXT: v_readfirstlane_b32 s52, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s65, v15
|
|
; SI-NEXT: v_readfirstlane_b32 s48, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s50, v13
|
|
; SI-NEXT: v_readfirstlane_b32 s70, v12
|
|
; SI-NEXT: v_readfirstlane_b32 s71, v11
|
|
; SI-NEXT: v_readfirstlane_b32 s37, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s29, v9
|
|
; SI-NEXT: v_readfirstlane_b32 s93, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s28, v7
|
|
; SI-NEXT: v_readfirstlane_b32 s38, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s49, v5
|
|
; SI-NEXT: v_readfirstlane_b32 s51, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s53, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s67, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s90, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s91, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_readfirstlane_b32 s47, v24
|
|
; SI-NEXT: v_readfirstlane_b32 s86, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s99, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v29
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_readfirstlane_b32 s78, v30
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_readfirstlane_b32 s88, v31
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_readfirstlane_b32 s21, v32
|
|
; SI-NEXT: s_waitcnt vmcnt(10)
|
|
; SI-NEXT: v_readfirstlane_b32 s98, v33
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_readfirstlane_b32 s96, v34
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
|
|
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_readfirstlane_b32 s34, v35
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_readfirstlane_b32 s83, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_readfirstlane_b32 s20, v37
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_readfirstlane_b32 s84, v38
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v39
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_readfirstlane_b32 s87, v48
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_readfirstlane_b32 s85, v49
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_readfirstlane_b32 s69, v50
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s35, v51
|
|
; SI-NEXT: v_writelane_b32 v41, s47, 6
|
|
; SI-NEXT: v_writelane_b32 v41, s58, 7
|
|
; SI-NEXT: s_cbranch_scc0 .LBB107_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s31, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 8
|
|
; SI-NEXT: s_or_b32 s12, s4, s5
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xff
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 16
|
|
; SI-NEXT: s_lshl_b32 s5, s19, 24
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s25, 8
|
|
; SI-NEXT: s_or_b32 s13, s5, s6
|
|
; SI-NEXT: s_and_b32 s5, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s27, 24
|
|
; SI-NEXT: s_or_b32 s6, s6, s5
|
|
; SI-NEXT: s_and_b32 s5, s67, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s53, 8
|
|
; SI-NEXT: s_or_b32 s14, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s51, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s49, 24
|
|
; SI-NEXT: s_or_b32 s8, s7, s5
|
|
; SI-NEXT: s_and_b32 s5, s37, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s71, 8
|
|
; SI-NEXT: s_or_b32 s15, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s70, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s50, 24
|
|
; SI-NEXT: s_or_b32 s10, s7, s5
|
|
; SI-NEXT: s_and_b32 s5, s68, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s82, 8
|
|
; SI-NEXT: s_or_b32 s40, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s81, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s66, 24
|
|
; SI-NEXT: s_or_b32 s60, s7, s5
|
|
; SI-NEXT: s_and_b32 s5, s55, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s94, 8
|
|
; SI-NEXT: s_or_b32 s41, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s79, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s36, 24
|
|
; SI-NEXT: s_or_b32 s62, s7, s5
|
|
; SI-NEXT: s_and_b32 s5, s87, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s44, 8
|
|
; SI-NEXT: s_or_b32 s42, s5, s7
|
|
; SI-NEXT: s_and_b32 s5, s21, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s88, 8
|
|
; SI-NEXT: s_or_b32 s43, s5, s7
|
|
; SI-NEXT: v_readlane_b32 s5, v41, 5
|
|
; SI-NEXT: v_readlane_b32 s7, v41, 4
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 8
|
|
; SI-NEXT: s_or_b32 s5, s5, s7
|
|
; SI-NEXT: v_readlane_b32 s7, v41, 3
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xff
|
|
; SI-NEXT: v_readlane_b32 s9, v41, 2
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 24
|
|
; SI-NEXT: s_or_b32 s57, s9, s7
|
|
; SI-NEXT: v_readlane_b32 s7, v41, 1
|
|
; SI-NEXT: v_readlane_b32 s9, v41, 0
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s91, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_lshl_b32 s11, s90, 24
|
|
; SI-NEXT: s_or_b32 s77, s11, s9
|
|
; SI-NEXT: s_and_b32 s9, s38, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s28, 8
|
|
; SI-NEXT: s_or_b32 s9, s9, s11
|
|
; SI-NEXT: s_and_b32 s11, s93, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 16
|
|
; SI-NEXT: v_writelane_b32 v41, s44, 12
|
|
; SI-NEXT: s_lshl_b32 s44, s29, 24
|
|
; SI-NEXT: s_or_b32 vcc_lo, s44, s11
|
|
; SI-NEXT: s_and_b32 s11, s48, 0xff
|
|
; SI-NEXT: s_lshl_b32 s44, s65, 8
|
|
; SI-NEXT: s_or_b32 s11, s11, s44
|
|
; SI-NEXT: s_and_b32 s44, s52, 0xff
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: s_lshl_b32 s45, s39, 24
|
|
; SI-NEXT: s_or_b32 vcc_hi, s45, s44
|
|
; SI-NEXT: s_and_b32 s44, s64, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s95, 8
|
|
; SI-NEXT: s_or_b32 s44, s44, s45
|
|
; SI-NEXT: s_and_b32 s45, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_mov_b32 s59, s46
|
|
; SI-NEXT: s_lshl_b32 s46, s30, 24
|
|
; SI-NEXT: v_writelane_b32 v41, s55, 13
|
|
; SI-NEXT: s_and_b32 s44, s44, 0xffff
|
|
; SI-NEXT: v_writelane_b32 v41, s79, 14
|
|
; SI-NEXT: s_or_b32 s79, s46, s45
|
|
; SI-NEXT: s_or_b32 s61, s44, s79
|
|
; SI-NEXT: s_and_b32 s44, s89, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s35, 8
|
|
; SI-NEXT: s_or_b32 s44, s44, s45
|
|
; SI-NEXT: s_and_b32 s45, s69, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s85, 24
|
|
; SI-NEXT: s_and_b32 s44, s44, 0xffff
|
|
; SI-NEXT: s_mov_b32 s23, s21
|
|
; SI-NEXT: s_mov_b32 s21, s87
|
|
; SI-NEXT: s_mov_b32 s87, s18
|
|
; SI-NEXT: s_or_b32 s18, s46, s45
|
|
; SI-NEXT: s_or_b32 s63, s44, s18
|
|
; SI-NEXT: s_and_b32 s44, s83, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s34, 8
|
|
; SI-NEXT: s_or_b32 s44, s44, s45
|
|
; SI-NEXT: s_and_b32 s45, s96, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s98, 24
|
|
; SI-NEXT: s_mov_b32 s56, s83
|
|
; SI-NEXT: s_mov_b32 s83, s64
|
|
; SI-NEXT: s_mov_b32 s64, s39
|
|
; SI-NEXT: s_mov_b32 s39, s91
|
|
; SI-NEXT: s_mov_b32 s91, s19
|
|
; SI-NEXT: s_or_b32 s19, s46, s45
|
|
; SI-NEXT: s_and_b32 s45, s84, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s20, 24
|
|
; SI-NEXT: s_and_b32 s44, s44, 0xffff
|
|
; SI-NEXT: s_or_b32 s72, s46, s45
|
|
; SI-NEXT: s_or_b32 s73, s44, s19
|
|
; SI-NEXT: s_and_b32 s44, s99, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s58, 8
|
|
; SI-NEXT: s_or_b32 s44, s44, s45
|
|
; SI-NEXT: s_and_b32 s45, s86, 0xff
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s47, 24
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_mov_b32 s76, s20
|
|
; SI-NEXT: s_mov_b32 s20, s84
|
|
; SI-NEXT: s_mov_b32 s84, s81
|
|
; SI-NEXT: s_mov_b32 s81, s70
|
|
; SI-NEXT: s_mov_b32 s70, s65
|
|
; SI-NEXT: s_mov_b32 s65, s49
|
|
; SI-NEXT: s_mov_b32 s49, s90
|
|
; SI-NEXT: s_mov_b32 s90, s17
|
|
; SI-NEXT: s_or_b32 s17, s46, s45
|
|
; SI-NEXT: s_and_b32 s45, s78, 0xff
|
|
; SI-NEXT: s_or_b32 s5, s5, s57
|
|
; SI-NEXT: s_lshl_b32 s45, s45, 16
|
|
; SI-NEXT: s_lshl_b32 s46, s59, 24
|
|
; SI-NEXT: s_and_b32 s44, s44, 0xffff
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s74, s46, s45
|
|
; SI-NEXT: s_or_b32 s75, s44, s17
|
|
; SI-NEXT: s_mov_b32 s46, s28
|
|
; SI-NEXT: s_and_b32 s28, s42, 0xffff
|
|
; SI-NEXT: s_mov_b32 s44, s30
|
|
; SI-NEXT: s_mov_b32 s30, s26
|
|
; SI-NEXT: s_and_b32 s26, s43, 0xffff
|
|
; SI-NEXT: s_or_b32 s42, s12, s4
|
|
; SI-NEXT: s_mov_b32 s43, s5
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s77
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 8
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 9
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[6:7], 16
|
|
; SI-NEXT: s_or_b32 s9, s9, vcc_lo
|
|
; SI-NEXT: s_or_b32 s11, s11, vcc_hi
|
|
; SI-NEXT: s_mov_b32 s92, s16
|
|
; SI-NEXT: s_mov_b32 s97, s48
|
|
; SI-NEXT: s_mov_b32 s48, s29
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: s_and_b32 s58, s15, 0xffff
|
|
; SI-NEXT: s_and_b32 s16, s40, 0xffff
|
|
; SI-NEXT: s_and_b32 s29, s41, 0xffff
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 10
|
|
; SI-NEXT: s_mov_b32 s22, s51
|
|
; SI-NEXT: s_mov_b32 s51, s93
|
|
; SI-NEXT: s_mov_b32 s45, s99
|
|
; SI-NEXT: s_mov_b32 s99, s96
|
|
; SI-NEXT: s_mov_b32 s96, s82
|
|
; SI-NEXT: s_mov_b32 s82, s95
|
|
; SI-NEXT: s_mov_b32 s95, s94
|
|
; SI-NEXT: s_mov_b32 s94, s92
|
|
; SI-NEXT: s_or_b32 s40, s13, s6
|
|
; SI-NEXT: s_mov_b32 s41, s7
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 11
|
|
; SI-NEXT: s_or_b32 s14, s14, s8
|
|
; SI-NEXT: s_mov_b32 s15, s9
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[8:9], 16
|
|
; SI-NEXT: s_or_b32 s12, s58, s10
|
|
; SI-NEXT: s_mov_b32 s13, s11
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[10:11], 16
|
|
; SI-NEXT: s_or_b32 s10, s16, s60
|
|
; SI-NEXT: s_mov_b32 s11, s61
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[60:61], 16
|
|
; SI-NEXT: s_or_b32 s8, s29, s62
|
|
; SI-NEXT: s_mov_b32 s9, s63
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[62:63], 16
|
|
; SI-NEXT: s_or_b32 s6, s28, s72
|
|
; SI-NEXT: s_mov_b32 s7, s73
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[72:73], 16
|
|
; SI-NEXT: s_or_b32 s4, s26, s74
|
|
; SI-NEXT: s_mov_b32 s5, s75
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[74:75], 16
|
|
; SI-NEXT: s_mov_b32 s16, s94
|
|
; SI-NEXT: s_mov_b32 s94, s95
|
|
; SI-NEXT: s_mov_b32 s95, s82
|
|
; SI-NEXT: s_mov_b32 s82, s96
|
|
; SI-NEXT: s_mov_b32 s96, s99
|
|
; SI-NEXT: s_mov_b32 s99, s45
|
|
; SI-NEXT: s_mov_b32 s28, s46
|
|
; SI-NEXT: s_mov_b32 s46, s59
|
|
; SI-NEXT: s_mov_b32 s26, s30
|
|
; SI-NEXT: s_mov_b32 s30, s44
|
|
; SI-NEXT: v_readlane_b32 s44, v41, 12
|
|
; SI-NEXT: s_lshr_b32 s47, s57, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s77, 16
|
|
; SI-NEXT: s_lshr_b32 s59, vcc_lo, 16
|
|
; SI-NEXT: s_lshr_b32 s61, vcc_hi, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s79, 16
|
|
; SI-NEXT: v_readlane_b32 s79, v41, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v41, 13
|
|
; SI-NEXT: s_lshr_b32 s73, s18, 16
|
|
; SI-NEXT: s_mov_b32 s18, s87
|
|
; SI-NEXT: s_mov_b32 s29, s48
|
|
; SI-NEXT: s_mov_b32 s48, s97
|
|
; SI-NEXT: s_mov_b32 s87, s21
|
|
; SI-NEXT: s_mov_b32 s21, s23
|
|
; SI-NEXT: s_mov_b32 s93, s51
|
|
; SI-NEXT: s_mov_b32 s51, s22
|
|
; SI-NEXT: s_lshr_b32 s75, s19, 16
|
|
; SI-NEXT: s_mov_b32 s19, s91
|
|
; SI-NEXT: s_mov_b32 s91, s39
|
|
; SI-NEXT: s_mov_b32 s39, s64
|
|
; SI-NEXT: s_mov_b32 s64, s83
|
|
; SI-NEXT: s_mov_b32 s83, s56
|
|
; SI-NEXT: s_lshr_b32 s45, s17, 16
|
|
; SI-NEXT: s_mov_b32 s17, s90
|
|
; SI-NEXT: s_mov_b32 s90, s49
|
|
; SI-NEXT: s_mov_b32 s49, s65
|
|
; SI-NEXT: s_mov_b32 s65, s70
|
|
; SI-NEXT: s_mov_b32 s70, s81
|
|
; SI-NEXT: s_mov_b32 s81, s84
|
|
; SI-NEXT: s_mov_b32 s84, s20
|
|
; SI-NEXT: s_mov_b32 s20, s76
|
|
; SI-NEXT: s_mov_b64 s[76:77], 0
|
|
; SI-NEXT: s_branch .LBB107_3
|
|
; SI-NEXT: .LBB107_2:
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: s_mov_b64 s[76:77], -1
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 8
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 9
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr47
|
|
; SI-NEXT: ; implicit-def: $sgpr40
|
|
; SI-NEXT: ; implicit-def: $sgpr57
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr61
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr63
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr72
|
|
; SI-NEXT: ; implicit-def: $sgpr75
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 10
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 11
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: .LBB107_3: ; %Flow
|
|
; SI-NEXT: s_andn2_b64 vcc, exec, s[76:77]
|
|
; SI-NEXT: v_readlane_b32 s76, v41, 8
|
|
; SI-NEXT: v_readlane_b32 s77, v41, 9
|
|
; SI-NEXT: s_mov_b32 s22, s76
|
|
; SI-NEXT: v_readlane_b32 s76, v41, 10
|
|
; SI-NEXT: s_mov_b32 s56, s76
|
|
; SI-NEXT: v_readlane_b32 s77, v41, 11
|
|
; SI-NEXT: s_cbranch_vccnz .LBB107_5
|
|
; SI-NEXT: ; %bb.4: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s21, s21, 3
|
|
; SI-NEXT: s_and_b32 s4, s21, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s88, 8
|
|
; SI-NEXT: s_add_i32 s78, s78, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s6, s78, 0xff
|
|
; SI-NEXT: s_addk_i32 s4, 0x300
|
|
; SI-NEXT: s_lshl_b32 s5, s46, 24
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s5, s6
|
|
; SI-NEXT: s_add_i32 s99, s99, 3
|
|
; SI-NEXT: v_readlane_b32 s6, v41, 7
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s99, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 8
|
|
; SI-NEXT: s_add_i32 s86, s86, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: v_readlane_b32 s6, v41, 6
|
|
; SI-NEXT: s_and_b32 s7, s86, 0xff
|
|
; SI-NEXT: s_addk_i32 s5, 0x300
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 24
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: s_add_i32 s97, s87, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: s_and_b32 s6, s97, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s44, 8
|
|
; SI-NEXT: s_add_i32 s84, s84, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s8, s84, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s20, 24
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s8
|
|
; SI-NEXT: s_add_i32 s83, s83, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s7, s83, 0xff
|
|
; SI-NEXT: s_lshl_b32 s8, s34, 8
|
|
; SI-NEXT: s_add_i32 s80, s96, 3
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: s_and_b32 s9, s80, 0xff
|
|
; SI-NEXT: s_addk_i32 s7, 0x300
|
|
; SI-NEXT: s_lshl_b32 s8, s98, 24
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s8, s8, s9
|
|
; SI-NEXT: s_add_i32 s55, s55, 3
|
|
; SI-NEXT: s_or_b32 s7, s8, s7
|
|
; SI-NEXT: s_and_b32 s8, s55, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s94, 8
|
|
; SI-NEXT: s_add_i32 s88, s79, 3
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_and_b32 s10, s88, 0xff
|
|
; SI-NEXT: s_addk_i32 s8, 0x300
|
|
; SI-NEXT: s_lshl_b32 s9, s36, 24
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s9, s10
|
|
; SI-NEXT: s_add_i32 s20, s89, 3
|
|
; SI-NEXT: s_or_b32 s8, s9, s8
|
|
; SI-NEXT: s_and_b32 s9, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s10, s35, 8
|
|
; SI-NEXT: s_add_i32 s69, s69, 3
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: s_and_b32 s11, s69, 0xff
|
|
; SI-NEXT: s_addk_i32 s9, 0x300
|
|
; SI-NEXT: s_lshl_b32 s10, s85, 24
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 16
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_or_b32 s10, s10, s11
|
|
; SI-NEXT: s_add_i32 s68, s68, 3
|
|
; SI-NEXT: s_or_b32 s9, s10, s9
|
|
; SI-NEXT: s_and_b32 s10, s68, 0xff
|
|
; SI-NEXT: s_lshl_b32 s11, s82, 8
|
|
; SI-NEXT: s_or_b32 s10, s11, s10
|
|
; SI-NEXT: s_lshl_b32 s11, s66, 24
|
|
; SI-NEXT: s_add_i32 s66, s81, 3
|
|
; SI-NEXT: s_and_b32 s12, s66, 0xff
|
|
; SI-NEXT: s_addk_i32 s10, 0x300
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xffff
|
|
; SI-NEXT: s_or_b32 s11, s11, s12
|
|
; SI-NEXT: s_add_i32 s64, s64, 3
|
|
; SI-NEXT: s_or_b32 s10, s11, s10
|
|
; SI-NEXT: s_and_b32 s11, s64, 0xff
|
|
; SI-NEXT: s_lshl_b32 s12, s95, 8
|
|
; SI-NEXT: s_add_i32 s94, s16, 3
|
|
; SI-NEXT: s_or_b32 s11, s12, s11
|
|
; SI-NEXT: s_and_b32 s13, s94, 0xff
|
|
; SI-NEXT: s_addk_i32 s11, 0x300
|
|
; SI-NEXT: s_lshl_b32 s12, s30, 24
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; SI-NEXT: s_or_b32 s12, s12, s13
|
|
; SI-NEXT: s_add_i32 s54, s37, 3
|
|
; SI-NEXT: s_or_b32 s11, s12, s11
|
|
; SI-NEXT: s_and_b32 s12, s54, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s71, 8
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: s_lshl_b32 s13, s50, 24
|
|
; SI-NEXT: s_add_i32 s50, s70, 3
|
|
; SI-NEXT: s_and_b32 s14, s50, 0xff
|
|
; SI-NEXT: s_addk_i32 s12, 0x300
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_or_b32 s13, s13, s14
|
|
; SI-NEXT: s_add_i32 s48, s48, 3
|
|
; SI-NEXT: s_or_b32 s12, s13, s12
|
|
; SI-NEXT: s_and_b32 s13, s48, 0xff
|
|
; SI-NEXT: s_lshl_b32 s14, s65, 8
|
|
; SI-NEXT: s_add_i32 s36, s52, 3
|
|
; SI-NEXT: s_or_b32 s13, s14, s13
|
|
; SI-NEXT: s_and_b32 s15, s36, 0xff
|
|
; SI-NEXT: s_addk_i32 s13, 0x300
|
|
; SI-NEXT: s_lshl_b32 s14, s39, 24
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 16
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_or_b32 s14, s14, s15
|
|
; SI-NEXT: s_add_i32 s39, s67, 3
|
|
; SI-NEXT: s_or_b32 s13, s14, s13
|
|
; SI-NEXT: s_and_b32 s14, s39, 0xff
|
|
; SI-NEXT: s_lshl_b32 s15, s53, 8
|
|
; SI-NEXT: s_add_i32 s34, s51, 3
|
|
; SI-NEXT: s_or_b32 s14, s15, s14
|
|
; SI-NEXT: s_and_b32 s20, s34, 0xff
|
|
; SI-NEXT: s_addk_i32 s14, 0x300
|
|
; SI-NEXT: s_lshl_b32 s15, s49, 24
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: s_or_b32 s15, s15, s20
|
|
; SI-NEXT: s_add_i32 s30, s38, 3
|
|
; SI-NEXT: s_or_b32 s14, s15, s14
|
|
; SI-NEXT: s_and_b32 s15, s30, 0xff
|
|
; SI-NEXT: s_lshl_b32 s20, s28, 8
|
|
; SI-NEXT: s_add_i32 s92, s93, 3
|
|
; SI-NEXT: s_or_b32 s15, s20, s15
|
|
; SI-NEXT: s_and_b32 s21, s92, 0xff
|
|
; SI-NEXT: s_addk_i32 s15, 0x300
|
|
; SI-NEXT: s_lshl_b32 s20, s29, 24
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; SI-NEXT: s_or_b32 s20, s20, s21
|
|
; SI-NEXT: s_add_i32 s24, s24, 3
|
|
; SI-NEXT: s_or_b32 s15, s20, s15
|
|
; SI-NEXT: s_and_b32 s20, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s21, s25, 8
|
|
; SI-NEXT: s_add_i32 s26, s26, 3
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s24, s26, 0xff
|
|
; SI-NEXT: s_add_i32 s16, s31, 3
|
|
; SI-NEXT: s_addk_i32 s20, 0x300
|
|
; SI-NEXT: s_lshl_b32 s21, s27, 24
|
|
; SI-NEXT: s_lshl_b32 s24, s24, 16
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_and_b32 s20, s20, 0xffff
|
|
; SI-NEXT: s_or_b32 s21, s21, s24
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xff
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_addk_i32 s16, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s19, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_add_i32 s40, s20, 0x3000000
|
|
; SI-NEXT: v_readlane_b32 s20, v41, 1
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s28, s20, 3
|
|
; SI-NEXT: v_readlane_b32 s21, v41, 0
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_and_b32 s20, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 8
|
|
; SI-NEXT: s_add_i32 s42, s16, 0x3000000
|
|
; SI-NEXT: v_readlane_b32 s16, v41, 5
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_lshl_b32 s21, s90, 24
|
|
; SI-NEXT: s_add_i32 s90, s91, 3
|
|
; SI-NEXT: s_add_i32 s16, s16, 3
|
|
; SI-NEXT: v_readlane_b32 s17, v41, 4
|
|
; SI-NEXT: v_readlane_b32 s18, v41, 3
|
|
; SI-NEXT: s_and_b32 s24, s90, 0xff
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_addk_i32 s20, 0x300
|
|
; SI-NEXT: s_lshl_b32 s24, s24, 16
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: v_readlane_b32 s17, v41, 2
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xff
|
|
; SI-NEXT: s_and_b32 s20, s20, 0xffff
|
|
; SI-NEXT: s_or_b32 s21, s21, s24
|
|
; SI-NEXT: s_addk_i32 s16, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_or_b32 s20, s21, s20
|
|
; SI-NEXT: s_and_b32 s16, s16, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
|
|
; SI-NEXT: s_add_i32 s6, s6, 0x3000000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
|
|
; SI-NEXT: s_add_i32 s8, s8, 0x3000000
|
|
; SI-NEXT: s_add_i32 s9, s9, 0x3000000
|
|
; SI-NEXT: s_add_i32 s10, s10, 0x3000000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
|
|
; SI-NEXT: s_add_i32 s41, s20, 0x3000000
|
|
; SI-NEXT: s_or_b32 s16, s17, s16
|
|
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
|
|
; SI-NEXT: s_add_i32 s13, s13, 0x3000000
|
|
; SI-NEXT: s_add_i32 s14, s14, 0x3000000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
|
|
; SI-NEXT: s_add_i32 s43, s16, 0x3000000
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[8:9], 16
|
|
; SI-NEXT: s_lshr_b64 s[72:73], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16
|
|
; SI-NEXT: s_lshr_b64 s[22:23], s[42:43], 16
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[14:15], 16
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b32 s47, s43, 16
|
|
; SI-NEXT: s_lshr_b32 s57, s41, 16
|
|
; SI-NEXT: s_lshr_b32 s59, s15, 16
|
|
; SI-NEXT: s_lshr_b32 s61, s13, 16
|
|
; SI-NEXT: s_lshr_b32 s63, s11, 16
|
|
; SI-NEXT: s_lshr_b32 s73, s9, 16
|
|
; SI-NEXT: s_lshr_b32 s75, s7, 16
|
|
; SI-NEXT: s_lshr_b32 s45, s5, 16
|
|
; SI-NEXT: .LBB107_5: ; %end
|
|
; SI-NEXT: s_and_b32 s16, s42, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s17, s22, 16
|
|
; SI-NEXT: s_or_b32 s16, s16, s17
|
|
; SI-NEXT: s_and_b32 s17, s43, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s18, s47, 16
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_and_b32 s18, s40, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s19, s56, 16
|
|
; SI-NEXT: s_or_b32 s18, s18, s19
|
|
; SI-NEXT: s_and_b32 s19, s41, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s57, 16
|
|
; SI-NEXT: s_or_b32 s19, s19, s20
|
|
; SI-NEXT: s_and_b32 s14, s14, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s54, 16
|
|
; SI-NEXT: s_or_b32 s14, s14, s20
|
|
; SI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s59, 16
|
|
; SI-NEXT: s_or_b32 s15, s15, s20
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s92, 16
|
|
; SI-NEXT: s_or_b32 s12, s12, s20
|
|
; SI-NEXT: s_and_b32 s13, s13, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s61, 16
|
|
; SI-NEXT: s_or_b32 s13, s13, s20
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s60, 16
|
|
; SI-NEXT: s_or_b32 s10, s10, s20
|
|
; SI-NEXT: s_and_b32 s11, s11, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s63, 16
|
|
; SI-NEXT: s_or_b32 s11, s11, s20
|
|
; SI-NEXT: s_and_b32 s8, s8, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s62, 16
|
|
; SI-NEXT: s_or_b32 s8, s8, s20
|
|
; SI-NEXT: s_and_b32 s9, s9, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s73, 16
|
|
; SI-NEXT: s_or_b32 s9, s9, s20
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s72, 16
|
|
; SI-NEXT: s_or_b32 s6, s6, s20
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s75, 16
|
|
; SI-NEXT: s_or_b32 s7, s7, s20
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s74, 16
|
|
; SI-NEXT: s_or_b32 s4, s4, s20
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_lshl_b32 s20, s45, 16
|
|
; SI-NEXT: s_or_b32 s5, s5, s20
|
|
; SI-NEXT: v_readlane_b32 s30, v40, 34
|
|
; SI-NEXT: v_mov_b32_e32 v0, s16
|
|
; SI-NEXT: v_mov_b32_e32 v1, s17
|
|
; SI-NEXT: v_mov_b32_e32 v2, s18
|
|
; SI-NEXT: v_mov_b32_e32 v3, s19
|
|
; SI-NEXT: v_mov_b32_e32 v4, s14
|
|
; SI-NEXT: v_mov_b32_e32 v5, s15
|
|
; SI-NEXT: v_mov_b32_e32 v6, s12
|
|
; SI-NEXT: v_mov_b32_e32 v7, s13
|
|
; SI-NEXT: v_mov_b32_e32 v8, s10
|
|
; SI-NEXT: v_mov_b32_e32 v9, s11
|
|
; SI-NEXT: v_mov_b32_e32 v10, s8
|
|
; SI-NEXT: v_mov_b32_e32 v11, s9
|
|
; SI-NEXT: v_mov_b32_e32 v12, s6
|
|
; SI-NEXT: v_mov_b32_e32 v13, s7
|
|
; SI-NEXT: v_mov_b32_e32 v14, s4
|
|
; SI-NEXT: v_mov_b32_e32 v15, s5
|
|
; SI-NEXT: v_readlane_b32 s31, v40, 35
|
|
; SI-NEXT: v_readlane_b32 s99, v40, 33
|
|
; SI-NEXT: v_readlane_b32 s98, v40, 32
|
|
; SI-NEXT: v_readlane_b32 s97, v40, 31
|
|
; SI-NEXT: v_readlane_b32 s96, v40, 30
|
|
; SI-NEXT: v_readlane_b32 s87, v40, 29
|
|
; SI-NEXT: v_readlane_b32 s86, v40, 28
|
|
; SI-NEXT: v_readlane_b32 s85, v40, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v40, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v40, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v40, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v40, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v40, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v40, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v40, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v40, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v40, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v40, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v40, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v40, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v40, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v40, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v40, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v40, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v40, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v40, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v40, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v40, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v40, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v40, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v40, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v40, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v40, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v40, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v40, 0
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v32f16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s41, v30
|
|
; VI-NEXT: v_readfirstlane_b32 s14, v29
|
|
; VI-NEXT: v_readfirstlane_b32 s40, v28
|
|
; VI-NEXT: v_readfirstlane_b32 s12, v27
|
|
; VI-NEXT: v_readfirstlane_b32 s15, v26
|
|
; VI-NEXT: v_readfirstlane_b32 s10, v25
|
|
; VI-NEXT: v_readfirstlane_b32 s13, v24
|
|
; VI-NEXT: v_readfirstlane_b32 s8, v23
|
|
; VI-NEXT: v_readfirstlane_b32 s11, v22
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v21
|
|
; VI-NEXT: v_readfirstlane_b32 s9, v20
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v19
|
|
; VI-NEXT: v_readfirstlane_b32 s44, v18
|
|
; VI-NEXT: v_readfirstlane_b32 s42, v17
|
|
; VI-NEXT: v_readfirstlane_b32 s43, v16
|
|
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: v_readfirstlane_b32 s74, v15
|
|
; VI-NEXT: v_readfirstlane_b32 s76, v14
|
|
; VI-NEXT: v_readfirstlane_b32 s72, v13
|
|
; VI-NEXT: v_readfirstlane_b32 s75, v12
|
|
; VI-NEXT: v_readfirstlane_b32 s62, v11
|
|
; VI-NEXT: v_readfirstlane_b32 s73, v10
|
|
; VI-NEXT: v_readfirstlane_b32 s60, v9
|
|
; VI-NEXT: v_readfirstlane_b32 s63, v8
|
|
; VI-NEXT: v_readfirstlane_b32 s58, v7
|
|
; VI-NEXT: v_readfirstlane_b32 s61, v6
|
|
; VI-NEXT: v_readfirstlane_b32 s47, v5
|
|
; VI-NEXT: v_readfirstlane_b32 s59, v4
|
|
; VI-NEXT: v_readfirstlane_b32 s46, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s56, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s45, v1
|
|
; VI-NEXT: v_readfirstlane_b32 s57, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; VI-NEXT: s_cbranch_scc0 .LBB107_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_mov_b32_e32 v3, s23
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_mov_b32_e32 v2, s21
|
|
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s45
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: v_perm_b32 v4, s57, v4, v11
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_mov_b32_e32 v5, s47
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_mov_b32_e32 v4, s46
|
|
; VI-NEXT: v_perm_b32 v5, s59, v5, v11
|
|
; VI-NEXT: v_perm_b32 v4, s56, v4, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_mov_b32_e32 v6, s60
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_mov_b32_e32 v5, s58
|
|
; VI-NEXT: v_perm_b32 v6, s63, v6, v11
|
|
; VI-NEXT: v_perm_b32 v5, s61, v5, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_mov_b32_e32 v7, s72
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_mov_b32_e32 v6, s62
|
|
; VI-NEXT: v_perm_b32 v7, s75, v7, v11
|
|
; VI-NEXT: v_perm_b32 v6, s73, v6, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_mov_b32_e32 v8, s42
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_mov_b32_e32 v7, s74
|
|
; VI-NEXT: v_perm_b32 v8, s43, v8, v11
|
|
; VI-NEXT: v_perm_b32 v7, s76, v7, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_mov_b32_e32 v9, s7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_mov_b32_e32 v8, s6
|
|
; VI-NEXT: v_perm_b32 v9, s9, v9, v11
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_mov_b32_e32 v10, s10
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_mov_b32_e32 v9, s8
|
|
; VI-NEXT: v_perm_b32 v10, s13, v10, v11
|
|
; VI-NEXT: v_perm_b32 v9, s11, v9, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_mov_b32_e32 v12, s14
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_mov_b32_e32 v10, s12
|
|
; VI-NEXT: v_perm_b32 v12, s40, v12, v11
|
|
; VI-NEXT: v_perm_b32 v10, s15, v10, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; VI-NEXT: v_perm_b32 v12, v18, v17, s4
|
|
; VI-NEXT: v_perm_b32 v11, s41, v16, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
|
|
; VI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
|
|
; VI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
|
|
; VI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
|
|
; VI-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; VI-NEXT: s_cbranch_execnz .LBB107_3
|
|
; VI-NEXT: .LBB107_2: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v8, v0, v31, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(12)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v33
|
|
; VI-NEXT: v_perm_b32 v9, v0, v28, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(10)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v32
|
|
; VI-NEXT: v_perm_b32 v10, v0, v26, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(8)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v29
|
|
; VI-NEXT: v_perm_b32 v11, v0, v23, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(6)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v30
|
|
; VI-NEXT: v_perm_b32 v12, v0, v24, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v27
|
|
; VI-NEXT: v_perm_b32 v13, v0, v21, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v25
|
|
; VI-NEXT: v_perm_b32 v14, v0, v20, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v22
|
|
; VI-NEXT: v_perm_b32 v15, v0, v19, s4
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v18
|
|
; VI-NEXT: v_perm_b32 v17, v0, v17, s4
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
|
|
; VI-NEXT: s_add_i32 s40, s40, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s14
|
|
; VI-NEXT: v_perm_b32 v18, s40, v1, v0
|
|
; VI-NEXT: s_add_i32 s15, s15, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s12
|
|
; VI-NEXT: v_perm_b32 v19, s15, v1, v0
|
|
; VI-NEXT: s_add_i32 s13, s13, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s10
|
|
; VI-NEXT: v_perm_b32 v20, s13, v1, v0
|
|
; VI-NEXT: s_add_i32 s11, s11, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s8
|
|
; VI-NEXT: v_perm_b32 v21, s11, v1, v0
|
|
; VI-NEXT: s_add_i32 s9, s9, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
; VI-NEXT: v_perm_b32 v22, s9, v1, v0
|
|
; VI-NEXT: s_add_i32 s44, s44, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s6
|
|
; VI-NEXT: v_perm_b32 v23, s44, v1, v0
|
|
; VI-NEXT: s_add_i32 s43, s43, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s42
|
|
; VI-NEXT: v_perm_b32 v7, s43, v1, v0
|
|
; VI-NEXT: s_add_i32 s76, s76, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s74
|
|
; VI-NEXT: v_perm_b32 v24, s76, v1, v0
|
|
; VI-NEXT: s_add_i32 s75, s75, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s72
|
|
; VI-NEXT: v_perm_b32 v6, s75, v1, v0
|
|
; VI-NEXT: s_add_i32 s73, s73, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s62
|
|
; VI-NEXT: v_perm_b32 v25, s73, v1, v0
|
|
; VI-NEXT: s_add_i32 s63, s63, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s60
|
|
; VI-NEXT: v_perm_b32 v5, s63, v1, v0
|
|
; VI-NEXT: s_add_i32 s61, s61, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s58
|
|
; VI-NEXT: v_perm_b32 v26, s61, v1, v0
|
|
; VI-NEXT: s_add_i32 s59, s59, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s47
|
|
; VI-NEXT: v_perm_b32 v4, s59, v1, v0
|
|
; VI-NEXT: s_add_i32 s56, s56, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s46
|
|
; VI-NEXT: v_perm_b32 v27, s56, v1, v0
|
|
; VI-NEXT: s_add_i32 s57, s57, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s45
|
|
; VI-NEXT: v_perm_b32 v3, s57, v1, v0
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s29
|
|
; VI-NEXT: v_perm_b32 v28, s28, v1, v0
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s27
|
|
; VI-NEXT: v_perm_b32 v2, s26, v1, v0
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s25
|
|
; VI-NEXT: s_add_i32 s41, s41, 3
|
|
; VI-NEXT: v_perm_b32 v29, s24, v1, v0
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s23
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: v_mov_b32_e32 v30, s21
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: v_mov_b32_e32 v31, s19
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: v_mov_b32_e32 v32, s17
|
|
; VI-NEXT: v_perm_b32 v16, s41, v16, v0
|
|
; VI-NEXT: v_perm_b32 v1, s22, v1, v0
|
|
; VI-NEXT: v_perm_b32 v30, s20, v30, v0
|
|
; VI-NEXT: v_perm_b32 v31, s18, v31, v0
|
|
; VI-NEXT: v_perm_b32 v0, s16, v32, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, 0x300, v28
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, 0x300, v27
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, 0x300, v26
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x300, v25
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, 0x300, v24
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, 0x300, v30
|
|
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x300, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, 0x300, v29
|
|
; VI-NEXT: v_or_b32_sdwa v3, v3, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v4, v4, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v5, v5, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v6, v6, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v7, v7, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v8
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x300, v9
|
|
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, 0x300, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x300, v13
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v14
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x300, v15
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v17
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x300, v16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v18
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x300, v19
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v20
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x300, v21
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x300, v23
|
|
; VI-NEXT: v_or_b32_sdwa v0, v31, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v1, v1, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v2, v2, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v8, v8, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v9, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v10, v10, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v11, v11, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v12, v12, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v13, v28, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v14, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v15, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x3000000, v3
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x3000000, v4
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x3000000, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x3000000, v6
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x3000000, v10
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x3000000, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x3000000, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x3000000, v13
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x3000000, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x3000000, v15
|
|
; VI-NEXT: .LBB107_3: ; %end
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB107_4:
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_branch .LBB107_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v32f16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s72, v30
|
|
; GFX9-NEXT: v_readfirstlane_b32 s56, v29
|
|
; GFX9-NEXT: v_readfirstlane_b32 s57, v28
|
|
; GFX9-NEXT: v_readfirstlane_b32 s61, v27
|
|
; GFX9-NEXT: v_readfirstlane_b32 s63, v26
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v25
|
|
; GFX9-NEXT: v_readfirstlane_b32 s47, v24
|
|
; GFX9-NEXT: v_readfirstlane_b32 s58, v23
|
|
; GFX9-NEXT: v_readfirstlane_b32 s60, v22
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v21
|
|
; GFX9-NEXT: v_readfirstlane_b32 s8, v20
|
|
; GFX9-NEXT: v_readfirstlane_b32 s9, v19
|
|
; GFX9-NEXT: v_readfirstlane_b32 s10, v18
|
|
; GFX9-NEXT: v_readfirstlane_b32 s11, v17
|
|
; GFX9-NEXT: v_readfirstlane_b32 s12, v16
|
|
; GFX9-NEXT: v_readfirstlane_b32 s15, v12
|
|
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s13, v15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s73, v14
|
|
; GFX9-NEXT: v_readfirstlane_b32 s14, v13
|
|
; GFX9-NEXT: v_readfirstlane_b32 s40, v11
|
|
; GFX9-NEXT: v_readfirstlane_b32 s76, v10
|
|
; GFX9-NEXT: v_readfirstlane_b32 s41, v9
|
|
; GFX9-NEXT: v_readfirstlane_b32 s42, v8
|
|
; GFX9-NEXT: v_readfirstlane_b32 s43, v7
|
|
; GFX9-NEXT: v_readfirstlane_b32 s75, v6
|
|
; GFX9-NEXT: v_readfirstlane_b32 s44, v5
|
|
; GFX9-NEXT: v_readfirstlane_b32 s45, v4
|
|
; GFX9-NEXT: v_readfirstlane_b32 s46, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s74, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s59, v1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s62, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
|
|
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB107_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s59
|
|
; GFX9-NEXT: v_perm_b32 v4, s62, v4, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s46
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s44
|
|
; GFX9-NEXT: v_perm_b32 v5, s45, v5, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s43
|
|
; GFX9-NEXT: v_perm_b32 v5, s75, v5, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s41
|
|
; GFX9-NEXT: v_perm_b32 v6, s42, v6, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s40
|
|
; GFX9-NEXT: v_perm_b32 v6, s76, v6, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s14
|
|
; GFX9-NEXT: v_perm_b32 v7, s15, v7, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s13
|
|
; GFX9-NEXT: v_perm_b32 v7, s73, v7, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s11
|
|
; GFX9-NEXT: v_perm_b32 v9, s12, v9, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(18)
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v16
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v10, s72, v18, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v26
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v29, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v19
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v21, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v20
|
|
; GFX9-NEXT: v_perm_b32 v10, v31, v28, s4
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v23, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v30
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v33, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v22
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v25, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v24
|
|
; GFX9-NEXT: v_perm_b32 v10, v34, v32, s4
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v27, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s58
|
|
; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
|
|
; GFX9-NEXT: s_and_b32 s4, s47, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s5, s7, 8
|
|
; GFX9-NEXT: s_or_b32 s4, s4, s5
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
|
|
; GFX9-NEXT: s_and_b32 s4, s10, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s5, s9, 8
|
|
; GFX9-NEXT: s_or_b32 s4, s4, s5
|
|
; GFX9-NEXT: s_and_b32 s5, s8, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s77, s6, 8
|
|
; GFX9-NEXT: s_or_b32 s5, s5, s77
|
|
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
|
|
; GFX9-NEXT: s_and_b32 s5, s63, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s77, s61, 8
|
|
; GFX9-NEXT: s_or_b32 s5, s5, s77
|
|
; GFX9-NEXT: s_and_b32 s77, s57, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s78, s56, 8
|
|
; GFX9-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s5
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
|
|
; GFX9-NEXT: .LBB107_2: ; %cmp.true
|
|
; GFX9-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v34
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v8, v0, v32, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v27
|
|
; GFX9-NEXT: v_perm_b32 v9, v0, v24, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v33
|
|
; GFX9-NEXT: v_perm_b32 v10, v0, v30, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v25
|
|
; GFX9-NEXT: v_perm_b32 v11, v0, v22, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v31
|
|
; GFX9-NEXT: v_perm_b32 v12, v0, v28, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v23
|
|
; GFX9-NEXT: v_perm_b32 v13, v0, v20, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v29
|
|
; GFX9-NEXT: v_perm_b32 v14, v0, v26, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v21
|
|
; GFX9-NEXT: v_perm_b32 v15, v0, v19, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v17
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v16, v0, v16, s4
|
|
; GFX9-NEXT: s_add_i32 s63, s63, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s61
|
|
; GFX9-NEXT: v_perm_b32 v17, s63, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s57, s57, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s56
|
|
; GFX9-NEXT: v_perm_b32 v20, s57, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s58
|
|
; GFX9-NEXT: v_perm_b32 v21, s60, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s21
|
|
; GFX9-NEXT: v_perm_b32 v0, s20, v0, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 0x300, v0
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s23
|
|
; GFX9-NEXT: v_perm_b32 v0, s22, v0, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v0
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_perm_b32 v3, s18, v3, v19
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v19
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v19
|
|
; GFX9-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s59
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_perm_b32 v4, s62, v4, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX9-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s46
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v19
|
|
; GFX9-NEXT: s_add_i32 s45, s45, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s44
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_perm_b32 v5, s45, v5, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX9-NEXT: s_add_i32 s75, s75, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s43
|
|
; GFX9-NEXT: v_perm_b32 v5, s75, v5, v19
|
|
; GFX9-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s41
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_perm_b32 v6, s42, v6, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX9-NEXT: s_add_i32 s76, s76, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s40
|
|
; GFX9-NEXT: v_perm_b32 v6, s76, v6, v19
|
|
; GFX9-NEXT: s_add_i32 s15, s15, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s14
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_perm_b32 v7, s15, v7, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX9-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s13
|
|
; GFX9-NEXT: v_perm_b32 v7, s73, v7, v19
|
|
; GFX9-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s11
|
|
; GFX9-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_perm_b32 v22, s12, v22, v19
|
|
; GFX9-NEXT: v_perm_b32 v18, s72, v18, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v22, 0x300, v22
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX9-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v23, s9
|
|
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v14
|
|
; GFX9-NEXT: s_add_i32 s47, s47, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v22, 16, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s7
|
|
; GFX9-NEXT: v_perm_b32 v23, s10, v23, v19
|
|
; GFX9-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v24, s6
|
|
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v18
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX9-NEXT: v_perm_b32 v22, s47, v22, v19
|
|
; GFX9-NEXT: v_perm_b32 v19, s8, v24, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v24, 0x300, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v26, 0x300, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v16
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 0x300, v21
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 0x300, v23
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v14, 16, v12
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff, v28
|
|
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v20
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x300, v22
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x300, v19
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v15, 16, v11
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff, v26
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff, v24
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v18, 16, v8
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v17, 16, v9
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v16, 16, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v27, 16, v14
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v25, 16, v15
|
|
; GFX9-NEXT: .LBB107_3: ; %end
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB107_4:
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_branch .LBB107_2
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32f16_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0xf
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB107_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
|
|
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
|
|
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB107_3
|
|
; GFX11-TRUE16-NEXT: .LBB107_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v29, s2, s3, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v30, s18, s19, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v31, s16, s17, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v32, s0, s1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v24
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v29
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v31
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v29.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v30.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v27.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v28.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v24.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v26.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v25.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v23.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v22.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v21.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v20.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v19.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v18.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v17.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
|
|
; GFX11-TRUE16-NEXT: .LBB107_3: ; %end
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB107_4:
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB107_2
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32f16_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_clause 0xf
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v30
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v29
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v28
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v27
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v26
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v25
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v24
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v23
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v22
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v21
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v20
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v19
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v18
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v16
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v15
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v14
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v13
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v12
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v11
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v10
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v9
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v8
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v7
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v6
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v5
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v3
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v2
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB107_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s41, 8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s77, s44, 0xff
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s40, s13, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
|
|
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v16, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB107_3
|
|
; GFX11-FAKE16-NEXT: .LBB107_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v52
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v50
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v49
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s43, s43, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s74, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s56, s45, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s73, s63, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s44, s41, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s72, s62, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s60, s57, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s61, s61, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s43, s15, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s7, s5, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s61, s59, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s46, s42, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s12, s9, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s26, s27, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v28, s0, s1, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s58, s47, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s40, s13, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s24, s25, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s20, s21, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v29, s16, s17, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v30, s2, s3, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s10, s8, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s28, s29, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v29
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v31, s22, s23, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s18, s19, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v30, 16, v28
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v32
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v27, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v26, 16, v32
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v23, 16, v22
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v21, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v28
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v31, 16, v29
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v30
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v25, 16, v24
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v9, 16, v26
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v10, 16, v27
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v20, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v18, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v14, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v22
|
|
; GFX11-FAKE16-NEXT: .LBB107_3: ; %end
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB107_4:
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB107_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <32 x half>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <32 x half>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x half> %phi
|
|
}
|
|
|
|
define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v64i8:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v29, 1.0, v1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_and_b32_e32 v35, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v37, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v39, 0xffff0000, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v34, 0xffff0000, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v3
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; SI-NEXT: v_mul_f32_e32 v28, 1.0, v27
|
|
; SI-NEXT: v_mul_f32_e32 v22, 1.0, v22
|
|
; SI-NEXT: v_mul_f32_e32 v27, 1.0, v2
|
|
; SI-NEXT: v_mul_f32_e32 v32, 1.0, v31
|
|
; SI-NEXT: v_mul_f32_e32 v33, 1.0, v3
|
|
; SI-NEXT: v_mul_f32_e32 v24, 1.0, v24
|
|
; SI-NEXT: v_mul_f32_e32 v31, 1.0, v4
|
|
; SI-NEXT: v_mul_f32_e32 v36, 1.0, v34
|
|
; SI-NEXT: v_mul_f32_e32 v38, 1.0, v5
|
|
; SI-NEXT: v_mul_f32_e32 v25, 1.0, v25
|
|
; SI-NEXT: v_mul_f32_e32 v34, 1.0, v6
|
|
; SI-NEXT: v_mul_f32_e32 v49, 1.0, v39
|
|
; SI-NEXT: v_mul_f32_e32 v51, 1.0, v7
|
|
; SI-NEXT: v_mul_f32_e32 v26, 1.0, v26
|
|
; SI-NEXT: v_mul_f32_e32 v39, 1.0, v8
|
|
; SI-NEXT: v_mul_f32_e32 v54, 1.0, v37
|
|
; SI-NEXT: v_mul_f32_e32 v55, 1.0, v9
|
|
; SI-NEXT: v_mul_f32_e32 v30, 1.0, v30
|
|
; SI-NEXT: v_mul_f32_e32 v53, 1.0, v10
|
|
; SI-NEXT: v_mul_f32_e32 v42, 1.0, v35
|
|
; SI-NEXT: v_mul_f32_e32 v43, 1.0, v11
|
|
; SI-NEXT: v_mul_f32_e32 v35, 1.0, v23
|
|
; SI-NEXT: v_mul_f32_e32 v41, 1.0, v12
|
|
; SI-NEXT: v_mul_f32_e32 v45, 1.0, v21
|
|
; SI-NEXT: v_mul_f32_e32 v46, 1.0, v13
|
|
; SI-NEXT: v_mul_f32_e32 v52, 1.0, v20
|
|
; SI-NEXT: v_mul_f32_e32 v44, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v56, 1.0, v19
|
|
; SI-NEXT: s_waitcnt expcnt(6)
|
|
; SI-NEXT: v_mul_f32_e32 v57, 1.0, v15
|
|
; SI-NEXT: v_mul_f32_e32 v40, 1.0, v18
|
|
; SI-NEXT: v_mul_f32_e32 v47, 1.0, v16
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB108_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v28
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v22
|
|
; SI-NEXT: v_alignbit_b32 v48, v1, v29, 16
|
|
; SI-NEXT: v_alignbit_b32 v50, v37, v27, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v50, v48, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v50, v48, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v50, v48, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v32
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v24
|
|
; SI-NEXT: v_alignbit_b32 v23, v1, v33, 16
|
|
; SI-NEXT: v_alignbit_b32 v21, v19, v31, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v21, v23, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v21, v23, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v21, v23, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v25
|
|
; SI-NEXT: v_alignbit_b32 v17, v1, v38, 16
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v34, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v18, v17, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v18, v17, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v18, v17, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
|
|
; SI-NEXT: v_alignbit_b32 v14, v1, v51, 16
|
|
; SI-NEXT: v_alignbit_b32 v15, v13, v39, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v15, v14, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v15, v14, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v15, v14, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v54
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v30
|
|
; SI-NEXT: v_alignbit_b32 v11, v1, v55, 16
|
|
; SI-NEXT: v_alignbit_b32 v12, v10, v53, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v12, v11, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v12, v11, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v12, v11, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v42
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v35
|
|
; SI-NEXT: v_alignbit_b32 v8, v1, v43, 16
|
|
; SI-NEXT: v_alignbit_b32 v9, v7, v41, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v9, v8, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v9, v8, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v9, v8, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v45
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v52
|
|
; SI-NEXT: v_alignbit_b32 v5, v1, v46, 16
|
|
; SI-NEXT: v_alignbit_b32 v6, v4, v44, 16
|
|
; SI-NEXT: v_alignbit_b32 v1, v6, v5, 24
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v6, v5, 16
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v1, v6, v5, 8
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v56
|
|
; SI-NEXT: v_alignbit_b32 v2, v1, v57, 16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
|
|
; SI-NEXT: v_alignbit_b32 v3, v1, v47, 16
|
|
; SI-NEXT: v_alignbit_b32 v20, v3, v2, 24
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v3, v2, 16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v3, v2, 8
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 24, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v18
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v26
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v15
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v30
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v35
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v40
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v9
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v6
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v3
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 8, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 8, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 24, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v58, 24, v52
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v12
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: .LBB108_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB108_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v32
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
|
|
; SI-NEXT: v_alignbit_b32 v23, v20, v19, 16
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v19
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v24
|
|
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v19, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
|
|
; SI-NEXT: v_alignbit_b32 v21, v19, v20, 16
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v29
|
|
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v28
|
|
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v28, 16, v28
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
|
|
; SI-NEXT: v_alignbit_b32 v48, v28, v20, 16
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v27
|
|
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v36
|
|
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; SI-NEXT: v_lshrrev_b32_e32 v37, 16, v22
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v38
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; SI-NEXT: v_alignbit_b32 v50, v37, v20, 16
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; SI-NEXT: v_alignbit_b32 v20, v50, v48, 24
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v49
|
|
; SI-NEXT: v_alignbit_b32 v17, v17, v16, 16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v34
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v50, v48, 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v51
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v25
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v50, v48, 8
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v21, v23, 24
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v54
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v13, 16
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v39
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v25
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v21, v23, 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v55
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v26
|
|
; SI-NEXT: v_alignbit_b32 v18, v16, v18, 16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v21, v23, 8
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v13
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v18, v17, 24
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v42
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v10, 16
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v53
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v26
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v18, v17, 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v43
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v30
|
|
; SI-NEXT: v_alignbit_b32 v15, v13, v15, 16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v18, v17, 8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_add_f32_e32 v30, 0x40c00000, v10
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v15, v14, 24
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v45
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v7, 16
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v30
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v15, v14, 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v46
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v35
|
|
; SI-NEXT: v_alignbit_b32 v12, v10, v12, 16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v15, v14, 8
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_add_f32_e32 v35, 0x40c00000, v7
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v12, v11, 24
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v56
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v4, 16
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v44
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v35
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v12, v11, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v57
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v4
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v52
|
|
; SI-NEXT: v_alignbit_b32 v9, v7, v9, 16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v12, v11, 8
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_add_f32_e32 v52, 0x40c00000, v4
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v9, v8, 24
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v1, 16
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v47
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v52
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v9, v8, 16
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v1
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v40
|
|
; SI-NEXT: v_alignbit_b32 v6, v4, v6, 16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v9, v8, 8
|
|
; SI-NEXT: v_add_f32_e32 v40, 0x40c00000, v1
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v6, v5, 24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v40
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v6, v5, 16
|
|
; SI-NEXT: v_alignbit_b32 v3, v1, v3, 16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v6, v5, 8
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v3, v2, 24
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v3, v2, 16
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_alignbit_b32 v20, v3, v2, 8
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 8, v18
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 8, v15
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v20, 24, v22
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v26
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v30
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v35
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 24, v40
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v9
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v6
|
|
; SI-NEXT: v_lshrrev_b32_e32 v63, 8, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v59, 8, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v62, 24, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v60, 24, v25
|
|
; SI-NEXT: v_lshrrev_b32_e32 v58, 24, v52
|
|
; SI-NEXT: v_lshrrev_b32_e32 v61, 8, v12
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshrrev_b32_e32 v22, 8, v3
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: .LBB108_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xff, v48
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v17
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v24
|
|
; SI-NEXT: v_or_b32_e32 v22, v22, v24
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v25, 24, v25
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xff, v24
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_or_b32_e32 v24, v25, v24
|
|
; SI-NEXT: v_or_b32_e32 v22, v22, v24
|
|
; SI-NEXT: buffer_store_dword v22, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xff, v50
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 8, v63
|
|
; SI-NEXT: v_or_b32_e32 v22, v22, v24
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xff, v37
|
|
; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff, v22
|
|
; SI-NEXT: v_or_b32_e32 v20, v20, v24
|
|
; SI-NEXT: v_or_b32_e32 v20, v22, v20
|
|
; SI-NEXT: v_add_i32_e32 v22, vcc, 4, v0
|
|
; SI-NEXT: buffer_store_dword v20, v22, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xff, v23
|
|
; SI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v22
|
|
; SI-NEXT: v_or_b32_e32 v20, v20, v22
|
|
; SI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 24, v23
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
|
|
; SI-NEXT: v_or_b32_e32 v22, v23, v22
|
|
; SI-NEXT: v_or_b32_e32 v20, v20, v22
|
|
; SI-NEXT: v_add_i32_e32 v22, vcc, 8, v0
|
|
; SI-NEXT: buffer_store_dword v20, v22, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xff, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 8, v59
|
|
; SI-NEXT: v_or_b32_e32 v20, v20, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v21, 24, v62
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff, v20
|
|
; SI-NEXT: v_or_b32_e32 v19, v21, v19
|
|
; SI-NEXT: v_or_b32_e32 v19, v20, v19
|
|
; SI-NEXT: v_add_i32_e32 v20, vcc, 12, v0
|
|
; SI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 8, v19
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v19
|
|
; SI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v20, 24, v20
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xff, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
|
|
; SI-NEXT: v_or_b32_e32 v19, v20, v19
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v19
|
|
; SI-NEXT: v_add_i32_e32 v19, vcc, 16, v0
|
|
; SI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xff, v18
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 8, v18
|
|
; SI-NEXT: v_or_b32_e32 v17, v17, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v18, 24, v60
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; SI-NEXT: v_or_b32_e32 v16, v18, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v17, v16
|
|
; SI-NEXT: v_add_i32_e32 v17, vcc, 20, v0
|
|
; SI-NEXT: buffer_store_dword v16, v17, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v17, 24, v17
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v17, v16
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v16
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 24, v0
|
|
; SI-NEXT: buffer_store_dword v14, v16, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v15
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 8, v15
|
|
; SI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 24, v15
|
|
; SI-NEXT: v_or_b32_e32 v13, v15, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 28, v0
|
|
; SI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 8, v13
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v13
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 24, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v13
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 32, v0
|
|
; SI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v61
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 24, v12
|
|
; SI-NEXT: v_or_b32_e32 v10, v12, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 36, v0
|
|
; SI-NEXT: buffer_store_dword v10, v11, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v10
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 24, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v10
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 40, v0
|
|
; SI-NEXT: buffer_store_dword v8, v10, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v9
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 8, v9
|
|
; SI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 24, v9
|
|
; SI-NEXT: v_or_b32_e32 v7, v9, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 44, v0
|
|
; SI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 8, v7
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v8
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v7
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 48, v0
|
|
; SI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v6
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v6
|
|
; SI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 24, v58
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 52, v0
|
|
; SI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v5, v4
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 56, v0
|
|
; SI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xff, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; SI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v64i8:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; kill: killed $vgpr17
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB108_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v16
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: v_mov_b32_e32 v27, v21
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: .LBB108_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB108_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v2
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
|
|
; VI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v2, 16, 1
|
|
; VI-NEXT: s_movk_i32 s6, 0x7fff
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v2
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_alignbit_b32 v2, v2, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v1
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_alignbit_b32 v1, v1, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v4
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v4, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v4
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_alignbit_b32 v4, v4, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v3
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v3
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_alignbit_b32 v3, v3, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v6
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v6, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v6
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v6
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_alignbit_b32 v6, v6, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v5
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v5
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_alignbit_b32 v5, v5, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v8
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v8
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_alignbit_b32 v8, v8, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v7
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v7
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_alignbit_b32 v7, v7, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v10
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v10, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v10
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v10
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; VI-NEXT: v_cndmask_b32_e32 v10, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_alignbit_b32 v10, v10, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v9
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v9
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_alignbit_b32 v9, v9, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v12
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v12, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v12
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v12
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; VI-NEXT: v_cndmask_b32_e32 v12, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_alignbit_b32 v12, v12, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v11
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v11
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_alignbit_b32 v11, v11, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v14
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v14
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_alignbit_b32 v14, v14, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v13
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v13
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_alignbit_b32 v13, v13, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v16
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v16
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: v_alignbit_b32 v16, v16, v17, 16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v15
|
|
; VI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_bfe_u32 v18, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v15
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, s6, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_alignbit_b32 v15, v15, v17, 16
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[7:8]
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[3:4]
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[1:2]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v27, 16, v16
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v15
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 24, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 24, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 16, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 8, v12
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v9
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 24, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 24, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 16, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v6
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v3
|
|
; VI-NEXT: v_lshrrev_b32_e32 v63, 24, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v30, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v1
|
|
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: .LBB108_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v21
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
|
|
; VI-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
|
|
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
|
|
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
|
|
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
|
|
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
|
|
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
|
|
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
|
|
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
|
|
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
|
|
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
|
|
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
|
|
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
|
|
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v64i8:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; kill: killed $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB108_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v16
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v15
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v14
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v13
|
|
; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 24, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 24, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 8, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 24, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 8, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 8, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 24, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 8, v1
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX9-NEXT: .LBB108_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB108_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; GFX9-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX9-NEXT: s_movk_i32 s6, 0x7fff
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX9-NEXT: v_add3_u32 v18, v18, v17, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; GFX9-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v18, v2, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v18, v18, v2, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v19, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v19, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v1
|
|
; GFX9-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; GFX9-NEXT: v_bfe_u32 v19, v18, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX9-NEXT: v_add3_u32 v19, v19, v18, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
|
|
; GFX9-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v19, v1, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v19, v19, v1, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v20, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v19, v20, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v4
|
|
; GFX9-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
|
|
; GFX9-NEXT: v_bfe_u32 v20, v19, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX9-NEXT: v_add3_u32 v20, v20, v19, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v21, 0x400000, v19
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
|
|
; GFX9-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v20, v4, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v20, v20, v4, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v21, 0x400000, v4
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v4, v20, v21, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; GFX9-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; GFX9-NEXT: v_bfe_u32 v21, v20, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX9-NEXT: v_add3_u32 v21, v21, v20, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v22, 0x400000, v20
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
|
|
; GFX9-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v21, v3, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v21, v21, v3, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v22, 0x400000, v3
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v3, v21, v22, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v6
|
|
; GFX9-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
|
|
; GFX9-NEXT: v_bfe_u32 v22, v21, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX9-NEXT: v_add3_u32 v22, v22, v21, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v23, 0x400000, v21
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
|
|
; GFX9-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v22, v6, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v22, v22, v6, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v23, 0x400000, v6
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v6, v22, v23, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v5
|
|
; GFX9-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; GFX9-NEXT: v_bfe_u32 v23, v22, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; GFX9-NEXT: v_add3_u32 v23, v23, v22, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v24, 0x400000, v22
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
|
|
; GFX9-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v22, v23, v24, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v23, v5, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v23, v23, v5, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v24, 0x400000, v5
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v5, v23, v24, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v8
|
|
; GFX9-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; GFX9-NEXT: v_bfe_u32 v24, v23, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX9-NEXT: v_add3_u32 v24, v24, v23, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v25, 0x400000, v23
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
|
|
; GFX9-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v24, v8, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v24, v24, v8, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v25, 0x400000, v8
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v8, v24, v25, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v7
|
|
; GFX9-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
|
|
; GFX9-NEXT: v_bfe_u32 v25, v24, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX9-NEXT: v_add3_u32 v25, v25, v24, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v26, 0x400000, v24
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
|
|
; GFX9-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v25, v7, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v25, v25, v7, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v26, 0x400000, v7
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v7, v25, v26, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v10
|
|
; GFX9-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
|
|
; GFX9-NEXT: v_bfe_u32 v26, v25, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; GFX9-NEXT: v_add3_u32 v26, v26, v25, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v27, 0x400000, v25
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v25, v25
|
|
; GFX9-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v25, v26, v27, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v26, v10, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v26, v26, v10, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v27, 0x400000, v10
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v10, v26, v27, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v9
|
|
; GFX9-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
|
|
; GFX9-NEXT: v_bfe_u32 v27, v26, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; GFX9-NEXT: v_add3_u32 v27, v27, v26, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v36, 0x400000, v26
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v26, v26
|
|
; GFX9-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v26, v27, v36, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v27, v9, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v27, v27, v9, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v36, 0x400000, v9
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v9, v27, v36, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v12
|
|
; GFX9-NEXT: v_add_f32_e32 v27, 0x40c00000, v27
|
|
; GFX9-NEXT: v_bfe_u32 v38, v27, 16, 1
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX9-NEXT: v_add3_u32 v38, v38, v27, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v39, 0x400000, v27
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v27, v27
|
|
; GFX9-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v27, v38, v39, vcc
|
|
; GFX9-NEXT: v_bfe_u32 v38, v12, 16, 1
|
|
; GFX9-NEXT: v_add3_u32 v38, v38, v12, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v39, 0x400000, v12
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v12, v38, v39, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v38, 16, v11
|
|
; GFX9-NEXT: v_add_f32_e32 v38, 0x40c00000, v38
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX9-NEXT: v_bfe_u32 v48, v38, 16, 1
|
|
; GFX9-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; GFX9-NEXT: v_add3_u32 v48, v48, v38, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v49, 0x400000, v38
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v38, v38
|
|
; GFX9-NEXT: v_bfe_u32 v38, v11, 16, 1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v52, v48, v49, vcc
|
|
; GFX9-NEXT: v_add3_u32 v38, v38, v11, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v48, 0x400000, v11
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v11, v38, v48, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v14
|
|
; GFX9-NEXT: v_add_f32_e32 v48, 0x40c00000, v48
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; GFX9-NEXT: v_bfe_u32 v49, v48, 16, 1
|
|
; GFX9-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX9-NEXT: v_add3_u32 v49, v49, v48, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v50, 0x400000, v48
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v48, v48
|
|
; GFX9-NEXT: v_bfe_u32 v48, v14, 16, 1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v53, v49, v50, vcc
|
|
; GFX9-NEXT: v_add3_u32 v48, v48, v14, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v49, 0x400000, v14
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v14, v48, v49, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v13
|
|
; GFX9-NEXT: v_add_f32_e32 v48, 0x40c00000, v48
|
|
; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX9-NEXT: v_bfe_u32 v50, v48, 16, 1
|
|
; GFX9-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; GFX9-NEXT: v_add3_u32 v50, v50, v48, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v51, 0x400000, v48
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v48, v48
|
|
; GFX9-NEXT: v_bfe_u32 v48, v13, 16, 1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v54, v50, v51, vcc
|
|
; GFX9-NEXT: v_add3_u32 v48, v48, v13, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v50, 0x400000, v13
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v13, v48, v50, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v16
|
|
; GFX9-NEXT: v_add_f32_e32 v50, 0x40c00000, v50
|
|
; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; GFX9-NEXT: v_bfe_u32 v51, v50, 16, 1
|
|
; GFX9-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX9-NEXT: v_add3_u32 v51, v51, v50, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v55, 0x400000, v50
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v50, v50
|
|
; GFX9-NEXT: v_bfe_u32 v50, v16, 16, 1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v55, v51, v55, vcc
|
|
; GFX9-NEXT: v_add3_u32 v50, v50, v16, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v51, 0x400000, v16
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v16, v50, v51, vcc
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v15
|
|
; GFX9-NEXT: v_add_f32_e32 v50, 0x40c00000, v50
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX9-NEXT: v_bfe_u32 v40, v50, 16, 1
|
|
; GFX9-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX9-NEXT: v_add3_u32 v40, v40, v50, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v41, 0x400000, v50
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v50, v50
|
|
; GFX9-NEXT: v_bfe_u32 v50, v15, 16, 1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v40, v40, v41, vcc
|
|
; GFX9-NEXT: v_add3_u32 v50, v50, v15, s6
|
|
; GFX9-NEXT: v_or_b32_e32 v41, 0x400000, v15
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; GFX9-NEXT: s_mov_b32 s7, 0x7060302
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v15, v50, v41, vcc
|
|
; GFX9-NEXT: v_perm_b32 v51, v16, v55, s7
|
|
; GFX9-NEXT: v_perm_b32 v50, v15, v40, s7
|
|
; GFX9-NEXT: v_perm_b32 v29, v2, v17, s7
|
|
; GFX9-NEXT: v_perm_b32 v28, v1, v18, s7
|
|
; GFX9-NEXT: v_perm_b32 v49, v14, v53, s7
|
|
; GFX9-NEXT: v_perm_b32 v48, v13, v54, s7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v17
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v63, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v18
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[50:51]
|
|
; GFX9-NEXT: v_perm_b32 v31, v4, v19, s7
|
|
; GFX9-NEXT: v_perm_b32 v39, v12, v27, s7
|
|
; GFX9-NEXT: v_perm_b32 v38, v11, v52, s7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v19
|
|
; GFX9-NEXT: v_lshrrev_b64 v[18:19], 24, v[48:49]
|
|
; GFX9-NEXT: v_perm_b32 v30, v3, v20, s7
|
|
; GFX9-NEXT: v_perm_b32 v35, v8, v23, s7
|
|
; GFX9-NEXT: v_perm_b32 v34, v7, v24, s7
|
|
; GFX9-NEXT: v_perm_b32 v37, v10, v25, s7
|
|
; GFX9-NEXT: v_perm_b32 v36, v9, v26, s7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v3
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v20
|
|
; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[38:39]
|
|
; GFX9-NEXT: v_perm_b32 v33, v6, v21, s7
|
|
; GFX9-NEXT: v_perm_b32 v32, v5, v22, s7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v8
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v23
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v24
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v6
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v21
|
|
; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[36:37]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[34:35]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v40
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v54
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v12
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v27
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v25
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v9
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v26
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v5
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v22
|
|
; GFX9-NEXT: v_lshrrev_b64 v[26:27], 24, v[32:33]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[30:31]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[28:29]
|
|
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v55
|
|
; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v53
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v52
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v51
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v51
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v50
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 24, v49
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 8, v49
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v48
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v39
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v39
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v38
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 24, v37
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v37
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 8, v36
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 24, v35
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v35
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v34
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v33
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 8, v33
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v32
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 24, v31
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v31
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 8, v30
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 24, v29
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v29
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 8, v28
|
|
; GFX9-NEXT: .LBB108_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v22, v63, v24, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v1, v28, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v22, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: v_perm_b32 v1, v61, v53, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
|
|
; GFX9-NEXT: v_perm_b32 v21, v60, v21, s4
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v30, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v21, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v1, v4, v31, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v58, v52, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v1, v5, v32, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v47, v26, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v1, v6, v33, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v44, v51, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v1, v7, v34, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v43, v23, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v1, v8, v35, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v42, v50, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v1, v9, v36, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v41, v20, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v1, v10, v37, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v40, v62, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v1, v11, v38, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v55, v19, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v1, v12, v39, s4
|
|
; GFX9-NEXT: v_perm_b32 v2, v54, v59, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v13, v48, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v18, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v14, v49, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v57, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v15, v56, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v17, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v16, v46, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v2, v45, s4
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v64i8:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr131_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr130_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr129_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr128_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr119_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr116_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr114_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr113_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr112_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr103_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr102_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr101_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr100_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr115_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr118_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr117_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
|
|
; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_2
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[11:12]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[9:10]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[7:8]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[15:16]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[30:31], 24, v[13:14]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v1.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v2.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v3.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.h, v4.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v4.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v5.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v6.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v7.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v8.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.h, v9.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v9.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.h, v11.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v11.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.h, v12.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v12.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.h, v13.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.h, v13.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.h, v14.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.h, v14.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.h, v15.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.h, v15.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.h, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.h, v16.h
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr9
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr13
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr15
|
|
; GFX11-TRUE16-NEXT: .LBB108_2: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB108_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v20, 0x40c00000, v18
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v24, v20, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v17
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v18, v18, v17, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v17, v24, v20, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v52, v18, v23 :: v_dual_lshlrev_b32 v1, 16, v1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v2, 0x40c00000, v2 :: v_dual_add_f32 v1, 0x40c00000, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v21, v21, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v23, v25, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v21, v22, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v19
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v52.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v53, v23, v26, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v19, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v22, 0x40c00000, v20 :: v_dual_add_f32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v19, v19, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v53.h
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v4, v22, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 24, v18
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v54, v19, v21, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v4, v22, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v22
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v1, v20, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[50:51], 24, v[17:18]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 8, v18
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 8, v17
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v55, v1, v19, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v54.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v4, v21, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v55.h
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 24, v20
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 8, v20
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 8, v19
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v8
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v64, v3, v21 :: v_dual_and_b32 v3, 0xffff0000, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v22, v1, v22, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v64.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v65, v2, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v5, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v1, v21, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v2, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v7
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v65.h
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v66, v4, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v4, 0x40c00000, v7 :: v_dual_lshlrev_b32 v5, 16, v10
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 8, v21
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v24, v1, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 24, v22
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 8, v22
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v23, v1, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v67, v3, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v6, 0x40c00000, v6 :: v_dual_lshlrev_b32 v5, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v9
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v68, v1, v4 :: v_dual_add_f32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v66.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v26, v2, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v67.h
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 24, v24
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 8, v24
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 8, v23
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v25, v2, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v7, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v68.h
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v1, v6, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v81, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, 0x40c00000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v81.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v71, v1, v2, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v26
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 8, v26
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 8, v25
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v4, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v7, v4, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v14
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v28, v3, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v13
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v71.h
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v27, v2, v3 :: v_dual_add_f32 v2, 0x40c00000, v4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v1, 0x40c00000, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 24, v28
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v97, v4, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v6, v8, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v2, 0x40c00000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v33, v4, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v16
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v3, v8, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v97.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v99, v6, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 8, v28
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[27:28]
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v33.l, v99.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v32, v3, v4, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v6, v2, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v15
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[25:26]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[23:24]
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v115, v4, v6, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_dual_add_f32 v1, 0x40c00000, v5 :: v_dual_add_f32 v6, 0x40c00000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v3, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v3, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v32.l, v115.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v117, v2, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v2, v10, v6, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v4, v7, v1, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[21:22]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[19:20]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v33
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v5, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v5
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v33
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v32
|
|
; GFX11-TRUE16-NEXT: v_add3_u32 v7, v7, v5, 0x7fff
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 8, v27
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v118, v7, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v49, v4, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v117.h
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v48, v2, v3, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v118.h
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v49
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v49
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[48:49]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[30:31], 24, v[32:33]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v48
|
|
; GFX11-TRUE16-NEXT: .LBB108_4: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v53.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v17.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v18.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v55.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v19.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v131, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v54.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v52.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v65.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v21.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v129, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v5, v128, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v6, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v7, v119, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v20.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v64.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v22.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v3, v130, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v114, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v116, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v113, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v112, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v7, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v9, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v11, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v67.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v23.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v66.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v24.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v81.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v25.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v68.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v26.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v97.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v27.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v7, v103, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v8, v36, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v9, v102, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v10, v101, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v11, v100, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v98, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v96, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v87, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v10, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v14, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v71.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v28.h
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v16, 16, v15
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v115.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v32.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v99.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v33.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v118.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v48.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v117.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v49.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v86, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v85, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v84, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v30, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v82, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v80, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v69, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v17, 16, v16
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v19, 16, v18
|
|
; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v20
|
|
; GFX11-TRUE16-NEXT: s_clause 0x3
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v64i8:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB108_2
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 24, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 8, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 24, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 8, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 24, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 8, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 8, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 24, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 8, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 8, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 24, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 8, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v1
|
|
; GFX11-FAKE16-NEXT: .LBB108_2: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB108_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v17, 0x40c00000, v17 :: v_dual_add_f32 v18, 0x40c00000, v18
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v19, 0x40c00000, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v17, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v19, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v1, v1, v17, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v18, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v1, v1, v20 :: v_dual_add_f32 v2, 0x40c00000, v2
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v20, v24, v19, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v2, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v2
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v21, v2, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v21, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v2, v1, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v22, v17, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v20, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v18
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v24, 0x40c00000, v3 :: v_dual_add_f32 v21, 0x40c00000, v21
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v28, v20, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v21, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v21
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v21, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v21, v28, v20, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v3, v19, v23, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v19, v24, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v19, v19, v24, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v18, v17, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v4, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v22, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v20
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v24
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v29, v4, v3, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v20, v21, v22 :: v_dual_add_f32 v21, 0x40c00000, v23
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v21, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v19, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v21
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v21, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v19, v20, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v19
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v21, v22, v25 :: v_dual_add_f32 v6, 0x40c00000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v6, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v24, v30 :: v_dual_and_b32 v5, 0xffff0000, v5
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v5, 0x40c00000, v5 :: v_dual_lshlrev_b32 v30, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v23, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v23
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v5, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v97, v6, v21, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v31, v23, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v5, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v25, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v5, v5
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v24, 0x40c00000, v30
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 8, v97
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v22, v31, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v24, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v24
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v22, v22, v24, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v8, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v96, v5, v23, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 16, v23
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v22, v22, v31, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 8, v96
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v8, v30, v32 :: v_dual_add_f32 v25, 0x40c00000, v25
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v7, 0x40c00000, v7 :: v_dual_lshlrev_b32 v32, 16, v10
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v25, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, 0x400000, v25
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v33, v25, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v25, v30, v31 :: v_dual_and_b32 v10, 0xffff0000, v10
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v32
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v10, 0x40c00000, v10 :: v_dual_lshlrev_b32 v31, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v7, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v31
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v24, v33, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v30, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v10, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v24, v24, v30, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v85, v8, v22, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v84, v7, v25, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v24, v24, v33, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v10, v32, v34 :: v_dual_and_b32 v9, 0xffff0000, v9
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v35, v31, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v31, 0x40c00000, v34 :: v_dual_add_f32 v12, 0x40c00000, v12
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v38, v32, v33, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v9, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v33, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v83, v10, v24, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v32, v31, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v30, v35, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v33, v33, v12, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v37, v32, v34, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_add_f32 v30, 0x40c00000, v30 :: v_dual_add_f32 v11, 0x40c00000, v11
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v82, v9, v38, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 8, v83
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v30, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v30
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v33, v35 :: v_dual_lshlrev_b32 v33, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v36, v30, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v69, v12, v37, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 8, v82
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v36, v31, v32, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v34, v11, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v33
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v33, 16, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v31, v32, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v30, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v33
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v30
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v68, v11, v36, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v34, v30, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v33, v32, v33 :: v_dual_and_b32 v14, 0xffff0000, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v34, v14, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v14
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v34, v14, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v30, v32, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v65, v14, v33, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v34, v35, v31, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v35, 16, v16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 8, v65
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v34, v34, v39 :: v_dual_add_f32 v13, 0x40c00000, v13
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v30, 0x40c00000, v35
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v39, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v35, v30, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v31, v48, v13, 0x7fff
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v50, 0x400000, v15
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v31, v32, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v31, 0x40c00000, v39
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v32, v35, v30, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, 0x400000, v30
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v30, v30
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v30, v15, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v48, v31, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v49, 0x400000, v31
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v32, v32, v35, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v30, v30, v15, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v48, v48, v31, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v64, v13, v34, 0x7060302
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 8, v64
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v39, v16, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
|
|
; GFX11-FAKE16-NEXT: v_add3_u32 v35, v39, v16, 0x7fff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v39, 0x400000, v16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v35, v39, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v31, v31
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v35, v48, v49, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 16, v25
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v30, v50, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v51, v16, v32, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v32
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v50, v15, v35, 0x7060302
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v33
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 16, v34
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[50:51]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[64:65]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[68:69]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[82:83]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 16, v37
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 16, v38
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 16, v22
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[84:85]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[96:97]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v35
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 16, v36
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 16, v24
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[28:29]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[26:27]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 24, v51
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 8, v51
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 8, v50
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 24, v65
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 24, v69
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 8, v69
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 8, v68
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 24, v83
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 24, v85
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 8, v85
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v84
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 24, v97
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 24, v29
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 8, v29
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 8, v28
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v97, 24, v27
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 8, v27
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 8, v26
|
|
; GFX11-FAKE16-NEXT: .LBB108_4: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v81, v24, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v5, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v55, v22, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v28, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v67, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v11, v68, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v35, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v7, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v49, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v80, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v37, v20, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v27, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v71, v97, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v24, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v24, v66, v96, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v6, v86, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v52, v85, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v22, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v83, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v38, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v23, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v10, v70, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v36, v69, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v34, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v54, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v18, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v32, v51, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v31, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v16, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v30, v39, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v25, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v24, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v26, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v22, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v23, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
|
|
; GFX11-FAKE16-NEXT: s_clause 0x3
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[13:16], off offset:48
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v32bf16_to_v64i8_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_writelane_b32 v40, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v40, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v40, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v40, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v40, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v40, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v40, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v40, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v40, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v40, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v40, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v40, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v40, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v40, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v40, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v40, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v40, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v40, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v40, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v40, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v40, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v40, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v40, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v40, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v40, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v40, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v40, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v40, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v40, s86, 28
|
|
; SI-NEXT: v_writelane_b32 v40, s87, 29
|
|
; SI-NEXT: v_writelane_b32 v40, s96, 30
|
|
; SI-NEXT: v_writelane_b32 v40, s97, 31
|
|
; SI-NEXT: v_writelane_b32 v40, s98, 32
|
|
; SI-NEXT: v_writelane_b32 v40, s99, 33
|
|
; SI-NEXT: v_writelane_b32 v40, s30, 34
|
|
; SI-NEXT: v_writelane_b32 v40, s31, 35
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v1
|
|
; SI-NEXT: s_and_b32 s4, s29, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s5, s29, 16
|
|
; SI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s28, 16
|
|
; SI-NEXT: s_and_b32 s8, s27, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s9, s27, 16
|
|
; SI-NEXT: s_and_b32 s10, s26, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s11, s26, 16
|
|
; SI-NEXT: s_and_b32 s12, s25, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s13, s25, 16
|
|
; SI-NEXT: s_and_b32 s14, s24, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s15, s24, 16
|
|
; SI-NEXT: s_and_b32 s24, s23, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s23, s23, 16
|
|
; SI-NEXT: s_and_b32 s25, s22, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s22, s22, 16
|
|
; SI-NEXT: s_and_b32 s26, s21, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s21, s21, 16
|
|
; SI-NEXT: s_and_b32 s27, s20, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s20, s20, 16
|
|
; SI-NEXT: s_and_b32 s28, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s19, s19, 16
|
|
; SI-NEXT: s_and_b32 s29, s18, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s40, s17, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s41, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s43, s42, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s42, s42, 16
|
|
; SI-NEXT: s_and_b32 s45, s44, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s44, s44, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v3
|
|
; SI-NEXT: s_cmp_lg_u32 s46, 0
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s41
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s16
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s40
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s17
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s29
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s18
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s28
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s19
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s27
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s20
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s26
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s21
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s25
|
|
; SI-NEXT: v_mul_f32_e64 v16, 1.0, s22
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s24
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s23
|
|
; SI-NEXT: v_mul_f32_e64 v19, 1.0, s14
|
|
; SI-NEXT: v_mul_f32_e64 v20, 1.0, s15
|
|
; SI-NEXT: v_mul_f32_e64 v17, 1.0, s12
|
|
; SI-NEXT: v_mul_f32_e64 v18, 1.0, s13
|
|
; SI-NEXT: v_mul_f32_e64 v23, 1.0, s10
|
|
; SI-NEXT: v_mul_f32_e64 v24, 1.0, s11
|
|
; SI-NEXT: v_mul_f32_e64 v21, 1.0, s8
|
|
; SI-NEXT: v_mul_f32_e64 v22, 1.0, s9
|
|
; SI-NEXT: v_mul_f32_e64 v29, 1.0, s6
|
|
; SI-NEXT: v_mul_f32_e64 v31, 1.0, s7
|
|
; SI-NEXT: v_mul_f32_e64 v27, 1.0, s4
|
|
; SI-NEXT: v_mul_f32_e64 v28, 1.0, s5
|
|
; SI-NEXT: v_mul_f32_e64 v36, 1.0, s45
|
|
; SI-NEXT: v_mul_f32_e64 v37, 1.0, s44
|
|
; SI-NEXT: v_mul_f32_e64 v33, 1.0, s43
|
|
; SI-NEXT: v_mul_f32_e64 v34, 1.0, s42
|
|
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
|
|
; SI-NEXT: s_cbranch_scc0 .LBB109_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v4
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; SI-NEXT: s_lshr_b32 s73, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s72, v2
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[72:73], 16
|
|
; SI-NEXT: s_mov_b32 s75, s76
|
|
; SI-NEXT: s_lshr_b64 s[4:5], s[74:75], 24
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 0
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 1
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v7
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v8
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v5
|
|
; SI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v11
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v12
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v9
|
|
; SI-NEXT: s_lshr_b32 s45, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v15
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v16
|
|
; SI-NEXT: s_lshr_b64 s[26:27], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v13
|
|
; SI-NEXT: s_lshr_b32 s25, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v19
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v20
|
|
; SI-NEXT: s_lshr_b64 s[16:17], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v17
|
|
; SI-NEXT: s_lshr_b32 s41, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v23
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v24
|
|
; SI-NEXT: s_lshr_b64 s[20:21], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v21
|
|
; SI-NEXT: s_lshr_b32 s19, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v29
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v31
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v27
|
|
; SI-NEXT: s_lshr_b32 s11, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v36
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v37
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v33
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s24, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s40, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s18, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v28
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v34
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[58:59], 16
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[44:45], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[22:23], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b64 s[28:29], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
|
|
; SI-NEXT: s_mov_b32 s61, s62
|
|
; SI-NEXT: s_mov_b32 s47, s56
|
|
; SI-NEXT: s_mov_b32 s27, s42
|
|
; SI-NEXT: s_mov_b32 s17, s22
|
|
; SI-NEXT: s_mov_b32 s21, s28
|
|
; SI-NEXT: s_mov_b32 s13, s14
|
|
; SI-NEXT: s_mov_b32 s7, s8
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[74:75], 16
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[74:75], 8
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[60:61], 24
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[60:61], 16
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[60:61], 8
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[46:47], 24
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[46:47], 16
|
|
; SI-NEXT: s_lshr_b64 s[38:39], s[46:47], 8
|
|
; SI-NEXT: s_lshr_b64 s[48:49], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[50:51], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[52:53], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[64:65], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[66:67], s[16:17], 8
|
|
; SI-NEXT: s_lshr_b64 s[68:69], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[80:81], s[20:21], 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 24, v5
|
|
; SI-NEXT: s_lshr_b32 s23, s76, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v9
|
|
; SI-NEXT: s_lshr_b32 s21, s62, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 24, v13
|
|
; SI-NEXT: s_lshr_b32 s18, s56, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v17
|
|
; SI-NEXT: s_lshr_b32 s17, s42, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 24, v21
|
|
; SI-NEXT: s_lshr_b32 s15, s22, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v27
|
|
; SI-NEXT: s_lshr_b32 s10, s28, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v33
|
|
; SI-NEXT: s_lshr_b32 s9, s14, 8
|
|
; SI-NEXT: s_lshr_b32 s4, s8, 8
|
|
; SI-NEXT: s_lshr_b64 s[96:97], s[12:13], 24
|
|
; SI-NEXT: s_lshr_b64 s[98:99], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[12:13], 8
|
|
; SI-NEXT: s_lshr_b64 s[82:83], s[6:7], 24
|
|
; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[86:87], s[6:7], 8
|
|
; SI-NEXT: s_cbranch_execnz .LBB109_3
|
|
; SI-NEXT: .LBB109_2: ; %cmp.true
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v36
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v37
|
|
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
|
|
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v26
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v25
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v34
|
|
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v25
|
|
; SI-NEXT: v_and_b32_e32 v25, 0xffff0000, v33
|
|
; SI-NEXT: v_add_f32_e32 v25, 0x40c00000, v25
|
|
; SI-NEXT: s_lshr_b64 s[6:7], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v25
|
|
; SI-NEXT: s_lshr_b32 s5, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v26
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v31
|
|
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
|
|
; SI-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v26
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v28
|
|
; SI-NEXT: v_add_f32_e32 v29, 0x40c00000, v29
|
|
; SI-NEXT: v_add_f32_e32 v28, 0x40c00000, v26
|
|
; SI-NEXT: v_and_b32_e32 v26, 0xffff0000, v27
|
|
; SI-NEXT: s_lshr_b64 s[8:9], s[4:5], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v29
|
|
; SI-NEXT: v_add_f32_e32 v26, 0x40c00000, v26
|
|
; SI-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
|
|
; SI-NEXT: s_lshr_b32 s11, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v26
|
|
; SI-NEXT: v_add_f32_e32 v23, 0x40c00000, v23
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
|
|
; SI-NEXT: s_lshr_b64 s[12:13], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b32 s11, s4, 16
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v23
|
|
; SI-NEXT: v_add_f32_e32 v21, 0x40c00000, v21
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
|
|
; SI-NEXT: v_add_f32_e32 v24, 0x40c00000, v24
|
|
; SI-NEXT: s_lshr_b32 s17, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v21
|
|
; SI-NEXT: v_add_f32_e32 v19, 0x40c00000, v19
|
|
; SI-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
|
|
; SI-NEXT: v_readfirstlane_b32 s16, v24
|
|
; SI-NEXT: s_lshr_b32 s19, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v19
|
|
; SI-NEXT: v_add_f32_e32 v17, 0x40c00000, v17
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
|
|
; SI-NEXT: s_lshr_b64 s[20:21], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b32 s17, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v17
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
|
|
; SI-NEXT: v_add_f32_e32 v15, 0x40c00000, v15
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
|
|
; SI-NEXT: s_lshr_b32 s41, s4, 16
|
|
; SI-NEXT: v_add_f32_e32 v16, 0x40c00000, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v15
|
|
; SI-NEXT: v_add_f32_e32 v13, 0x40c00000, v13
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
|
|
; SI-NEXT: s_lshr_b32 s25, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s24, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v13
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
|
|
; SI-NEXT: v_add_f32_e32 v11, 0x40c00000, v11
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
|
|
; SI-NEXT: s_lshr_b64 s[26:27], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b32 s25, s4, 16
|
|
; SI-NEXT: v_add_f32_e32 v12, 0x40c00000, v12
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v11
|
|
; SI-NEXT: v_add_f32_e32 v9, 0x40c00000, v9
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
|
|
; SI-NEXT: s_lshr_b32 s45, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v12
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v9
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
|
|
; SI-NEXT: v_add_f32_e32 v7, 0x40c00000, v7
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
|
|
; SI-NEXT: s_lshr_b64 s[46:47], s[44:45], 16
|
|
; SI-NEXT: s_lshr_b32 s45, s4, 16
|
|
; SI-NEXT: v_add_f32_e32 v8, 0x40c00000, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v7
|
|
; SI-NEXT: v_add_f32_e32 v5, 0x40c00000, v5
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
|
|
; SI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v5
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
|
|
; SI-NEXT: v_add_f32_e32 v3, 0x40c00000, v3
|
|
; SI-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
|
|
; SI-NEXT: s_lshr_b64 s[60:61], s[58:59], 16
|
|
; SI-NEXT: s_lshr_b32 s59, s4, 16
|
|
; SI-NEXT: v_add_f32_e32 v4, 0x40c00000, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
|
|
; SI-NEXT: v_add_f32_e32 v1, 0x40c00000, v1
|
|
; SI-NEXT: s_lshr_b32 s73, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s72, v4
|
|
; SI-NEXT: v_add_f32_e32 v2, 0x40c00000, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; SI-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
|
|
; SI-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
|
|
; SI-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
|
|
; SI-NEXT: s_lshr_b64 s[74:75], s[72:73], 16
|
|
; SI-NEXT: s_lshr_b32 s73, s4, 16
|
|
; SI-NEXT: v_readfirstlane_b32 s72, v2
|
|
; SI-NEXT: v_add_f32_e32 v22, 0x40c00000, v22
|
|
; SI-NEXT: v_add_f32_e32 v20, 0x40c00000, v20
|
|
; SI-NEXT: v_add_f32_e32 v18, 0x40c00000, v18
|
|
; SI-NEXT: v_add_f32_e32 v14, 0x40c00000, v14
|
|
; SI-NEXT: v_add_f32_e32 v10, 0x40c00000, v10
|
|
; SI-NEXT: v_add_f32_e32 v6, 0x40c00000, v6
|
|
; SI-NEXT: s_lshr_b64 s[76:77], s[72:73], 16
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v28
|
|
; SI-NEXT: v_readfirstlane_b32 s18, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s16, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s40, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s24, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v6
|
|
; SI-NEXT: s_mov_b32 s75, s76
|
|
; SI-NEXT: s_lshr_b64 s[14:15], s[10:11], 16
|
|
; SI-NEXT: s_lshr_b64 s[28:29], s[18:19], 16
|
|
; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[22:23], s[40:41], 16
|
|
; SI-NEXT: s_lshr_b64 s[42:43], s[24:25], 16
|
|
; SI-NEXT: s_lshr_b64 s[56:57], s[44:45], 16
|
|
; SI-NEXT: s_lshr_b64 s[62:63], s[58:59], 16
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[74:75], 24
|
|
; SI-NEXT: s_mov_b32 s7, s8
|
|
; SI-NEXT: s_mov_b32 s13, s14
|
|
; SI-NEXT: s_mov_b32 s21, s28
|
|
; SI-NEXT: s_mov_b32 s17, s22
|
|
; SI-NEXT: s_mov_b32 s27, s42
|
|
; SI-NEXT: s_mov_b32 s47, s56
|
|
; SI-NEXT: s_mov_b32 s61, s62
|
|
; SI-NEXT: v_writelane_b32 v41, s78, 0
|
|
; SI-NEXT: v_writelane_b32 v41, s79, 1
|
|
; SI-NEXT: s_lshr_b64 s[88:89], s[74:75], 16
|
|
; SI-NEXT: s_lshr_b64 s[92:93], s[74:75], 8
|
|
; SI-NEXT: s_lshr_b64 s[90:91], s[60:61], 24
|
|
; SI-NEXT: s_lshr_b64 s[94:95], s[60:61], 16
|
|
; SI-NEXT: s_lshr_b64 s[30:31], s[60:61], 8
|
|
; SI-NEXT: s_lshr_b64 s[34:35], s[46:47], 24
|
|
; SI-NEXT: s_lshr_b64 s[36:37], s[46:47], 16
|
|
; SI-NEXT: s_lshr_b64 s[38:39], s[46:47], 8
|
|
; SI-NEXT: s_lshr_b64 s[48:49], s[26:27], 24
|
|
; SI-NEXT: s_lshr_b64 s[50:51], s[26:27], 16
|
|
; SI-NEXT: s_lshr_b64 s[52:53], s[26:27], 8
|
|
; SI-NEXT: s_lshr_b64 s[54:55], s[16:17], 24
|
|
; SI-NEXT: s_lshr_b64 s[64:65], s[16:17], 16
|
|
; SI-NEXT: s_lshr_b64 s[66:67], s[16:17], 8
|
|
; SI-NEXT: s_lshr_b64 s[68:69], s[20:21], 24
|
|
; SI-NEXT: s_lshr_b64 s[70:71], s[20:21], 16
|
|
; SI-NEXT: s_lshr_b64 s[80:81], s[20:21], 8
|
|
; SI-NEXT: s_lshr_b32 s23, s76, 8
|
|
; SI-NEXT: s_lshr_b32 s21, s62, 8
|
|
; SI-NEXT: s_lshr_b32 s18, s56, 8
|
|
; SI-NEXT: s_lshr_b32 s17, s42, 8
|
|
; SI-NEXT: s_lshr_b32 s15, s22, 8
|
|
; SI-NEXT: s_lshr_b32 s10, s28, 8
|
|
; SI-NEXT: s_lshr_b32 s9, s14, 8
|
|
; SI-NEXT: s_lshr_b32 s4, s8, 8
|
|
; SI-NEXT: v_lshrrev_b32_e32 v48, 24, v1
|
|
; SI-NEXT: v_lshrrev_b32_e32 v39, 24, v5
|
|
; SI-NEXT: v_lshrrev_b32_e32 v38, 24, v9
|
|
; SI-NEXT: v_lshrrev_b32_e32 v35, 24, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v32, 24, v17
|
|
; SI-NEXT: v_lshrrev_b32_e32 v30, 24, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v26, 24, v26
|
|
; SI-NEXT: v_lshrrev_b32_e32 v25, 24, v25
|
|
; SI-NEXT: s_lshr_b64 s[96:97], s[12:13], 24
|
|
; SI-NEXT: s_lshr_b64 s[98:99], s[12:13], 16
|
|
; SI-NEXT: s_lshr_b64 s[78:79], s[12:13], 8
|
|
; SI-NEXT: s_lshr_b64 s[82:83], s[6:7], 24
|
|
; SI-NEXT: s_lshr_b64 s[84:85], s[6:7], 16
|
|
; SI-NEXT: s_lshr_b64 s[86:87], s[6:7], 8
|
|
; SI-NEXT: .LBB109_3: ; %end
|
|
; SI-NEXT: s_and_b32 s7, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s92, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s88, 0xff
|
|
; SI-NEXT: v_readlane_b32 s74, v41, 0
|
|
; SI-NEXT: s_lshl_b32 s24, s74, 24
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_or_b32 s13, s24, s13
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: v_mov_b32_e32 v1, s7
|
|
; SI-NEXT: s_and_b32 s7, s76, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s23, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s73, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 24, v48
|
|
; SI-NEXT: v_or_b32_e32 v2, s13, v2
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v1, s7, v2
|
|
; SI-NEXT: s_and_b32 s7, s60, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s30, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s94, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_lshl_b32 s23, s90, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s13, s23, s13
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 4, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s62, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s21, 8
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 8, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s59, 0xff
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v39
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v1, s13, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, s7, v1
|
|
; SI-NEXT: s_and_b32 s7, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s38, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s36, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_lshl_b32 s21, s34, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s13, s21, s13
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 12, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s56, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s18, 8
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 16, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s45, 0xff
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v38
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v1, s13, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, s7, v1
|
|
; SI-NEXT: s_and_b32 s7, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s52, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s50, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_lshl_b32 s18, s48, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s13, s18, s13
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 20, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s17, 8
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 24, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s25, 0xff
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v35
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v1, s13, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, s7, v1
|
|
; SI-NEXT: s_and_b32 s7, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s66, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s64, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_lshl_b32 s16, s54, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s13, s16, s13
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 28, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s22, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s15, 8
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 32, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s41, 0xff
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v32
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v1, s13, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, s7, v1
|
|
; SI-NEXT: s_and_b32 s7, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s80, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_and_b32 s13, s70, 0xff
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_lshl_b32 s15, s68, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s13, s15, s13
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 36, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 8
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 40, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s10
|
|
; SI-NEXT: s_and_b32 s10, s19, 0xff
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v30
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v1, s10, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, s7, v1
|
|
; SI-NEXT: s_and_b32 s7, s12, 0xff
|
|
; SI-NEXT: s_lshl_b32 s10, s78, 8
|
|
; SI-NEXT: s_or_b32 s7, s7, s10
|
|
; SI-NEXT: s_and_b32 s10, s98, 0xff
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_lshl_b32 s12, s96, 24
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s10, s12, s10
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 44, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s10
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: v_mov_b32_e32 v2, s7
|
|
; SI-NEXT: s_and_b32 s7, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 8
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 48, v0
|
|
; SI-NEXT: s_or_b32 s7, s7, s9
|
|
; SI-NEXT: s_and_b32 s9, s11, 0xff
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v26
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v1, s9, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, s7, v1
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s86, 8
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: s_and_b32 s7, s84, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s9, s82, 24
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s9, s7
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 52, v0
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, 56, v0
|
|
; SI-NEXT: v_mov_b32_e32 v2, s6
|
|
; SI-NEXT: s_and_b32 s6, s8, 0xff
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 8
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xff
|
|
; SI-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen
|
|
; SI-NEXT: s_or_b32 s4, s6, s4
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v25
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: v_or_b32_e32 v1, s5, v1
|
|
; SI-NEXT: v_or_b32_e32 v1, s4, v1
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, 60, v0
|
|
; SI-NEXT: v_readlane_b32 s30, v40, 34
|
|
; SI-NEXT: v_readlane_b32 s75, v41, 1
|
|
; SI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; SI-NEXT: v_readlane_b32 s31, v40, 35
|
|
; SI-NEXT: v_readlane_b32 s99, v40, 33
|
|
; SI-NEXT: v_readlane_b32 s98, v40, 32
|
|
; SI-NEXT: v_readlane_b32 s97, v40, 31
|
|
; SI-NEXT: v_readlane_b32 s96, v40, 30
|
|
; SI-NEXT: v_readlane_b32 s87, v40, 29
|
|
; SI-NEXT: v_readlane_b32 s86, v40, 28
|
|
; SI-NEXT: v_readlane_b32 s85, v40, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v40, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v40, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v40, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v40, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v40, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v40, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v40, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v40, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v40, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v40, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v40, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v40, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v40, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v40, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v40, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v40, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v40, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v40, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v40, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v40, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v40, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v40, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v40, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v40, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v40, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v40, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v40, 0
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB109_4:
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v41, s4, 0
|
|
; SI-NEXT: ; implicit-def: $sgpr74
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: v_writelane_b32 v41, s5, 1
|
|
; SI-NEXT: ; implicit-def: $sgpr76
|
|
; SI-NEXT: ; implicit-def: $sgpr23
|
|
; SI-NEXT: ; implicit-def: $sgpr73
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: ; implicit-def: $sgpr60
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr90
|
|
; SI-NEXT: ; implicit-def: $sgpr62
|
|
; SI-NEXT: ; implicit-def: $sgpr21
|
|
; SI-NEXT: ; implicit-def: $sgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $sgpr46
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr36
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr56
|
|
; SI-NEXT: ; implicit-def: $sgpr18
|
|
; SI-NEXT: ; implicit-def: $sgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr26
|
|
; SI-NEXT: ; implicit-def: $sgpr52
|
|
; SI-NEXT: ; implicit-def: $sgpr50
|
|
; SI-NEXT: ; implicit-def: $sgpr48
|
|
; SI-NEXT: ; implicit-def: $sgpr42
|
|
; SI-NEXT: ; implicit-def: $sgpr17
|
|
; SI-NEXT: ; implicit-def: $sgpr25
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $sgpr16
|
|
; SI-NEXT: ; implicit-def: $sgpr66
|
|
; SI-NEXT: ; implicit-def: $sgpr64
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr22
|
|
; SI-NEXT: ; implicit-def: $sgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $sgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $sgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $sgpr4
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: ; implicit-def: $sgpr41
|
|
; SI-NEXT: ; implicit-def: $sgpr20
|
|
; SI-NEXT: ; implicit-def: $sgpr80
|
|
; SI-NEXT: ; implicit-def: $sgpr70
|
|
; SI-NEXT: ; implicit-def: $sgpr68
|
|
; SI-NEXT: ; implicit-def: $sgpr28
|
|
; SI-NEXT: ; implicit-def: $sgpr19
|
|
; SI-NEXT: ; implicit-def: $sgpr12
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr98
|
|
; SI-NEXT: ; implicit-def: $sgpr96
|
|
; SI-NEXT: ; implicit-def: $sgpr14
|
|
; SI-NEXT: ; implicit-def: $sgpr11
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr86
|
|
; SI-NEXT: ; implicit-def: $sgpr84
|
|
; SI-NEXT: ; implicit-def: $sgpr82
|
|
; SI-NEXT: ; implicit-def: $sgpr8
|
|
; SI-NEXT: ; implicit-def: $sgpr5
|
|
; SI-NEXT: s_branch .LBB109_2
|
|
;
|
|
; VI-LABEL: bitcast_v32bf16_to_v64i8_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_writelane_b32 v63, s34, 0
|
|
; VI-NEXT: v_writelane_b32 v63, s35, 1
|
|
; VI-NEXT: v_writelane_b32 v63, s36, 2
|
|
; VI-NEXT: v_writelane_b32 v63, s37, 3
|
|
; VI-NEXT: v_writelane_b32 v63, s38, 4
|
|
; VI-NEXT: v_writelane_b32 v63, s39, 5
|
|
; VI-NEXT: v_writelane_b32 v63, s48, 6
|
|
; VI-NEXT: v_writelane_b32 v63, s49, 7
|
|
; VI-NEXT: v_writelane_b32 v63, s50, 8
|
|
; VI-NEXT: v_writelane_b32 v63, s51, 9
|
|
; VI-NEXT: v_writelane_b32 v63, s52, 10
|
|
; VI-NEXT: v_writelane_b32 v63, s53, 11
|
|
; VI-NEXT: v_writelane_b32 v63, s54, 12
|
|
; VI-NEXT: v_writelane_b32 v63, s55, 13
|
|
; VI-NEXT: v_writelane_b32 v63, s64, 14
|
|
; VI-NEXT: v_writelane_b32 v63, s65, 15
|
|
; VI-NEXT: v_writelane_b32 v63, s66, 16
|
|
; VI-NEXT: v_writelane_b32 v63, s67, 17
|
|
; VI-NEXT: v_writelane_b32 v63, s30, 18
|
|
; VI-NEXT: v_writelane_b32 v63, s31, 19
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s5, v2
|
|
; VI-NEXT: s_cmp_lg_u32 s4, 0
|
|
; VI-NEXT: v_readfirstlane_b32 s4, v1
|
|
; VI-NEXT: s_cbranch_scc0 .LBB109_3
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: s_lshr_b32 s65, s5, 24
|
|
; VI-NEXT: s_lshr_b32 s64, s5, 16
|
|
; VI-NEXT: s_lshr_b32 s55, s5, 8
|
|
; VI-NEXT: s_lshr_b32 s67, s4, 16
|
|
; VI-NEXT: s_lshr_b32 s66, s4, 8
|
|
; VI-NEXT: s_lshr_b32 s52, s29, 24
|
|
; VI-NEXT: s_lshr_b32 s51, s29, 16
|
|
; VI-NEXT: s_lshr_b32 s50, s29, 8
|
|
; VI-NEXT: s_lshr_b32 s54, s28, 16
|
|
; VI-NEXT: s_lshr_b32 s53, s28, 8
|
|
; VI-NEXT: s_lshr_b32 s39, s27, 24
|
|
; VI-NEXT: s_lshr_b32 s38, s27, 16
|
|
; VI-NEXT: s_lshr_b32 s37, s27, 8
|
|
; VI-NEXT: s_lshr_b32 s49, s26, 16
|
|
; VI-NEXT: s_lshr_b32 s48, s26, 8
|
|
; VI-NEXT: s_lshr_b32 s34, s25, 24
|
|
; VI-NEXT: s_lshr_b32 s31, s25, 16
|
|
; VI-NEXT: s_lshr_b32 s30, s25, 8
|
|
; VI-NEXT: s_lshr_b32 s36, s24, 16
|
|
; VI-NEXT: s_lshr_b32 s35, s24, 8
|
|
; VI-NEXT: s_lshr_b32 s89, s23, 24
|
|
; VI-NEXT: s_lshr_b32 s88, s23, 16
|
|
; VI-NEXT: s_lshr_b32 s79, s23, 8
|
|
; VI-NEXT: s_lshr_b32 s91, s22, 16
|
|
; VI-NEXT: s_lshr_b32 s90, s22, 8
|
|
; VI-NEXT: s_lshr_b32 s76, s21, 24
|
|
; VI-NEXT: s_lshr_b32 s75, s21, 16
|
|
; VI-NEXT: s_lshr_b32 s74, s21, 8
|
|
; VI-NEXT: s_lshr_b32 s78, s20, 16
|
|
; VI-NEXT: s_lshr_b32 s77, s20, 8
|
|
; VI-NEXT: s_lshr_b32 s63, s19, 24
|
|
; VI-NEXT: s_lshr_b32 s62, s19, 16
|
|
; VI-NEXT: s_lshr_b32 s61, s19, 8
|
|
; VI-NEXT: s_lshr_b32 s73, s18, 16
|
|
; VI-NEXT: s_lshr_b32 s72, s18, 8
|
|
; VI-NEXT: s_lshr_b32 s58, s17, 24
|
|
; VI-NEXT: s_lshr_b32 s57, s17, 16
|
|
; VI-NEXT: s_lshr_b32 s56, s17, 8
|
|
; VI-NEXT: s_lshr_b32 s60, s16, 16
|
|
; VI-NEXT: s_lshr_b32 s59, s16, 8
|
|
; VI-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; VI-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; VI-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; VI-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; VI-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; VI-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; VI-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; VI-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; VI-NEXT: s_cbranch_execnz .LBB109_4
|
|
; VI-NEXT: .LBB109_2: ; %cmp.true
|
|
; VI-NEXT: s_lshl_b32 s6, s17, 16
|
|
; VI-NEXT: v_mov_b32_e32 v24, 0x40c00000
|
|
; VI-NEXT: v_add_f32_e32 v1, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x7fff, v2
|
|
; VI-NEXT: v_or_b32_e32 v3, 0x400000, v1
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; VI-NEXT: s_and_b32 s6, s17, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_lshrrev_b64 v[1:2], 16, v[1:2]
|
|
; VI-NEXT: s_lshl_b32 s6, s16, 16
|
|
; VI-NEXT: v_add_f32_e32 v2, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, v3, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x7fff, v3
|
|
; VI-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; VI-NEXT: s_and_b32 s6, s16, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; VI-NEXT: v_add_f32_e32 v3, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v4, v3, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v3
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x7fff, v4
|
|
; VI-NEXT: v_or_b32_e32 v5, 0x400000, v3
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
|
|
; VI-NEXT: s_lshl_b32 s6, s19, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
|
|
; VI-NEXT: v_add_f32_e32 v4, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v5, v4, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v4
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x7fff, v5
|
|
; VI-NEXT: v_or_b32_e32 v6, 0x400000, v4
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
|
|
; VI-NEXT: s_and_b32 s6, s19, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_lshrrev_b64 v[4:5], 16, v[4:5]
|
|
; VI-NEXT: s_lshl_b32 s6, s18, 16
|
|
; VI-NEXT: v_add_f32_e32 v5, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v6, v5, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x7fff, v6
|
|
; VI-NEXT: v_or_b32_e32 v7, 0x400000, v5
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
|
|
; VI-NEXT: s_and_b32 s6, s18, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
|
|
; VI-NEXT: v_add_f32_e32 v6, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v7, v6, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v6
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x7fff, v7
|
|
; VI-NEXT: v_or_b32_e32 v8, 0x400000, v6
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v6, v6
|
|
; VI-NEXT: s_lshl_b32 s6, s21, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc
|
|
; VI-NEXT: v_add_f32_e32 v7, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v8, v7, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, v8, v7
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x7fff, v8
|
|
; VI-NEXT: v_or_b32_e32 v9, 0x400000, v7
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
|
|
; VI-NEXT: s_and_b32 s6, s21, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
|
|
; VI-NEXT: v_add_f32_e32 v8, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_lshrrev_b64 v[7:8], 16, v[7:8]
|
|
; VI-NEXT: s_lshl_b32 s6, s20, 16
|
|
; VI-NEXT: v_add_f32_e32 v8, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v9, v8, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, v9, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x7fff, v9
|
|
; VI-NEXT: v_or_b32_e32 v10, 0x400000, v8
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v8, v8
|
|
; VI-NEXT: s_and_b32 s6, s20, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v10, vcc
|
|
; VI-NEXT: v_add_f32_e32 v9, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v10, v9, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, v10, v9
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x7fff, v10
|
|
; VI-NEXT: v_or_b32_e32 v11, 0x400000, v9
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
|
|
; VI-NEXT: s_lshl_b32 s6, s23, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
|
|
; VI-NEXT: v_add_f32_e32 v10, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v11, v10, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, v11, v10
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x7fff, v11
|
|
; VI-NEXT: v_or_b32_e32 v12, 0x400000, v10
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v10, v10
|
|
; VI-NEXT: s_and_b32 s6, s23, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v10, v11, v12, vcc
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_lshrrev_b64 v[10:11], 16, v[10:11]
|
|
; VI-NEXT: s_lshl_b32 s6, s22, 16
|
|
; VI-NEXT: v_add_f32_e32 v11, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v12, v11, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, v12, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x7fff, v12
|
|
; VI-NEXT: v_or_b32_e32 v13, 0x400000, v11
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
|
|
; VI-NEXT: s_and_b32 s6, s22, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v11, v12, v13, vcc
|
|
; VI-NEXT: v_add_f32_e32 v12, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v13, v12, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, v13, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x7fff, v13
|
|
; VI-NEXT: v_or_b32_e32 v14, 0x400000, v12
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v12, v12
|
|
; VI-NEXT: s_lshl_b32 s6, s25, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v12, v13, v14, vcc
|
|
; VI-NEXT: v_add_f32_e32 v13, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v14, v13, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, v14, v13
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x7fff, v14
|
|
; VI-NEXT: v_or_b32_e32 v15, 0x400000, v13
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v13, v13
|
|
; VI-NEXT: s_and_b32 s6, s25, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v13, v14, v15, vcc
|
|
; VI-NEXT: v_add_f32_e32 v14, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_lshrrev_b64 v[13:14], 16, v[13:14]
|
|
; VI-NEXT: s_lshl_b32 s6, s24, 16
|
|
; VI-NEXT: v_add_f32_e32 v14, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v15, v14, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, v15, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x7fff, v15
|
|
; VI-NEXT: v_or_b32_e32 v16, 0x400000, v14
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v14, v14
|
|
; VI-NEXT: s_and_b32 s6, s24, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v14, v15, v16, vcc
|
|
; VI-NEXT: v_add_f32_e32 v15, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v16, v15, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, v16, v15
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x7fff, v16
|
|
; VI-NEXT: v_or_b32_e32 v17, 0x400000, v15
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v15, v15
|
|
; VI-NEXT: s_lshl_b32 s6, s27, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v15, v16, v17, vcc
|
|
; VI-NEXT: v_add_f32_e32 v16, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v17, v16, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, v17, v16
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x7fff, v17
|
|
; VI-NEXT: v_or_b32_e32 v18, 0x400000, v16
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v16, v16
|
|
; VI-NEXT: s_and_b32 s6, s27, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v16, v17, v18, vcc
|
|
; VI-NEXT: v_add_f32_e32 v17, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v17, 16, v17
|
|
; VI-NEXT: v_lshrrev_b64 v[16:17], 16, v[16:17]
|
|
; VI-NEXT: s_lshl_b32 s6, s26, 16
|
|
; VI-NEXT: v_add_f32_e32 v17, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v18, v17, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, v18, v17
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x7fff, v18
|
|
; VI-NEXT: v_or_b32_e32 v19, 0x400000, v17
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v17, v17
|
|
; VI-NEXT: s_and_b32 s6, s26, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v17, v18, v19, vcc
|
|
; VI-NEXT: v_add_f32_e32 v18, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v19, v18, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, v19, v18
|
|
; VI-NEXT: v_add_u32_e32 v19, vcc, 0x7fff, v19
|
|
; VI-NEXT: v_or_b32_e32 v20, 0x400000, v18
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v18, v18
|
|
; VI-NEXT: s_lshl_b32 s6, s29, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v18, v19, v20, vcc
|
|
; VI-NEXT: v_add_f32_e32 v19, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v20, v19, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, v20, v19
|
|
; VI-NEXT: v_add_u32_e32 v20, vcc, 0x7fff, v20
|
|
; VI-NEXT: v_or_b32_e32 v21, 0x400000, v19
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v19, v19
|
|
; VI-NEXT: s_and_b32 s6, s29, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v19, v20, v21, vcc
|
|
; VI-NEXT: v_add_f32_e32 v20, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
|
|
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v20
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
|
|
; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v20, 16, v20
|
|
; VI-NEXT: v_lshrrev_b64 v[19:20], 16, v[19:20]
|
|
; VI-NEXT: s_lshl_b32 s6, s28, 16
|
|
; VI-NEXT: v_add_f32_e32 v20, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v21, v20, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, v21, v20
|
|
; VI-NEXT: v_add_u32_e32 v21, vcc, 0x7fff, v21
|
|
; VI-NEXT: v_or_b32_e32 v22, 0x400000, v20
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v20, v20
|
|
; VI-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v20, v21, v22, vcc
|
|
; VI-NEXT: v_add_f32_e32 v21, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v22, v21, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, v22, v21
|
|
; VI-NEXT: v_add_u32_e32 v22, vcc, 0x7fff, v22
|
|
; VI-NEXT: v_or_b32_e32 v23, 0x400000, v21
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v21, v21
|
|
; VI-NEXT: s_lshl_b32 s6, s5, 16
|
|
; VI-NEXT: v_cndmask_b32_e32 v21, v22, v23, vcc
|
|
; VI-NEXT: v_add_f32_e32 v22, s6, v24
|
|
; VI-NEXT: v_bfe_u32 v23, v22, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, v23, v22
|
|
; VI-NEXT: v_add_u32_e32 v23, vcc, 0x7fff, v23
|
|
; VI-NEXT: v_or_b32_e32 v25, 0x400000, v22
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v22, v22
|
|
; VI-NEXT: s_and_b32 s5, s5, 0xffff0000
|
|
; VI-NEXT: v_cndmask_b32_e32 v22, v23, v25, vcc
|
|
; VI-NEXT: v_add_f32_e32 v23, s5, v24
|
|
; VI-NEXT: v_bfe_u32 v25, v23, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v23
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
|
|
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v23
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
|
|
; VI-NEXT: v_cndmask_b32_e32 v23, v25, v26, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v23, 16, v23
|
|
; VI-NEXT: v_lshrrev_b64 v[22:23], 16, v[22:23]
|
|
; VI-NEXT: s_lshl_b32 s5, s4, 16
|
|
; VI-NEXT: v_add_f32_e32 v23, s5, v24
|
|
; VI-NEXT: v_bfe_u32 v25, v23, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v23
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
|
|
; VI-NEXT: s_and_b32 s4, s4, 0xffff0000
|
|
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v23
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v23, v23
|
|
; VI-NEXT: v_add_f32_e32 v24, s4, v24
|
|
; VI-NEXT: v_cndmask_b32_e32 v23, v25, v26, vcc
|
|
; VI-NEXT: v_bfe_u32 v25, v24, 16, 1
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, v25, v24
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x7fff, v25
|
|
; VI-NEXT: v_or_b32_e32 v26, 0x400000, v24
|
|
; VI-NEXT: v_cmp_u_f32_e32 vcc, v24, v24
|
|
; VI-NEXT: v_cndmask_b32_e32 v24, v25, v26, vcc
|
|
; VI-NEXT: v_lshrrev_b32_e32 v24, 16, v24
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v21
|
|
; VI-NEXT: v_lshrrev_b64 v[23:24], 16, v[23:24]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 16, v18
|
|
; VI-NEXT: v_lshrrev_b64 v[20:21], 16, v[20:21]
|
|
; VI-NEXT: v_mov_b32_e32 v24, v22
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_lshrrev_b64 v[17:18], 16, v[17:18]
|
|
; VI-NEXT: v_mov_b32_e32 v21, v19
|
|
; VI-NEXT: v_lshrrev_b64 v[24:25], 24, v[23:24]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_lshrrev_b64 v[14:15], 16, v[14:15]
|
|
; VI-NEXT: v_mov_b32_e32 v18, v16
|
|
; VI-NEXT: v_lshrrev_b64 v[25:26], 24, v[20:21]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_lshrrev_b64 v[11:12], 16, v[11:12]
|
|
; VI-NEXT: v_mov_b32_e32 v15, v13
|
|
; VI-NEXT: v_lshrrev_b64 v[26:27], 24, v[17:18]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_lshrrev_b64 v[8:9], 16, v[8:9]
|
|
; VI-NEXT: v_mov_b32_e32 v12, v10
|
|
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[14:15]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_lshrrev_b64 v[5:6], 16, v[5:6]
|
|
; VI-NEXT: v_mov_b32_e32 v9, v7
|
|
; VI-NEXT: v_lshrrev_b64 v[28:29], 24, v[11:12]
|
|
; VI-NEXT: v_lshrrev_b64 v[2:3], 16, v[2:3]
|
|
; VI-NEXT: v_mov_b32_e32 v6, v4
|
|
; VI-NEXT: v_lshrrev_b64 v[29:30], 24, v[8:9]
|
|
; VI-NEXT: v_mov_b32_e32 v3, v1
|
|
; VI-NEXT: v_lshrrev_b64 v[30:31], 24, v[5:6]
|
|
; VI-NEXT: v_lshrrev_b64 v[31:32], 24, v[2:3]
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 24, v22
|
|
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v22
|
|
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v22
|
|
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v23
|
|
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v23
|
|
; VI-NEXT: v_lshrrev_b32_e32 v18, 24, v19
|
|
; VI-NEXT: v_lshrrev_b32_e32 v21, 16, v19
|
|
; VI-NEXT: v_lshrrev_b32_e32 v32, 8, v19
|
|
; VI-NEXT: v_lshrrev_b32_e32 v33, 16, v20
|
|
; VI-NEXT: v_lshrrev_b32_e32 v34, 8, v20
|
|
; VI-NEXT: v_lshrrev_b32_e32 v35, 24, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v36, 16, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v37, 8, v16
|
|
; VI-NEXT: v_lshrrev_b32_e32 v38, 16, v17
|
|
; VI-NEXT: v_lshrrev_b32_e32 v39, 8, v17
|
|
; VI-NEXT: v_lshrrev_b32_e32 v48, 24, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v49, 16, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v50, 8, v13
|
|
; VI-NEXT: v_lshrrev_b32_e32 v51, 16, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v52, 8, v14
|
|
; VI-NEXT: v_lshrrev_b32_e32 v53, 24, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v54, 16, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v10
|
|
; VI-NEXT: v_lshrrev_b32_e32 v40, 16, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v11
|
|
; VI-NEXT: v_lshrrev_b32_e32 v42, 24, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v43, 16, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v7
|
|
; VI-NEXT: v_lshrrev_b32_e32 v45, 16, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v8
|
|
; VI-NEXT: v_lshrrev_b32_e32 v47, 24, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v56, 16, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v4
|
|
; VI-NEXT: v_lshrrev_b32_e32 v58, 16, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v59, 8, v5
|
|
; VI-NEXT: v_lshrrev_b32_e32 v60, 24, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v61, 16, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v62, 8, v1
|
|
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v2
|
|
; VI-NEXT: s_branch .LBB109_5
|
|
; VI-NEXT: .LBB109_3:
|
|
; VI-NEXT: ; implicit-def: $sgpr59
|
|
; VI-NEXT: ; implicit-def: $sgpr60
|
|
; VI-NEXT: ; implicit-def: $sgpr6
|
|
; VI-NEXT: ; implicit-def: $sgpr56
|
|
; VI-NEXT: ; implicit-def: $sgpr57
|
|
; VI-NEXT: ; implicit-def: $sgpr58
|
|
; VI-NEXT: ; implicit-def: $sgpr72
|
|
; VI-NEXT: ; implicit-def: $sgpr73
|
|
; VI-NEXT: ; implicit-def: $sgpr8
|
|
; VI-NEXT: ; implicit-def: $sgpr61
|
|
; VI-NEXT: ; implicit-def: $sgpr62
|
|
; VI-NEXT: ; implicit-def: $sgpr63
|
|
; VI-NEXT: ; implicit-def: $sgpr77
|
|
; VI-NEXT: ; implicit-def: $sgpr78
|
|
; VI-NEXT: ; implicit-def: $sgpr10
|
|
; VI-NEXT: ; implicit-def: $sgpr74
|
|
; VI-NEXT: ; implicit-def: $sgpr75
|
|
; VI-NEXT: ; implicit-def: $sgpr76
|
|
; VI-NEXT: ; implicit-def: $sgpr90
|
|
; VI-NEXT: ; implicit-def: $sgpr91
|
|
; VI-NEXT: ; implicit-def: $sgpr12
|
|
; VI-NEXT: ; implicit-def: $sgpr79
|
|
; VI-NEXT: ; implicit-def: $sgpr88
|
|
; VI-NEXT: ; implicit-def: $sgpr89
|
|
; VI-NEXT: ; implicit-def: $sgpr35
|
|
; VI-NEXT: ; implicit-def: $sgpr36
|
|
; VI-NEXT: ; implicit-def: $sgpr14
|
|
; VI-NEXT: ; implicit-def: $sgpr30
|
|
; VI-NEXT: ; implicit-def: $sgpr31
|
|
; VI-NEXT: ; implicit-def: $sgpr34
|
|
; VI-NEXT: ; implicit-def: $sgpr48
|
|
; VI-NEXT: ; implicit-def: $sgpr49
|
|
; VI-NEXT: ; implicit-def: $sgpr40
|
|
; VI-NEXT: ; implicit-def: $sgpr37
|
|
; VI-NEXT: ; implicit-def: $sgpr38
|
|
; VI-NEXT: ; implicit-def: $sgpr39
|
|
; VI-NEXT: ; implicit-def: $sgpr53
|
|
; VI-NEXT: ; implicit-def: $sgpr54
|
|
; VI-NEXT: ; implicit-def: $sgpr42
|
|
; VI-NEXT: ; implicit-def: $sgpr50
|
|
; VI-NEXT: ; implicit-def: $sgpr51
|
|
; VI-NEXT: ; implicit-def: $sgpr52
|
|
; VI-NEXT: ; implicit-def: $sgpr66
|
|
; VI-NEXT: ; implicit-def: $sgpr67
|
|
; VI-NEXT: ; implicit-def: $sgpr44
|
|
; VI-NEXT: ; implicit-def: $sgpr55
|
|
; VI-NEXT: ; implicit-def: $sgpr64
|
|
; VI-NEXT: ; implicit-def: $sgpr65
|
|
; VI-NEXT: s_branch .LBB109_2
|
|
; VI-NEXT: .LBB109_4:
|
|
; VI-NEXT: v_mov_b32_e32 v1, s65
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v1, s64
|
|
; VI-NEXT: v_mov_b32_e32 v12, s67
|
|
; VI-NEXT: v_mov_b32_e32 v15, s66
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; VI-NEXT: v_mov_b32_e32 v9, s55
|
|
; VI-NEXT: v_mov_b32_e32 v33, s54
|
|
; VI-NEXT: v_mov_b32_e32 v34, s53
|
|
; VI-NEXT: v_mov_b32_e32 v18, s52
|
|
; VI-NEXT: v_mov_b32_e32 v21, s51
|
|
; VI-NEXT: v_mov_b32_e32 v32, s50
|
|
; VI-NEXT: v_mov_b32_e32 v38, s49
|
|
; VI-NEXT: v_mov_b32_e32 v39, s48
|
|
; VI-NEXT: v_mov_b32_e32 v35, s39
|
|
; VI-NEXT: v_mov_b32_e32 v36, s38
|
|
; VI-NEXT: v_mov_b32_e32 v37, s37
|
|
; VI-NEXT: v_mov_b32_e32 v51, s36
|
|
; VI-NEXT: v_mov_b32_e32 v52, s35
|
|
; VI-NEXT: v_mov_b32_e32 v48, s34
|
|
; VI-NEXT: v_mov_b32_e32 v49, s31
|
|
; VI-NEXT: v_mov_b32_e32 v50, s30
|
|
; VI-NEXT: v_mov_b32_e32 v40, s91
|
|
; VI-NEXT: v_mov_b32_e32 v41, s90
|
|
; VI-NEXT: v_mov_b32_e32 v53, s89
|
|
; VI-NEXT: v_mov_b32_e32 v54, s88
|
|
; VI-NEXT: v_mov_b32_e32 v55, s79
|
|
; VI-NEXT: v_mov_b32_e32 v45, s78
|
|
; VI-NEXT: v_mov_b32_e32 v46, s77
|
|
; VI-NEXT: v_mov_b32_e32 v42, s76
|
|
; VI-NEXT: v_mov_b32_e32 v43, s75
|
|
; VI-NEXT: v_mov_b32_e32 v44, s74
|
|
; VI-NEXT: v_mov_b32_e32 v58, s73
|
|
; VI-NEXT: v_mov_b32_e32 v59, s72
|
|
; VI-NEXT: v_mov_b32_e32 v47, s63
|
|
; VI-NEXT: v_mov_b32_e32 v56, s62
|
|
; VI-NEXT: v_mov_b32_e32 v57, s61
|
|
; VI-NEXT: v_mov_b32_e32 v3, s60
|
|
; VI-NEXT: v_mov_b32_e32 v6, s59
|
|
; VI-NEXT: v_mov_b32_e32 v60, s58
|
|
; VI-NEXT: v_mov_b32_e32 v61, s57
|
|
; VI-NEXT: v_mov_b32_e32 v62, s56
|
|
; VI-NEXT: v_mov_b32_e32 v23, s4
|
|
; VI-NEXT: v_mov_b32_e32 v22, s5
|
|
; VI-NEXT: v_mov_b32_e32 v20, s28
|
|
; VI-NEXT: v_mov_b32_e32 v19, s29
|
|
; VI-NEXT: v_mov_b32_e32 v17, s26
|
|
; VI-NEXT: v_mov_b32_e32 v16, s27
|
|
; VI-NEXT: v_mov_b32_e32 v14, s24
|
|
; VI-NEXT: v_mov_b32_e32 v13, s25
|
|
; VI-NEXT: v_mov_b32_e32 v11, s22
|
|
; VI-NEXT: v_mov_b32_e32 v10, s23
|
|
; VI-NEXT: v_mov_b32_e32 v8, s20
|
|
; VI-NEXT: v_mov_b32_e32 v7, s21
|
|
; VI-NEXT: v_mov_b32_e32 v5, s18
|
|
; VI-NEXT: v_mov_b32_e32 v4, s19
|
|
; VI-NEXT: v_mov_b32_e32 v2, s16
|
|
; VI-NEXT: v_mov_b32_e32 v1, s17
|
|
; VI-NEXT: v_mov_b32_e32 v24, s44
|
|
; VI-NEXT: v_mov_b32_e32 v25, s42
|
|
; VI-NEXT: v_mov_b32_e32 v26, s40
|
|
; VI-NEXT: v_mov_b32_e32 v27, s14
|
|
; VI-NEXT: v_mov_b32_e32 v28, s12
|
|
; VI-NEXT: v_mov_b32_e32 v29, s10
|
|
; VI-NEXT: v_mov_b32_e32 v30, s8
|
|
; VI-NEXT: v_mov_b32_e32 v31, s6
|
|
; VI-NEXT: .LBB109_5: ; %end
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v3, v3, v31, s4
|
|
; VI-NEXT: v_perm_b32 v2, v2, v6, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v61, v60, s4
|
|
; VI-NEXT: v_perm_b32 v1, v1, v62, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v58, v30, s4
|
|
; VI-NEXT: v_perm_b32 v1, v5, v59, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v56, v47, s4
|
|
; VI-NEXT: v_perm_b32 v1, v4, v57, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v45, v29, s4
|
|
; VI-NEXT: v_perm_b32 v1, v8, v46, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v43, v42, s4
|
|
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v40, v28, s4
|
|
; VI-NEXT: v_perm_b32 v1, v11, v41, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v54, v53, s4
|
|
; VI-NEXT: v_perm_b32 v1, v10, v55, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v51, v27, s4
|
|
; VI-NEXT: v_perm_b32 v1, v14, v52, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v49, v48, s4
|
|
; VI-NEXT: v_perm_b32 v1, v13, v50, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v38, v26, s4
|
|
; VI-NEXT: v_perm_b32 v1, v17, v39, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v36, v35, s4
|
|
; VI-NEXT: v_perm_b32 v1, v16, v37, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v33, v25, s4
|
|
; VI-NEXT: v_perm_b32 v1, v20, v34, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v21, v18, s4
|
|
; VI-NEXT: v_perm_b32 v1, v19, v32, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: v_perm_b32 v2, v12, v24, s4
|
|
; VI-NEXT: v_perm_b32 v1, v23, v15, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
|
|
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_perm_b32 v1, v22, v9, s4
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
|
|
; VI-NEXT: v_readlane_b32 s30, v63, 18
|
|
; VI-NEXT: v_readlane_b32 s31, v63, 19
|
|
; VI-NEXT: v_readlane_b32 s67, v63, 17
|
|
; VI-NEXT: v_readlane_b32 s66, v63, 16
|
|
; VI-NEXT: v_readlane_b32 s65, v63, 15
|
|
; VI-NEXT: v_readlane_b32 s64, v63, 14
|
|
; VI-NEXT: v_readlane_b32 s55, v63, 13
|
|
; VI-NEXT: v_readlane_b32 s54, v63, 12
|
|
; VI-NEXT: v_readlane_b32 s53, v63, 11
|
|
; VI-NEXT: v_readlane_b32 s52, v63, 10
|
|
; VI-NEXT: v_readlane_b32 s51, v63, 9
|
|
; VI-NEXT: v_readlane_b32 s50, v63, 8
|
|
; VI-NEXT: v_readlane_b32 s49, v63, 7
|
|
; VI-NEXT: v_readlane_b32 s48, v63, 6
|
|
; VI-NEXT: v_readlane_b32 s39, v63, 5
|
|
; VI-NEXT: v_readlane_b32 s38, v63, 4
|
|
; VI-NEXT: v_readlane_b32 s37, v63, 3
|
|
; VI-NEXT: v_readlane_b32 s36, v63, 2
|
|
; VI-NEXT: v_readlane_b32 s35, v63, 1
|
|
; VI-NEXT: v_readlane_b32 s34, v63, 0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v32bf16_to_v64i8_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_writelane_b32 v63, s34, 0
|
|
; GFX9-NEXT: v_writelane_b32 v63, s35, 1
|
|
; GFX9-NEXT: v_writelane_b32 v63, s36, 2
|
|
; GFX9-NEXT: v_writelane_b32 v63, s37, 3
|
|
; GFX9-NEXT: v_writelane_b32 v63, s38, 4
|
|
; GFX9-NEXT: v_writelane_b32 v63, s39, 5
|
|
; GFX9-NEXT: v_writelane_b32 v63, s48, 6
|
|
; GFX9-NEXT: v_writelane_b32 v63, s49, 7
|
|
; GFX9-NEXT: v_writelane_b32 v63, s50, 8
|
|
; GFX9-NEXT: v_writelane_b32 v63, s51, 9
|
|
; GFX9-NEXT: v_writelane_b32 v63, s52, 10
|
|
; GFX9-NEXT: v_writelane_b32 v63, s53, 11
|
|
; GFX9-NEXT: v_writelane_b32 v63, s54, 12
|
|
; GFX9-NEXT: v_writelane_b32 v63, s55, 13
|
|
; GFX9-NEXT: v_writelane_b32 v63, s30, 14
|
|
; GFX9-NEXT: v_writelane_b32 v63, s31, 15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s5, v2
|
|
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
|
|
; GFX9-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB109_3
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: s_lshr_b32 s91, s5, 24
|
|
; GFX9-NEXT: s_lshr_b32 s54, s5, 16
|
|
; GFX9-NEXT: s_lshr_b32 s93, s5, 8
|
|
; GFX9-NEXT: s_lshr_b32 s55, s4, 16
|
|
; GFX9-NEXT: s_lshr_b32 s95, s4, 8
|
|
; GFX9-NEXT: s_lshr_b32 s88, s29, 24
|
|
; GFX9-NEXT: s_lshr_b32 s52, s29, 16
|
|
; GFX9-NEXT: s_lshr_b32 s90, s29, 8
|
|
; GFX9-NEXT: s_lshr_b32 s53, s28, 16
|
|
; GFX9-NEXT: s_lshr_b32 s94, s28, 8
|
|
; GFX9-NEXT: s_lshr_b32 s77, s27, 24
|
|
; GFX9-NEXT: s_lshr_b32 s50, s27, 16
|
|
; GFX9-NEXT: s_lshr_b32 s79, s27, 8
|
|
; GFX9-NEXT: s_lshr_b32 s51, s26, 16
|
|
; GFX9-NEXT: s_lshr_b32 s92, s26, 8
|
|
; GFX9-NEXT: s_lshr_b32 s74, s25, 24
|
|
; GFX9-NEXT: s_lshr_b32 s48, s25, 16
|
|
; GFX9-NEXT: s_lshr_b32 s76, s25, 8
|
|
; GFX9-NEXT: s_lshr_b32 s49, s24, 16
|
|
; GFX9-NEXT: s_lshr_b32 s89, s24, 8
|
|
; GFX9-NEXT: s_lshr_b32 s63, s23, 24
|
|
; GFX9-NEXT: s_lshr_b32 s38, s23, 16
|
|
; GFX9-NEXT: s_lshr_b32 s73, s23, 8
|
|
; GFX9-NEXT: s_lshr_b32 s39, s22, 16
|
|
; GFX9-NEXT: s_lshr_b32 s78, s22, 8
|
|
; GFX9-NEXT: s_lshr_b32 s60, s21, 24
|
|
; GFX9-NEXT: s_lshr_b32 s36, s21, 16
|
|
; GFX9-NEXT: s_lshr_b32 s62, s21, 8
|
|
; GFX9-NEXT: s_lshr_b32 s37, s20, 16
|
|
; GFX9-NEXT: s_lshr_b32 s75, s20, 8
|
|
; GFX9-NEXT: s_lshr_b32 s58, s19, 24
|
|
; GFX9-NEXT: s_lshr_b32 s34, s19, 16
|
|
; GFX9-NEXT: s_lshr_b32 s59, s19, 8
|
|
; GFX9-NEXT: s_lshr_b32 s35, s18, 16
|
|
; GFX9-NEXT: s_lshr_b32 s72, s18, 8
|
|
; GFX9-NEXT: s_lshr_b32 s56, s17, 24
|
|
; GFX9-NEXT: s_lshr_b32 s30, s17, 16
|
|
; GFX9-NEXT: s_lshr_b32 s57, s17, 8
|
|
; GFX9-NEXT: s_lshr_b32 s31, s16, 16
|
|
; GFX9-NEXT: s_lshr_b32 s61, s16, 8
|
|
; GFX9-NEXT: s_lshr_b64 s[44:45], s[4:5], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[42:43], s[28:29], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[14:15], s[24:25], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[12:13], s[22:23], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[10:11], s[20:21], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[8:9], s[18:19], 24
|
|
; GFX9-NEXT: s_lshr_b64 s[6:7], s[16:17], 24
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB109_4
|
|
; GFX9-NEXT: .LBB109_2: ; %cmp.true
|
|
; GFX9-NEXT: s_and_b32 s6, s17, 0xffff0000
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0x40c00000
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s17, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: s_and_b32 s6, s16, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s16, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v30
|
|
; GFX9-NEXT: s_and_b32 s6, s19, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v31, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s19, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v32
|
|
; GFX9-NEXT: s_and_b32 s6, s18, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v29, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s18, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v35
|
|
; GFX9-NEXT: s_and_b32 s6, s21, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v37, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s21, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v28
|
|
; GFX9-NEXT: s_and_b32 s6, s20, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v27, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s20, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v50
|
|
; GFX9-NEXT: s_and_b32 s6, s23, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v36, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s23, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v34
|
|
; GFX9-NEXT: s_and_b32 s6, s22, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v20, v33, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s22, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v48
|
|
; GFX9-NEXT: s_and_b32 s6, s25, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v19, v38, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s25, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v49
|
|
; GFX9-NEXT: s_and_b32 s6, s24, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v22, v39, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s24, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v53
|
|
; GFX9-NEXT: s_and_b32 s6, s27, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v21, v51, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s27, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v54
|
|
; GFX9-NEXT: s_and_b32 s6, s26, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v24, v52, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s26, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v41
|
|
; GFX9-NEXT: s_and_b32 s6, s29, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v23, v55, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s29, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v42
|
|
; GFX9-NEXT: s_and_b32 s6, s28, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v26, v40, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s6, s28, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v45
|
|
; GFX9-NEXT: s_and_b32 s6, s5, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v25, v43, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: s_lshl_b32 s5, s5, 16
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s5, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v2
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v46
|
|
; GFX9-NEXT: s_and_b32 s5, s4, 0xffff0000
|
|
; GFX9-NEXT: v_lshl_or_b32 v58, v44, 16, v2
|
|
; GFX9-NEXT: v_add_f32_e32 v2, s5, v1
|
|
; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
|
|
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
|
|
; GFX9-NEXT: s_lshl_b32 s4, s4, 16
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
|
|
; GFX9-NEXT: v_add_f32_e32 v1, s4, v1
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v2
|
|
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
|
|
; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v1
|
|
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
|
|
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b64 v[5:6], 24, v[25:26]
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v56
|
|
; GFX9-NEXT: v_lshrrev_b64 v[6:7], 24, v[23:24]
|
|
; GFX9-NEXT: v_lshl_or_b32 v57, v47, 16, v1
|
|
; GFX9-NEXT: v_lshrrev_b64 v[7:8], 24, v[21:22]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[16:17], 24, v[10:11]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[1:2], 24, v[57:58]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[8:9], 24, v[19:20]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[12:13], 24, v[14:15]
|
|
; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 24, v58
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v58
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v57
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 24, v26
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v26
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v25
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v24
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 8, v24
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 8, v23
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v22
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v22
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v21
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 24, v20
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v20
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v19
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 24, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v15
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 8, v14
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v11, 8, v11
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 8, v10
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v4
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v3
|
|
; GFX9-NEXT: s_branch .LBB109_5
|
|
; GFX9-NEXT: .LBB109_3:
|
|
; GFX9-NEXT: ; implicit-def: $sgpr61
|
|
; GFX9-NEXT: ; implicit-def: $sgpr31
|
|
; GFX9-NEXT: ; implicit-def: $sgpr6
|
|
; GFX9-NEXT: ; implicit-def: $sgpr57
|
|
; GFX9-NEXT: ; implicit-def: $sgpr30
|
|
; GFX9-NEXT: ; implicit-def: $sgpr56
|
|
; GFX9-NEXT: ; implicit-def: $sgpr72
|
|
; GFX9-NEXT: ; implicit-def: $sgpr35
|
|
; GFX9-NEXT: ; implicit-def: $sgpr8
|
|
; GFX9-NEXT: ; implicit-def: $sgpr59
|
|
; GFX9-NEXT: ; implicit-def: $sgpr34
|
|
; GFX9-NEXT: ; implicit-def: $sgpr58
|
|
; GFX9-NEXT: ; implicit-def: $sgpr75
|
|
; GFX9-NEXT: ; implicit-def: $sgpr37
|
|
; GFX9-NEXT: ; implicit-def: $sgpr10
|
|
; GFX9-NEXT: ; implicit-def: $sgpr62
|
|
; GFX9-NEXT: ; implicit-def: $sgpr36
|
|
; GFX9-NEXT: ; implicit-def: $sgpr60
|
|
; GFX9-NEXT: ; implicit-def: $sgpr78
|
|
; GFX9-NEXT: ; implicit-def: $sgpr39
|
|
; GFX9-NEXT: ; implicit-def: $sgpr12
|
|
; GFX9-NEXT: ; implicit-def: $sgpr73
|
|
; GFX9-NEXT: ; implicit-def: $sgpr38
|
|
; GFX9-NEXT: ; implicit-def: $sgpr63
|
|
; GFX9-NEXT: ; implicit-def: $sgpr89
|
|
; GFX9-NEXT: ; implicit-def: $sgpr49
|
|
; GFX9-NEXT: ; implicit-def: $sgpr14
|
|
; GFX9-NEXT: ; implicit-def: $sgpr76
|
|
; GFX9-NEXT: ; implicit-def: $sgpr48
|
|
; GFX9-NEXT: ; implicit-def: $sgpr74
|
|
; GFX9-NEXT: ; implicit-def: $sgpr92
|
|
; GFX9-NEXT: ; implicit-def: $sgpr51
|
|
; GFX9-NEXT: ; implicit-def: $sgpr40
|
|
; GFX9-NEXT: ; implicit-def: $sgpr79
|
|
; GFX9-NEXT: ; implicit-def: $sgpr50
|
|
; GFX9-NEXT: ; implicit-def: $sgpr77
|
|
; GFX9-NEXT: ; implicit-def: $sgpr94
|
|
; GFX9-NEXT: ; implicit-def: $sgpr53
|
|
; GFX9-NEXT: ; implicit-def: $sgpr42
|
|
; GFX9-NEXT: ; implicit-def: $sgpr90
|
|
; GFX9-NEXT: ; implicit-def: $sgpr52
|
|
; GFX9-NEXT: ; implicit-def: $sgpr88
|
|
; GFX9-NEXT: ; implicit-def: $sgpr95
|
|
; GFX9-NEXT: ; implicit-def: $sgpr55
|
|
; GFX9-NEXT: ; implicit-def: $sgpr44
|
|
; GFX9-NEXT: ; implicit-def: $sgpr93
|
|
; GFX9-NEXT: ; implicit-def: $sgpr54
|
|
; GFX9-NEXT: ; implicit-def: $sgpr91
|
|
; GFX9-NEXT: s_branch .LBB109_2
|
|
; GFX9-NEXT: .LBB109_4:
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s17
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s30
|
|
; GFX9-NEXT: v_mov_b32_e32 v56, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v47, s55
|
|
; GFX9-NEXT: v_mov_b32_e32 v46, s5
|
|
; GFX9-NEXT: v_mov_b32_e32 v44, s54
|
|
; GFX9-NEXT: v_mov_b32_e32 v45, s28
|
|
; GFX9-NEXT: v_mov_b32_e32 v43, s53
|
|
; GFX9-NEXT: v_mov_b32_e32 v42, s29
|
|
; GFX9-NEXT: v_mov_b32_e32 v40, s52
|
|
; GFX9-NEXT: v_mov_b32_e32 v41, s26
|
|
; GFX9-NEXT: v_mov_b32_e32 v55, s51
|
|
; GFX9-NEXT: v_mov_b32_e32 v54, s27
|
|
; GFX9-NEXT: v_mov_b32_e32 v52, s50
|
|
; GFX9-NEXT: v_mov_b32_e32 v53, s24
|
|
; GFX9-NEXT: v_mov_b32_e32 v51, s49
|
|
; GFX9-NEXT: v_mov_b32_e32 v49, s25
|
|
; GFX9-NEXT: v_mov_b32_e32 v39, s48
|
|
; GFX9-NEXT: v_mov_b32_e32 v48, s22
|
|
; GFX9-NEXT: v_mov_b32_e32 v38, s39
|
|
; GFX9-NEXT: v_mov_b32_e32 v34, s23
|
|
; GFX9-NEXT: v_mov_b32_e32 v33, s38
|
|
; GFX9-NEXT: v_mov_b32_e32 v50, s20
|
|
; GFX9-NEXT: v_mov_b32_e32 v36, s37
|
|
; GFX9-NEXT: v_mov_b32_e32 v28, s21
|
|
; GFX9-NEXT: v_mov_b32_e32 v27, s36
|
|
; GFX9-NEXT: v_mov_b32_e32 v35, s18
|
|
; GFX9-NEXT: v_mov_b32_e32 v37, s35
|
|
; GFX9-NEXT: v_mov_b32_e32 v32, s19
|
|
; GFX9-NEXT: v_mov_b32_e32 v29, s34
|
|
; GFX9-NEXT: v_mov_b32_e32 v30, s16
|
|
; GFX9-NEXT: v_mov_b32_e32 v31, s31
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: v_mov_b32_e32 v13, s95
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s91
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s93
|
|
; GFX9-NEXT: v_mov_b32_e32 v58, s94
|
|
; GFX9-NEXT: v_mov_b32_e32 v18, s88
|
|
; GFX9-NEXT: v_mov_b32_e32 v57, s90
|
|
; GFX9-NEXT: v_mov_b32_e32 v23, s92
|
|
; GFX9-NEXT: v_mov_b32_e32 v59, s77
|
|
; GFX9-NEXT: v_mov_b32_e32 v24, s79
|
|
; GFX9-NEXT: v_mov_b32_e32 v21, s89
|
|
; GFX9-NEXT: v_mov_b32_e32 v60, s74
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s76
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, s78
|
|
; GFX9-NEXT: v_mov_b32_e32 v61, s63
|
|
; GFX9-NEXT: v_mov_b32_e32 v20, s73
|
|
; GFX9-NEXT: v_mov_b32_e32 v14, s75
|
|
; GFX9-NEXT: v_mov_b32_e32 v62, s60
|
|
; GFX9-NEXT: v_mov_b32_e32 v15, s62
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s72
|
|
; GFX9-NEXT: v_mov_b32_e32 v25, s58
|
|
; GFX9-NEXT: v_mov_b32_e32 v11, s59
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s61
|
|
; GFX9-NEXT: v_mov_b32_e32 v26, s56
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s57
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s44
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s42
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s40
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s14
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s12
|
|
; GFX9-NEXT: v_mov_b32_e32 v12, s10
|
|
; GFX9-NEXT: v_mov_b32_e32 v16, s8
|
|
; GFX9-NEXT: v_mov_b32_e32 v17, s6
|
|
; GFX9-NEXT: .LBB109_5: ; %end
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v17, v31, v17, s4
|
|
; GFX9-NEXT: v_perm_b32 v3, v30, v3, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v16, v37, v16, s4
|
|
; GFX9-NEXT: v_perm_b32 v1, v47, v1, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; GFX9-NEXT: v_perm_b32 v2, v44, v2, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; GFX9-NEXT: v_readlane_b32 s30, v63, 14
|
|
; GFX9-NEXT: v_readlane_b32 s31, v63, 15
|
|
; GFX9-NEXT: v_readlane_b32 s55, v63, 13
|
|
; GFX9-NEXT: v_readlane_b32 s54, v63, 12
|
|
; GFX9-NEXT: v_readlane_b32 s53, v63, 11
|
|
; GFX9-NEXT: v_readlane_b32 s52, v63, 10
|
|
; GFX9-NEXT: v_readlane_b32 s51, v63, 9
|
|
; GFX9-NEXT: v_readlane_b32 s50, v63, 8
|
|
; GFX9-NEXT: v_readlane_b32 s49, v63, 7
|
|
; GFX9-NEXT: v_readlane_b32 s48, v63, 6
|
|
; GFX9-NEXT: v_readlane_b32 s39, v63, 5
|
|
; GFX9-NEXT: v_readlane_b32 s38, v63, 4
|
|
; GFX9-NEXT: v_readlane_b32 s37, v63, 3
|
|
; GFX9-NEXT: v_readlane_b32 s36, v63, 2
|
|
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
|
|
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v4, v4, v26, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:4
|
|
; GFX9-NEXT: v_perm_b32 v3, v35, v10, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v16
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v29, v25, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:8
|
|
; GFX9-NEXT: v_perm_b32 v3, v32, v11, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v36, v12, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:12
|
|
; GFX9-NEXT: v_perm_b32 v3, v50, v14, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v27, v62, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:16
|
|
; GFX9-NEXT: v_perm_b32 v3, v28, v15, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v38, v8, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:20
|
|
; GFX9-NEXT: v_perm_b32 v3, v48, v19, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v33, v61, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
|
|
; GFX9-NEXT: v_perm_b32 v3, v34, v20, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v51, v7, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
|
|
; GFX9-NEXT: v_perm_b32 v3, v53, v21, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v39, v60, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:32
|
|
; GFX9-NEXT: v_perm_b32 v3, v49, v22, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v55, v6, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:36
|
|
; GFX9-NEXT: v_perm_b32 v3, v41, v23, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v52, v59, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:40
|
|
; GFX9-NEXT: v_perm_b32 v3, v54, v24, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v43, v5, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:44
|
|
; GFX9-NEXT: v_perm_b32 v3, v45, v58, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: v_perm_b32 v4, v40, v18, s4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
|
|
; GFX9-NEXT: v_perm_b32 v3, v42, v57, s4
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
|
|
; GFX9-NEXT: v_perm_b32 v3, v56, v13, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
|
|
; GFX9-NEXT: v_perm_b32 v1, v46, v9, s4
|
|
; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
|
|
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v32bf16_to_v64i8_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s4, -1
|
|
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s4
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s34, 0
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s35, 1
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s36, 2
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s37, 3
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s38, 4
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s39, 5
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s48, 6
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s49, 7
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s30, 8
|
|
; GFX11-TRUE16-NEXT: v_writelane_b32 v40, s31, 9
|
|
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB109_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s78, s27, 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s48, s27, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s88, s27, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s49, s26, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s90, s26, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s75, s25, 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s38, s25, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s77, s25, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s39, s24, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s89, s24, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s72, s23, 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s36, s23, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s74, s23, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s37, s22, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s79, s22, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s61, s21, 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s63, s21, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s35, s20, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s76, s20, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s58, s19, 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s30, s19, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s60, s19, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s31, s18, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s73, s18, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s47, s17, 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s95, s17, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s57, s17, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 vcc_hi, s16, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s62, s16, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s45, s3, 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s93, s3, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s46, s3, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s94, s2, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s59, s2, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s43, s1, 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s91, s1, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s44, s1, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s92, s0, 16
|
|
; GFX11-TRUE16-NEXT: s_lshr_b32 s56, s0, 8
|
|
; GFX11-TRUE16-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b64 s[28:29], s[24:25], 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b64 s[12:13], s[20:21], 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b64 s[10:11], s[18:19], 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b64 s[8:9], s[16:17], 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b64 s[6:7], s[2:3], 24
|
|
; GFX11-TRUE16-NEXT: s_lshr_b64 s[4:5], s[0:1], 24
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB109_4
|
|
; GFX11-TRUE16-NEXT: .LBB109_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s1, 16
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s4, s0, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v4, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 16
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s2, 16
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v11, v6
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v5, v8 :: v_dual_add_nc_u32 v5, 0x7fff, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v2
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v17.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v9 :: v_dual_add_nc_u32 v4, v5, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v6, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v6, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v8, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v6
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v4
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v21.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 24, v2
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_add_nc_u32 v6, 0x7fff, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s1, s19, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v10, v11
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v9
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s26, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v25, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v23.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v8, v10
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v12 :: v_dual_add_nc_u32 v7, v9, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_add_nc_u32 v8, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v15, v12
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v9, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 16, v5
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v9 :: v_dual_add_nc_u32 v8, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v15, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_add_nc_u32 v7, v9, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s1
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v14, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v12 :: v_dual_add_nc_u32 v8, v9, v10
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v11, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v10
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v11
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v8 :: v_dual_add_nc_u32 v8, 0x7fff, v9
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v10, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v34.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v13
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.h, v37.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.l, v48.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v38.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v30.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.h, v33.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v8
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v35.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.h, v36.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.h, v29.l
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v10 :: v_dual_add_nc_u32 v10, 0x7fff, v11
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.h, v39.l
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v7, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v31.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.h, v32.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v12, v7
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v9, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v9
|
|
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v9
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v8, v10, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v12, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v13, 16, 1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v52, 0x400000, v13
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v12
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v49.l
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v11, v51 :: v_dual_add_nc_u32 v10, v10, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v12
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v14
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v50.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v53.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v55.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v15, v51, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v26.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v27.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.l
|
|
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v52, vcc_lo
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v51.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v22.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v24.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v52.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v18.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v19.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 24, v67
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v54.l
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v81
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v80
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v84
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[7:8], 24, v[66:67]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[68:69]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[9:10], 24, v[80:81]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[10:11], 24, v[83:84]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[85:86]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[5:6]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[3:4]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[1:2]
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 8, v67
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v66
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v69
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v69
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 8, v68
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v81
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v84
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v83
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v86
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v86
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v85
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v4
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v3
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
|
|
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB109_5
|
|
; GFX11-TRUE16-NEXT: .LBB109_3:
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr56
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr92
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr4
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr44
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr91
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr43
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr59
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr94
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr6
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr46
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr93
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr45
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr62
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vcc_hi
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr8
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr57
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr95
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr47
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr73
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr31
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr10
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr60
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr30
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr58
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr76
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr35
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr12
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr63
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr34
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr61
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr79
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr37
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr14
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr74
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr36
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr72
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr89
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr39
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr28
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr77
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr38
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr75
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr90
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr49
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr40
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr88
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr48
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr78
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB109_2
|
|
; GFX11-TRUE16-NEXT: .LBB109_4:
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, s26 :: v_dual_mov_b32 v51, s27
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s49 :: v_dual_mov_b32 v53, s48
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, s24 :: v_dual_mov_b32 v50, s39
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, s25 :: v_dual_mov_b32 v48, s22
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, s38 :: v_dual_mov_b32 v38, s37
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, s23 :: v_dual_mov_b32 v37, s36
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s20 :: v_dual_mov_b32 v36, s35
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s21 :: v_dual_mov_b32 v33, s34
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s18 :: v_dual_mov_b32 v32, s31
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, s19 :: v_dual_mov_b32 v29, s30
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, s16 :: v_dual_mov_b32 v27, vcc_hi
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, s17 :: v_dual_mov_b32 v22, s2
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, s95 :: v_dual_mov_b32 v24, s94
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v21, s93
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s0 :: v_dual_mov_b32 v19, s92
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s1 :: v_dual_mov_b32 v17, s91
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, s90 :: v_dual_mov_b32 v65, s78
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, s88 :: v_dual_mov_b32 v68, s89
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v67, s75 :: v_dual_mov_b32 v66, s77
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v71, s79 :: v_dual_mov_b32 v70, s72
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v69, s74 :: v_dual_mov_b32 v82, s61
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v81, s76 :: v_dual_mov_b32 v80, s63
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v85, s73 :: v_dual_mov_b32 v84, s58
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v83, s60 :: v_dual_mov_b32 v86, s47
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, s62 :: v_dual_mov_b32 v6, s57
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, s59 :: v_dual_mov_b32 v4, s46
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v87, s45 :: v_dual_mov_b32 v96, s43
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s56 :: v_dual_mov_b32 v2, s44
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, s40 :: v_dual_mov_b32 v8, s28
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, s14 :: v_dual_mov_b32 v10, s12
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, s10 :: v_dual_mov_b32 v12, s8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, s6 :: v_dual_mov_b32 v14, s4
|
|
; GFX11-TRUE16-NEXT: .LBB109_5: ; %end
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v19, v14, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v1, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v96, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v24, v13, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v27, v12, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v16, v2, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v22, v3, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v14
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v25, v86, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v21, v87, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v26, v5, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v32, v11, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v23, v6, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v13
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v17
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v5, v12
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v29, v84, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v16
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v20, v4, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v85, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v6, v14
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v36, v10, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v33, v82, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v38, v9, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v13
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v16, v17
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v35, v81, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v30, v80, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v48, v71, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v6, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v17, v18
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v9
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v8, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v39, v67, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v54, v7, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v53, v65, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v34, v69, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v55, v68, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v49, v66, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v52, v64, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v15, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v8, v5
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v6
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v20, v10
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v21, v7
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v22
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 8
|
|
; GFX11-TRUE16-NEXT: s_clause 0x3
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[11:14], off offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[16:19], off offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 9
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s49, v40, 7
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s48, v40, 6
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s39, v40, 5
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s38, v40, 4
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s37, v40, 3
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s36, v40, 2
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s35, v40, 1
|
|
; GFX11-TRUE16-NEXT: v_readlane_b32 s34, v40, 0
|
|
; GFX11-TRUE16-NEXT: s_or_saveexec_b32 s0, -1
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v32bf16_to_v64i8_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s4, -1
|
|
; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 ; 4-byte Folded Spill
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s4
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s34, 0
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s35, 1
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s36, 2
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s37, 3
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s38, 4
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s39, 5
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s48, 6
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s49, 7
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s30, 8
|
|
; GFX11-FAKE16-NEXT: v_writelane_b32 v40, s31, 9
|
|
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s28, 0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s42, 0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB109_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s78, s27, 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s48, s27, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s88, s27, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s49, s26, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s90, s26, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s75, s25, 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s38, s25, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s77, s25, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s39, s24, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s89, s24, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s72, s23, 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s36, s23, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s74, s23, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s37, s22, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s79, s22, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s61, s21, 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s34, s21, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s63, s21, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s35, s20, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s76, s20, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s58, s19, 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s30, s19, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s60, s19, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s31, s18, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s73, s18, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s47, s17, 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s95, s17, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s57, s17, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 vcc_hi, s16, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s62, s16, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s45, s3, 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s93, s3, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s46, s3, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s94, s2, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s59, s2, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s43, s1, 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s91, s1, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s44, s1, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s92, s0, 16
|
|
; GFX11-FAKE16-NEXT: s_lshr_b32 s56, s0, 8
|
|
; GFX11-FAKE16-NEXT: s_lshr_b64 s[40:41], s[26:27], 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b64 s[28:29], s[24:25], 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b64 s[14:15], s[22:23], 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b64 s[12:13], s[20:21], 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b64 s[10:11], s[18:19], 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b64 s[8:9], s[16:17], 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b64 s[6:7], s[2:3], 24
|
|
; GFX11-FAKE16-NEXT: s_lshr_b64 s[4:5], s[0:1], 24
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB109_4
|
|
; GFX11-FAKE16-NEXT: .LBB109_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s1, 16
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v1, 0x40c00000, s4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v2, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s4, s0, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v4, 0x40c00000, s4
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v3, v1, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v2, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v2
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v2
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s1, s3, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v4, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s2, 16
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v3, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v11, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v9
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v6, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 16, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v5, v7
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v9 :: v_dual_add_nc_u32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v16
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v1, v10, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v8, v9
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v17, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v20, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v4, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v19, 16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v9, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v9, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v20
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v12, v8
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v22, 16, v6
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v10, v13
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v21
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v12, v9
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v25
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v97, v23, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v9
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v96, v27, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 24, v97
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v15, 16, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 8, v96
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v7, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v24
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v84, v26, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v12, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v13, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v28, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v29, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v11, v30, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s20, 16
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v28
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s23, 16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v82, v29, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v6
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v12, v12, v10
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v31, v11
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v33, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v34, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v34
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v31
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s25, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v30
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v70, v33, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v10
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s25, 16
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v81, v35, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v12, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v8, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v39, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v13, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v36, v8
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v39, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v10
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s24, 16
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v39
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v49, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v49, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s27, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v11, v49
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v49
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s26, 16
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v11, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v13, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v6, 16, 1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v12 :: v_dual_add_nc_u32 v12, v50, v11
|
|
; GFX11-FAKE16-NEXT: v_add_f32_e64 v51, 0x40c00000, s0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v50, v52, v13
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v11
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v6
|
|
; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v51, 16, 1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v50, 0x7fff, v50
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v13
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v53, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v6
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v49, v49, v51
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v51
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v50, v54, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v36
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v49
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v52, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v37
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v67, v39, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v83, v32, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v53, vcc_lo
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v49
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v50
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v69, v38, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v53
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v65, v51, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 24, v70
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v82
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v64, v52, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v66, v48, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 24, v65
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v81
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[5:6], 24, v[64:65]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[66:67]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[7:8], 24, v[69:70]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[81:82]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[9:10], 24, v[83:84]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[10:11], 24, v[96:97]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[3:4]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[1:2]
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v65
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 8, v64
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 24, v67
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v67
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v66
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 8, v70
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v69
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 8, v82
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 24, v84
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 8, v84
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 8, v83
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v97
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 8, v4
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 8, v3
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 24, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
|
|
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB109_5
|
|
; GFX11-FAKE16-NEXT: .LBB109_3:
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr56
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr92
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr4
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr44
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr91
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr43
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr59
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr94
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr6
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr46
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr93
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr45
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr62
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vcc_hi
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr8
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr57
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr95
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr47
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr73
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr10
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr60
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr58
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr76
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr12
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr63
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr61
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr79
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr14
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr74
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr72
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr89
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr77
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr75
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr90
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr40
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr88
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $sgpr78
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB109_2
|
|
; GFX11-FAKE16-NEXT: .LBB109_4:
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, s26 :: v_dual_mov_b32 v49, s27
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s49 :: v_dual_mov_b32 v51, s48
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, s24 :: v_dual_mov_b32 v48, s39
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s25 :: v_dual_mov_b32 v39, s38
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, s22 :: v_dual_mov_b32 v38, s37
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, s23 :: v_dual_mov_b32 v34, s20
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, s36 :: v_dual_mov_b32 v28, s21
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, s35 :: v_dual_mov_b32 v30, s18
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v29, s34 :: v_dual_mov_b32 v32, s31
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, s19 :: v_dual_mov_b32 v25, s16
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, s30 :: v_dual_mov_b32 v27, vcc_hi
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, s17 :: v_dual_mov_b32 v20, s2
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, s95 :: v_dual_mov_b32 v22, s94
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s3 :: v_dual_mov_b32 v19, s93
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v17, s92
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s1 :: v_dual_mov_b32 v15, s91
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, s90 :: v_dual_mov_b32 v55, s78
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, s88 :: v_dual_mov_b32 v66, s89
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, s75 :: v_dual_mov_b32 v64, s77
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, s79 :: v_dual_mov_b32 v68, s72
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, s74 :: v_dual_mov_b32 v80, s61
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v71, s76 :: v_dual_mov_b32 v70, s63
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, s73 :: v_dual_mov_b32 v82, s58
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v81, s60 :: v_dual_mov_b32 v86, s47
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, s62 :: v_dual_mov_b32 v84, s57
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, s59 :: v_dual_mov_b32 v4, s46
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v87, s45 :: v_dual_mov_b32 v96, s43
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s56 :: v_dual_mov_b32 v2, s44
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, s40 :: v_dual_mov_b32 v6, s28
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s12
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, s8
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s4
|
|
; GFX11-FAKE16-NEXT: .LBB109_5: ; %end
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v17, v12, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v96, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v16, v1, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v22, v11, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v14, v2, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v27, v10, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v19, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v12
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v23, v86, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v14
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v25, v85, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v32, v9, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v11
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v84, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v18, v4, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v30, v83, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v82, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v35, v8, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v12
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v80, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v81, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v34, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v38, v7, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v28, v70, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v37, v69, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v68, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v15
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v65, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v52, v5, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v51, v55, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v7
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v31, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v53, v66, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v36, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v50, v54, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v49, v13, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v7, v8
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v18, v6
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v19, v21
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v22, v23
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v20
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 8
|
|
; GFX11-FAKE16-NEXT: s_clause 0x3
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 9
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s49, v40, 7
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s48, v40, 6
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s39, v40, 5
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s38, v40, 4
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s37, v40, 3
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s36, v40, 2
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s35, v40, 1
|
|
; GFX11-FAKE16-NEXT: v_readlane_b32 s34, v40, 0
|
|
; GFX11-FAKE16-NEXT: s_or_saveexec_b32 s0, -1
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 ; 4-byte Folded Reload
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = fadd <32 x bfloat> %a, splat (bfloat 0xR40C0)
|
|
%a2 = bitcast <32 x bfloat> %a1 to <64 x i8>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <32 x bfloat> %a to <64 x i8>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <64 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <64 x i8> %phi
|
|
}
|
|
|
|
define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v32bf16:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:80
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:88
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:96
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:112
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:120
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:128
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:108
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:104
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:100
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:92
|
|
; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v3
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 8, v5
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v7
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v11
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v15
|
|
; SI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; kill: killed $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v38, 8, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v36, 24, v19
|
|
; SI-NEXT: v_lshlrev_b32_e32 v51, 8, v21
|
|
; SI-NEXT: v_lshlrev_b32_e32 v48, 24, v23
|
|
; SI-NEXT: v_lshlrev_b32_e32 v49, 24, v27
|
|
; SI-NEXT: v_lshlrev_b32_e32 v42, 8, v29
|
|
; SI-NEXT: ; kill: killed $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; kill: killed $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr21
|
|
; SI-NEXT: ; implicit-def: $vgpr23
|
|
; SI-NEXT: ; implicit-def: $vgpr27
|
|
; SI-NEXT: ; implicit-def: $vgpr29
|
|
; SI-NEXT: ; implicit-def: $vgpr50
|
|
; SI-NEXT: ; implicit-def: $vgpr52
|
|
; SI-NEXT: ; implicit-def: $vgpr53
|
|
; SI-NEXT: ; implicit-def: $vgpr55
|
|
; SI-NEXT: ; implicit-def: $vgpr41
|
|
; SI-NEXT: ; implicit-def: $vgpr44
|
|
; SI-NEXT: ; implicit-def: $vgpr45
|
|
; SI-NEXT: ; implicit-def: $vgpr46
|
|
; SI-NEXT: ; implicit-def: $vgpr57
|
|
; SI-NEXT: ; implicit-def: $vgpr58
|
|
; SI-NEXT: ; implicit-def: $vgpr61
|
|
; SI-NEXT: ; implicit-def: $vgpr62
|
|
; SI-NEXT: ; implicit-def: $vgpr31
|
|
; SI-NEXT: ; implicit-def: $vgpr32
|
|
; SI-NEXT: ; implicit-def: $vgpr11
|
|
; SI-NEXT: ; implicit-def: $vgpr13
|
|
; SI-NEXT: ; implicit-def: $vgpr33
|
|
; SI-NEXT: ; implicit-def: $vgpr30
|
|
; SI-NEXT: ; implicit-def: $vgpr34
|
|
; SI-NEXT: ; implicit-def: $vgpr15
|
|
; SI-NEXT: ; implicit-def: $vgpr35
|
|
; SI-NEXT: ; implicit-def: $vgpr19
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v54, 24, v1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v40, 24, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v60, 8, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v47, 24, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v59, 24, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v22, 8, v14
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v26, 24, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v18
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 24, v20
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v1, 24, v24
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v25
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:84
|
|
; SI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 24, v28
|
|
; SI-NEXT: ; implicit-def: $vgpr14
|
|
; SI-NEXT: ; implicit-def: $vgpr24
|
|
; SI-NEXT: ; implicit-def: $vgpr28
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:124
|
|
; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB110_2
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 24, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
|
|
; SI-NEXT: v_or_b32_e32 v11, v13, v11
|
|
; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v11, v13, v11
|
|
; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v13
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v21, v14, v13
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
|
|
; SI-NEXT: v_or_b32_e32 v23, v13, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v27, v13, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v38
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr38
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v50, v13, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
|
|
; SI-NEXT: v_or_b32_e32 v52, v13, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v53, v36, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr36
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v51
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr51
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v41, v48, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr48
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v44, v13, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v45, v49, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v13
|
|
; SI-NEXT: ; implicit-def: $vgpr49
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v42
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr42
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v57, v54, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr54
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v58, v13, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 24, v25
|
|
; SI-NEXT: ; implicit-def: $vgpr25
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v61, v40, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v37
|
|
; SI-NEXT: v_or_b32_e32 v11, v11, v60
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v11
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
|
|
; SI-NEXT: ; implicit-def: $vgpr37
|
|
; SI-NEXT: ; implicit-def: $vgpr40
|
|
; SI-NEXT: ; implicit-def: $vgpr60
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v31, v47, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v39
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v32, v13, v11
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v20
|
|
; SI-NEXT: v_or_b32_e32 v13, v13, v22
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v17
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v3, v13
|
|
; SI-NEXT: v_and_b32_e32 v3, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_or_b32_e32 v33, v0, v3
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v30, v26, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v43
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v24, v16, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v3, 24, v63
|
|
; SI-NEXT: v_or_b32_e32 v28, v3, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v56
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v15, v1, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v12
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v0
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: v_or_b32_e32 v19, v8, v0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v18
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: v_or_b32_e32 v11, v59, v11
|
|
; SI-NEXT: ; kill: killed $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr39
|
|
; SI-NEXT: ; implicit-def: $vgpr18
|
|
; SI-NEXT: ; implicit-def: $vgpr20
|
|
; SI-NEXT: ; implicit-def: $vgpr17
|
|
; SI-NEXT: ; implicit-def: $vgpr9
|
|
; SI-NEXT: ; implicit-def: $vgpr0
|
|
; SI-NEXT: ; implicit-def: $vgpr5
|
|
; SI-NEXT: ; implicit-def: $vgpr7
|
|
; SI-NEXT: ; implicit-def: $vgpr43
|
|
; SI-NEXT: ; implicit-def: $vgpr10
|
|
; SI-NEXT: ; implicit-def: $vgpr63
|
|
; SI-NEXT: ; implicit-def: $vgpr56
|
|
; SI-NEXT: ; implicit-def: $vgpr12
|
|
; SI-NEXT: ; implicit-def: $vgpr4
|
|
; SI-NEXT: ; kill: killed $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr47
|
|
; SI-NEXT: ; implicit-def: $vgpr59
|
|
; SI-NEXT: ; implicit-def: $vgpr22
|
|
; SI-NEXT: ; implicit-def: $vgpr3
|
|
; SI-NEXT: ; implicit-def: $vgpr26
|
|
; SI-NEXT: ; implicit-def: $vgpr6
|
|
; SI-NEXT: ; implicit-def: $vgpr16
|
|
; SI-NEXT: ; implicit-def: $vgpr1
|
|
; SI-NEXT: ; implicit-def: $vgpr2
|
|
; SI-NEXT: ; implicit-def: $vgpr8
|
|
; SI-NEXT: .LBB110_2: ; %Flow
|
|
; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; SI-NEXT: s_cbranch_execz .LBB110_4
|
|
; SI-NEXT: ; %bb.3: ; %cmp.true
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v12
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4
|
|
; SI-NEXT: v_or_b32_e32 v2, v2, v11
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, 0x300, v2
|
|
; SI-NEXT: v_or_b32_e32 v4, v8, v4
|
|
; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; SI-NEXT: v_or_b32_e32 v2, v4, v2
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v10
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v63
|
|
; SI-NEXT: v_or_b32_e32 v4, v8, v4
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v56
|
|
; SI-NEXT: s_movk_i32 s6, 0x300
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v8
|
|
; SI-NEXT: v_or_b32_e32 v1, v1, v4
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v7
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v43
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; SI-NEXT: v_or_b32_e32 v6, v16, v6
|
|
; SI-NEXT: v_or_b32_e32 v4, v6, v4
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v9
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5
|
|
; SI-NEXT: v_or_b32_e32 v0, v0, v6
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s6, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; SI-NEXT: v_or_b32_e32 v5, v26, v5
|
|
; SI-NEXT: v_or_b32_e32 v0, v5, v0
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v20
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v17
|
|
; SI-NEXT: v_or_b32_e32 v5, v22, v5
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v6
|
|
; SI-NEXT: v_or_b32_e32 v3, v3, v5
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v39
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xff, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v25
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v18
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; SI-NEXT: v_or_b32_e32 v6, v59, v6
|
|
; SI-NEXT: v_or_b32_e32 v5, v6, v5
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v37
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xff, v6
|
|
; SI-NEXT: v_or_b32_e32 v6, v60, v6
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s6, v6
|
|
; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b32 s7, 0x3000000
|
|
; SI-NEXT: v_add_i32_e32 v2, vcc, s7, v2
|
|
; SI-NEXT: v_add_i32_e32 v1, vcc, s7, v1
|
|
; SI-NEXT: v_add_i32_e32 v4, vcc, s7, v4
|
|
; SI-NEXT: v_add_i32_e32 v0, vcc, s7, v0
|
|
; SI-NEXT: v_add_i32_e32 v3, vcc, s7, v3
|
|
; SI-NEXT: v_add_i32_e32 v5, vcc, s7, v5
|
|
; SI-NEXT: v_lshlrev_b32_e32 v32, 16, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v47, v7
|
|
; SI-NEXT: v_or_b32_e32 v6, v7, v6
|
|
; SI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 8, v8
|
|
; SI-NEXT: v_add_i32_e32 v6, vcc, s7, v6
|
|
; SI-NEXT: v_and_b32_e32 v31, 0xffff0000, v6
|
|
; SI-NEXT: v_lshlrev_b32_e32 v62, 16, v6
|
|
; SI-NEXT: v_and_b32_e32 v30, 0xffff0000, v0
|
|
; SI-NEXT: v_lshlrev_b32_e32 v33, 16, v0
|
|
; SI-NEXT: v_and_b32_e32 v24, 0xffff0000, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v34, 16, v4
|
|
; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v1
|
|
; SI-NEXT: v_and_b32_e32 v19, 0xffff0000, v2
|
|
; SI-NEXT: v_lshlrev_b32_e32 v35, 16, v2
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v54, v9
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 8, v10
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v48, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 8, v12
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xff, v7
|
|
; SI-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s6, v7
|
|
; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v40, v8
|
|
; SI-NEXT: v_or_b32_e32 v7, v8, v7
|
|
; SI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v7, vcc, s7, v7
|
|
; SI-NEXT: v_and_b32_e32 v61, 0xffff0000, v7
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 8, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v58, 16, v7
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v42, v8
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s6, v8
|
|
; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; SI-NEXT: v_or_b32_e32 v8, v9, v8
|
|
; SI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v8, vcc, s7, v8
|
|
; SI-NEXT: v_and_b32_e32 v57, 0xffff0000, v8
|
|
; SI-NEXT: v_lshlrev_b32_e32 v46, 16, v8
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xff, v9
|
|
; SI-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s6, v9
|
|
; SI-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v49, v10
|
|
; SI-NEXT: v_or_b32_e32 v9, v10, v9
|
|
; SI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v9, vcc, s7, v9
|
|
; SI-NEXT: v_and_b32_e32 v45, 0xffff0000, v9
|
|
; SI-NEXT: v_lshlrev_b32_e32 v44, 16, v9
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v51, v10
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s6, v10
|
|
; SI-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; SI-NEXT: v_or_b32_e32 v10, v11, v10
|
|
; SI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v10, vcc, s7, v10
|
|
; SI-NEXT: v_and_b32_e32 v41, 0xffff0000, v10
|
|
; SI-NEXT: v_lshlrev_b32_e32 v55, 16, v10
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xff, v11
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s6, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v36, v12
|
|
; SI-NEXT: v_or_b32_e32 v11, v12, v11
|
|
; SI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v11, vcc, s7, v11
|
|
; SI-NEXT: v_and_b32_e32 v53, 0xffff0000, v11
|
|
; SI-NEXT: v_lshlrev_b32_e32 v52, 16, v11
|
|
; SI-NEXT: v_and_b32_e32 v11, 0xffff0000, v5
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v38, v12
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s6, v12
|
|
; SI-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; SI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; SI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v12, vcc, s7, v12
|
|
; SI-NEXT: v_and_b32_e32 v50, 0xffff0000, v12
|
|
; SI-NEXT: v_lshlrev_b32_e32 v29, 16, v12
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xff, v13
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s6, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; SI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v13, vcc, s7, v13
|
|
; SI-NEXT: v_and_b32_e32 v27, 0xffff0000, v13
|
|
; SI-NEXT: v_lshlrev_b32_e32 v23, 16, v13
|
|
; SI-NEXT: v_and_b32_e32 v13, 0xffff0000, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xff, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s6, v14
|
|
; SI-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; SI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v14, vcc, s7, v14
|
|
; SI-NEXT: v_and_b32_e32 v21, 0xffff0000, v14
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v3
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 8, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, s6, v15
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff, v15
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xff, v16
|
|
; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; SI-NEXT: v_or_b32_e32 v16, v17, v16
|
|
; SI-NEXT: v_or_b32_e32 v15, v16, v15
|
|
; SI-NEXT: v_add_i32_e32 v15, vcc, s7, v15
|
|
; SI-NEXT: v_and_b32_e32 v16, 0xffff0000, v15
|
|
; SI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_and_b32_e32 v15, 0xffff0000, v1
|
|
; SI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
|
|
; SI-NEXT: .LBB110_4: ; %end
|
|
; SI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; SI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v23
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v29
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v52
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v55
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v44
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v46
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v58
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v62
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v14
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v34
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_mul_f32_e32 v16, 1.0, v35
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
|
|
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
|
|
; SI-NEXT: v_alignbit_b32 v0, v0, v1, 16
|
|
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v21
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
|
|
; SI-NEXT: v_alignbit_b32 v1, v1, v2, 16
|
|
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v27
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
|
; SI-NEXT: v_alignbit_b32 v2, v2, v3, 16
|
|
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
|
|
; SI-NEXT: v_alignbit_b32 v3, v3, v4, 16
|
|
; SI-NEXT: v_mul_f32_e32 v4, 1.0, v53
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 16
|
|
; SI-NEXT: v_mul_f32_e32 v5, 1.0, v41
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
; SI-NEXT: v_alignbit_b32 v5, v5, v6, 16
|
|
; SI-NEXT: v_mul_f32_e32 v6, 1.0, v45
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v6
|
|
; SI-NEXT: v_alignbit_b32 v6, v6, v7, 16
|
|
; SI-NEXT: v_mul_f32_e32 v7, 1.0, v57
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v7
|
|
; SI-NEXT: v_alignbit_b32 v7, v7, v8, 16
|
|
; SI-NEXT: v_mul_f32_e32 v8, 1.0, v61
|
|
; SI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v8
|
|
; SI-NEXT: v_alignbit_b32 v8, v8, v9, 16
|
|
; SI-NEXT: v_mul_f32_e32 v9, 1.0, v31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v9
|
|
; SI-NEXT: v_alignbit_b32 v9, v9, v10, 16
|
|
; SI-NEXT: v_mul_f32_e32 v10, 1.0, v11
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v10
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v32
|
|
; SI-NEXT: v_alignbit_b32 v10, v10, v11, 16
|
|
; SI-NEXT: v_mul_f32_e32 v11, 1.0, v13
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v11
|
|
; SI-NEXT: v_alignbit_b32 v11, v11, v12, 16
|
|
; SI-NEXT: v_mul_f32_e32 v12, 1.0, v30
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v12
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v33
|
|
; SI-NEXT: v_alignbit_b32 v12, v12, v13, 16
|
|
; SI-NEXT: v_mul_f32_e32 v13, 1.0, v24
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v13
|
|
; SI-NEXT: v_alignbit_b32 v13, v13, v14, 16
|
|
; SI-NEXT: v_mul_f32_e32 v14, 1.0, v15
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v14
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v28
|
|
; SI-NEXT: v_alignbit_b32 v14, v14, v15, 16
|
|
; SI-NEXT: v_mul_f32_e32 v15, 1.0, v19
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v15
|
|
; SI-NEXT: v_alignbit_b32 v15, v15, v16, 16
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v32bf16:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; VI-NEXT: buffer_load_ushort v55, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:128
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:124
|
|
; VI-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:120
|
|
; VI-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:116
|
|
; VI-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:112
|
|
; VI-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:108
|
|
; VI-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:104
|
|
; VI-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:100
|
|
; VI-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:96
|
|
; VI-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:92
|
|
; VI-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:88
|
|
; VI-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:84
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:80
|
|
; VI-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: v_mov_b32_e32 v17, v14
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB110_2
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
|
|
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; kill: killed $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr18
|
|
; VI-NEXT: ; implicit-def: $vgpr19
|
|
; VI-NEXT: ; implicit-def: $vgpr22
|
|
; VI-NEXT: ; implicit-def: $vgpr23
|
|
; VI-NEXT: ; implicit-def: $vgpr26
|
|
; VI-NEXT: ; implicit-def: $vgpr27
|
|
; VI-NEXT: ; implicit-def: $vgpr30
|
|
; VI-NEXT: ; implicit-def: $vgpr55
|
|
; VI-NEXT: ; implicit-def: $vgpr44
|
|
; VI-NEXT: ; implicit-def: $vgpr42
|
|
; VI-NEXT: ; implicit-def: $vgpr57
|
|
; VI-NEXT: ; implicit-def: $vgpr46
|
|
; VI-NEXT: ; implicit-def: $vgpr58
|
|
; VI-NEXT: ; implicit-def: $vgpr47
|
|
; VI-NEXT: ; implicit-def: $vgpr33
|
|
; VI-NEXT: ; implicit-def: $vgpr62
|
|
; VI-NEXT: ; implicit-def: $vgpr35
|
|
; VI-NEXT: ; implicit-def: $vgpr34
|
|
; VI-NEXT: ; implicit-def: $vgpr49
|
|
; VI-NEXT: ; implicit-def: $vgpr48
|
|
; VI-NEXT: ; implicit-def: $vgpr51
|
|
; VI-NEXT: ; implicit-def: $vgpr50
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v0, v1, v0, s6
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: ; implicit-def: $vgpr17
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v11
|
|
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
|
|
; VI-NEXT: v_or_b32_e32 v12, v12, v13
|
|
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
|
|
; VI-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
|
|
; VI-NEXT: v_perm_b32 v16, v32, v54, s6
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v15
|
|
; VI-NEXT: v_perm_b32 v15, v53, v52, s6
|
|
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; kill: killed $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr16
|
|
; VI-NEXT: ; implicit-def: $vgpr20
|
|
; VI-NEXT: ; implicit-def: $vgpr21
|
|
; VI-NEXT: ; implicit-def: $vgpr24
|
|
; VI-NEXT: ; implicit-def: $vgpr25
|
|
; VI-NEXT: ; implicit-def: $vgpr28
|
|
; VI-NEXT: ; implicit-def: $vgpr29
|
|
; VI-NEXT: ; implicit-def: $vgpr41
|
|
; VI-NEXT: ; implicit-def: $vgpr40
|
|
; VI-NEXT: ; implicit-def: $vgpr45
|
|
; VI-NEXT: ; implicit-def: $vgpr43
|
|
; VI-NEXT: ; implicit-def: $vgpr61
|
|
; VI-NEXT: ; implicit-def: $vgpr60
|
|
; VI-NEXT: ; implicit-def: $vgpr59
|
|
; VI-NEXT: ; implicit-def: $vgpr56
|
|
; VI-NEXT: ; implicit-def: $vgpr31
|
|
; VI-NEXT: ; implicit-def: $vgpr63
|
|
; VI-NEXT: ; implicit-def: $vgpr37
|
|
; VI-NEXT: ; implicit-def: $vgpr36
|
|
; VI-NEXT: ; implicit-def: $vgpr39
|
|
; VI-NEXT: ; implicit-def: $vgpr38
|
|
; VI-NEXT: ; implicit-def: $vgpr53
|
|
; VI-NEXT: ; implicit-def: $vgpr52
|
|
; VI-NEXT: ; implicit-def: $vgpr32
|
|
; VI-NEXT: ; implicit-def: $vgpr54
|
|
; VI-NEXT: .LBB110_2: ; %Flow
|
|
; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; VI-NEXT: s_cbranch_execz .LBB110_4
|
|
; VI-NEXT: ; %bb.3: ; %cmp.true
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v32
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v54
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v53
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v52
|
|
; VI-NEXT: v_or_b32_sdwa v15, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v1, 3, v51
|
|
; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v50
|
|
; VI-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v39
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v38
|
|
; VI-NEXT: v_or_b32_sdwa v14, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(12)
|
|
; VI-NEXT: v_add_u16_e32 v2, 3, v49
|
|
; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v48
|
|
; VI-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_mov_b32_e32 v3, 0x300
|
|
; VI-NEXT: v_add_u16_sdwa v32, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_sdwa v38, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(10)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v37
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v36
|
|
; VI-NEXT: v_or_b32_sdwa v36, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(8)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v35
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v34
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v12, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(6)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v31
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v63
|
|
; VI-NEXT: v_or_b32_sdwa v31, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v33
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v62
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v11, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v59
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v56
|
|
; VI-NEXT: v_or_b32_sdwa v33, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v58
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v47
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v10, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v61
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v60
|
|
; VI-NEXT: v_or_b32_sdwa v34, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v57
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v46
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v9, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v45
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v43
|
|
; VI-NEXT: v_or_b32_sdwa v35, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v44
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v42
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v8, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v41
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v40
|
|
; VI-NEXT: v_or_b32_sdwa v37, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v30
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v55
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v7, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v28
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v29
|
|
; VI-NEXT: v_or_b32_sdwa v28, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v26
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v27
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v6, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v24
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v25
|
|
; VI-NEXT: v_or_b32_sdwa v24, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v22
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v23
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v5, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v20
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v21
|
|
; VI-NEXT: v_or_b32_sdwa v20, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v18
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v19
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_sdwa v4, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v16
|
|
; VI-NEXT: v_add_u16_sdwa v13, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: v_add_u16_e32 v14, 0x300, v14
|
|
; VI-NEXT: v_add_u16_e32 v15, 0x300, v15
|
|
; VI-NEXT: v_or_b32_e32 v14, v14, v38
|
|
; VI-NEXT: v_or_b32_e32 v15, v15, v32
|
|
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v16, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v17
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v16
|
|
; VI-NEXT: v_or_b32_e32 v4, v16, v4
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v20
|
|
; VI-NEXT: v_or_b32_e32 v5, v16, v5
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v24
|
|
; VI-NEXT: v_or_b32_e32 v6, v16, v6
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v28
|
|
; VI-NEXT: v_or_b32_e32 v7, v16, v7
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v37
|
|
; VI-NEXT: v_or_b32_e32 v8, v16, v8
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v35
|
|
; VI-NEXT: v_or_b32_e32 v9, v16, v9
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v34
|
|
; VI-NEXT: v_or_b32_e32 v10, v16, v10
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v33
|
|
; VI-NEXT: v_or_b32_e32 v11, v16, v11
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v31
|
|
; VI-NEXT: v_or_b32_e32 v12, v16, v12
|
|
; VI-NEXT: v_add_u16_e32 v16, 0x300, v36
|
|
; VI-NEXT: v_or_b32_e32 v13, v16, v13
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v21, 8, v21
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v17, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v18, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v2, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v19, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; VI-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v1, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: v_or_b32_sdwa v21, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; VI-NEXT: v_or_b32_sdwa v0, v22, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
|
|
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(1)
|
|
; VI-NEXT: v_add_u16_e32 v3, 3, v3
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; VI-NEXT: v_or_b32_sdwa v3, v22, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v21
|
|
; VI-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v19
|
|
; VI-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; VI-NEXT: v_add_u16_e32 v3, 0x300, v18
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v17
|
|
; VI-NEXT: .LBB110_4: ; %end
|
|
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; VI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v32bf16:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:124
|
|
; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:120
|
|
; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:116
|
|
; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, v12
|
|
; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:132
|
|
; GFX9-NEXT: s_nop 0
|
|
; GFX9-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v2, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:80
|
|
; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:96
|
|
; GFX9-NEXT: buffer_load_ushort v10, off, s[0:3], s32 offset:104
|
|
; GFX9-NEXT: buffer_load_ushort v11, off, s[0:3], s32 offset:112
|
|
; GFX9-NEXT: buffer_load_ushort v12, off, s[0:3], s32 offset:128
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:108
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:100
|
|
; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:92
|
|
; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:88
|
|
; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:84
|
|
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: s_waitcnt vmcnt(23)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(22)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v56, 8, v1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(21)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v45, 8, v2
|
|
; GFX9-NEXT: s_waitcnt vmcnt(20)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v61, 8, v3
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v38, 8, v4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(18)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v33, 8, v5
|
|
; GFX9-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v37, 8, v6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v51, 8, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(15)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v35, 8, v8
|
|
; GFX9-NEXT: s_waitcnt vmcnt(14)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v50, 8, v9
|
|
; GFX9-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v49, 8, v10
|
|
; GFX9-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v39, 8, v11
|
|
; GFX9-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v32, 8, v12
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB110_2
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_mov_b32 s6, 0xc0c0004
|
|
; GFX9-NEXT: s_mov_b32 s7, 0x5040100
|
|
; GFX9-NEXT: v_perm_b32 v6, v22, v23, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v26, v27, s6
|
|
; GFX9-NEXT: v_perm_b32 v8, v30, v36, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v47, v45 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v10, v63, v62, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v55, v33 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v12, v42, v41, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v43, v35 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v14, v58, v57, s6
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v34, v39 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: ; implicit-def: $vgpr22
|
|
; GFX9-NEXT: ; implicit-def: $vgpr23
|
|
; GFX9-NEXT: ; implicit-def: $vgpr26
|
|
; GFX9-NEXT: ; implicit-def: $vgpr27
|
|
; GFX9-NEXT: ; implicit-def: $vgpr30
|
|
; GFX9-NEXT: ; implicit-def: $vgpr36
|
|
; GFX9-NEXT: ; implicit-def: $vgpr47
|
|
; GFX9-NEXT: ; implicit-def: $vgpr63
|
|
; GFX9-NEXT: ; implicit-def: $vgpr62
|
|
; GFX9-NEXT: ; implicit-def: $vgpr55
|
|
; GFX9-NEXT: ; implicit-def: $vgpr42
|
|
; GFX9-NEXT: ; implicit-def: $vgpr41
|
|
; GFX9-NEXT: ; implicit-def: $vgpr43
|
|
; GFX9-NEXT: ; implicit-def: $vgpr58
|
|
; GFX9-NEXT: ; implicit-def: $vgpr57
|
|
; GFX9-NEXT: ; implicit-def: $vgpr34
|
|
; GFX9-NEXT: ; implicit-def: $vgpr45
|
|
; GFX9-NEXT: ; implicit-def: $vgpr33
|
|
; GFX9-NEXT: ; implicit-def: $vgpr35
|
|
; GFX9-NEXT: ; implicit-def: $vgpr39
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; GFX9-NEXT: v_perm_b32 v1, v3, v2, s7
|
|
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
|
|
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s7
|
|
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s6
|
|
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_perm_b32 v3, v19, v3, s6
|
|
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s7
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v17, s6
|
|
; GFX9-NEXT: v_perm_b32 v16, v52, v54, s6
|
|
; GFX9-NEXT: ; implicit-def: $vgpr19
|
|
; GFX9-NEXT: ; implicit-def: $vgpr17
|
|
; GFX9-NEXT: ; implicit-def: $vgpr52
|
|
; GFX9-NEXT: ; implicit-def: $vgpr54
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_perm_b32 v5, v18, v5, s6
|
|
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s7
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v21, s6
|
|
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s7
|
|
; GFX9-NEXT: v_perm_b32 v6, v24, v25, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s7
|
|
; GFX9-NEXT: v_perm_b32 v7, v28, v29, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v8, v59, v56 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v60, v61 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v9, v9, v10, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v48, v38 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v10, v11, v10, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v11, v40, v37 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v11, v11, v12, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v12, v44, v51 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v12, v13, v12, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v13, v46, v50 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v13, v13, v14, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v14, v31, v49 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s7
|
|
; GFX9-NEXT: v_or_b32_sdwa v15, v53, v32 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_perm_b32 v15, v15, v16, s7
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; kill: killed $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr16
|
|
; GFX9-NEXT: ; implicit-def: $vgpr18
|
|
; GFX9-NEXT: ; kill: killed $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr20
|
|
; GFX9-NEXT: ; implicit-def: $vgpr21
|
|
; GFX9-NEXT: ; implicit-def: $vgpr24
|
|
; GFX9-NEXT: ; implicit-def: $vgpr25
|
|
; GFX9-NEXT: ; implicit-def: $vgpr28
|
|
; GFX9-NEXT: ; implicit-def: $vgpr29
|
|
; GFX9-NEXT: ; implicit-def: $vgpr59
|
|
; GFX9-NEXT: ; implicit-def: $vgpr60
|
|
; GFX9-NEXT: ; implicit-def: $vgpr48
|
|
; GFX9-NEXT: ; implicit-def: $vgpr40
|
|
; GFX9-NEXT: ; implicit-def: $vgpr44
|
|
; GFX9-NEXT: ; implicit-def: $vgpr46
|
|
; GFX9-NEXT: ; implicit-def: $vgpr31
|
|
; GFX9-NEXT: ; implicit-def: $vgpr53
|
|
; GFX9-NEXT: ; implicit-def: $vgpr56
|
|
; GFX9-NEXT: ; implicit-def: $vgpr61
|
|
; GFX9-NEXT: ; implicit-def: $vgpr38
|
|
; GFX9-NEXT: ; implicit-def: $vgpr37
|
|
; GFX9-NEXT: ; implicit-def: $vgpr51
|
|
; GFX9-NEXT: ; implicit-def: $vgpr50
|
|
; GFX9-NEXT: ; implicit-def: $vgpr49
|
|
; GFX9-NEXT: ; implicit-def: $vgpr32
|
|
; GFX9-NEXT: .LBB110_2: ; %Flow
|
|
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]
|
|
; GFX9-NEXT: s_cbranch_execz .LBB110_4
|
|
; GFX9-NEXT: ; %bb.3: ; %cmp.true
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v52
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v54
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 3, v53
|
|
; GFX9-NEXT: v_or_b32_sdwa v1, v32, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(9)
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 3, v31
|
|
; GFX9-NEXT: v_add_u16_e32 v15, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v31, 0x300, v1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v58
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v57
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v13, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v46
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v50, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 3, v34
|
|
; GFX9-NEXT: v_add_u16_e32 v34, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v44
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v51, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v12, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v43
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v35, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v35, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v42
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v41
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v11, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v40
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v37, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v37, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v48
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v38, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v10, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v55
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v33, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v33, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v63
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v62
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v9, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v60
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v61, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v38, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v59
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v56, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v8, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v47
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v45, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_or_b32_sdwa v3, v39, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v39, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v28
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v29
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v7, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v30
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v36
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v28, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v24
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v25
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v6, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v26
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v27
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v24, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v20
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v5, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v22
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v23
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v20, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v16
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v17
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v4, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v18
|
|
; GFX9-NEXT: v_add_u16_e32 v32, 0x300, v3
|
|
; GFX9-NEXT: v_or_b32_sdwa v2, v49, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v14, 0x300, v2
|
|
; GFX9-NEXT: s_mov_b32 s6, 0x5040100
|
|
; GFX9-NEXT: v_perm_b32 v5, v20, v5, s6
|
|
; GFX9-NEXT: v_perm_b32 v6, v24, v6, s6
|
|
; GFX9-NEXT: v_perm_b32 v7, v28, v7, s6
|
|
; GFX9-NEXT: v_perm_b32 v8, v39, v8, s6
|
|
; GFX9-NEXT: v_perm_b32 v9, v38, v9, s6
|
|
; GFX9-NEXT: v_perm_b32 v10, v33, v10, s6
|
|
; GFX9-NEXT: v_perm_b32 v11, v37, v11, s6
|
|
; GFX9-NEXT: v_perm_b32 v12, v35, v12, s6
|
|
; GFX9-NEXT: v_perm_b32 v13, v34, v13, s6
|
|
; GFX9-NEXT: v_perm_b32 v14, v32, v14, s6
|
|
; GFX9-NEXT: v_perm_b32 v15, v31, v15, s6
|
|
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v16, 0x300, v0
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v19
|
|
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v4, v16, v4, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v21, 8, v21
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v22, 8, v22
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v3, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(2)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v19, 8, v19
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v17, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v3, v17, v3, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v2, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v18, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v2, v18, v2, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v1, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v19, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v19, 0x300, v0
|
|
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_perm_b32 v1, v19, v1, s6
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 3, v0
|
|
; GFX9-NEXT: v_or_b32_sdwa v0, v21, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: v_add_u16_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u16_e32 v21, 3, v21
|
|
; GFX9-NEXT: v_or_b32_sdwa v21, v22, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
|
; GFX9-NEXT: v_add_u16_e32 v21, 0x300, v21
|
|
; GFX9-NEXT: v_perm_b32 v0, v21, v0, s6
|
|
; GFX9-NEXT: .LBB110_4: ; %end
|
|
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
|
|
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32bf16:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1f
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v37, off, s32 offset:128
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v33, off, s32 offset:124
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:120
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:116
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v38, off, s32 offset:112
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v31, off, s32 offset:108
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v39, off, s32 offset:104
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:100
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v48, off, s32 offset:96
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v32, off, s32 offset:92
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:88
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:84
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v49, off, s32 offset:80
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:76
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v50, off, s32 offset:72
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:68
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v100, off, s32 offset:132
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v51, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v52, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v53, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v54, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v55, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v64, off, s32 offset:64
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v35, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v36, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: s_clause 0x1
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_hi_b16 v34, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v30.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v29.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v70.l, v27.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v26.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v25.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v24.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v23.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v22.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v21.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v71.l, v20.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v19.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v69.l, v18.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v39.l, v17.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v48.l, v15.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v64.l, v14.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v13.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v12.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v11.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v9.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v6.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v5.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v4.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v0.l
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.h, 8, v37.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.h, 8, v38.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v21.l, 8, v39.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v20.l, 8, v48.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.h, 8, v49.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.h, 8, v50.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v51.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.h, 8, v52.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v53.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v54.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v55.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v19.l, 8, v64.h
|
|
; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v100
|
|
; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB110_3
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB110_4
|
|
; GFX11-TRUE16-NEXT: .LBB110_2: ; %end
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB110_3: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v28, v24, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v27, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v30, v23, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v69, v54, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v64, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v70, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v26, v22, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v82, v68, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v51, v29, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v87, v80, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v9.l, 0xff, v35.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v25, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v4.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v55, v39, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.h, 0xff, v36.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v67, v38, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v96, v83, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.h, 0xff, v32.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v71, v65, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.l, 0xff, v34.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v14.l, 0xff, v33.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v86, v81, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v9.l, v17.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v10.h, 0xff, v36.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v11.l, 0xff, v35.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v11.h, v19.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v12.h, 0xff, v32.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v13.l, 0xff, v31.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v13.h, v20.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.l, 0xff, v33.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v15.h, 0xff, v31.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v8.h, 0xff, v34.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v8.l, v16.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v14.l, v21.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v97, v84, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.l, v10.h, v18.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v10.h, v11.l, v17.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v99, v98, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v12.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.l, v12.h, v19.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v12.h, v13.l, v18.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v49, v37, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v14.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.l, v15.l, v21.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v14.h, v15.h, v20.h
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v66, v53, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v8.h, v16.h
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr26_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr22_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr28_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr24_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr52_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr25_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr30_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr23_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr51_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr29_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr50_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr27_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr67_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr38_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr64_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr48_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr55_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr39_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr69_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr54_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr71_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr65_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr82_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr68_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr96_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr83_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr85_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr70_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr86_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr81_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr87_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr80_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr34_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr97_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr84_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr35_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr99_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr98_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr36_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr49_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr37_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr32_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr31_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr66_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr53_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr33_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr16_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr17_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr19_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr18_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_lo16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr20_hi16
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21_hi16
|
|
; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB110_2
|
|
; GFX11-TRUE16-NEXT: .LBB110_4: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v66.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v33.h, 3
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v53.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v33.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v31.h, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v49.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, v82.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v21.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v32.h, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v21.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v15.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v20.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v37.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v32.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.l, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v14.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v20.l, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v31.l, 3
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v99.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v13.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v36.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v98.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v36.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v18.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v2.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v35.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v12.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v19.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.l, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v18.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v97.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v11.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v35.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v17.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v84.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v34.h, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v34.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v10.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v17.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v86.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v9.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v16.l, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.h, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v81.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v87.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v96.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v8.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v80.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v83.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v85.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v71.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v70.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v65.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v7.h, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v68.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v55.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v6.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, v69.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v39.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v54.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v5.h, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v67.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v1.h, v1.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v64.l, 3
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v2.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, v51.l, 3
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v38.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v48.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.h, 8, v29.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.l, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v2.h, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.l, v3.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v4.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v3.h, v2.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v50.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, v52.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, v26.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.l, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, v30.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v16.h, v28.l, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v3.h, 0x300, v1.l
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v27.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v16.l, 8, v25.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.l, 8, v23.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v2.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v17.h, 8, v22.l
|
|
; GFX11-TRUE16-NEXT: v_and_b16 v16.h, 0xff, v16.h
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v18.l, 8, v24.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v0.h, v16.l, v0.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v1.h, v17.l, v1.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.l, v17.h, v2.h
|
|
; GFX11-TRUE16-NEXT: v_or_b16 v16.h, v18.l, v16.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v2.h, 0x300, v0.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, 0x300, v0.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.h, 0x300, v1.h
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.l, 0x300, v16.l
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u16 v0.h, 0x300, v16.h
|
|
; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32bf16:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, v15 :: v_dual_mov_b32 v33, v12
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, v14 :: v_dual_mov_b32 v37, v11
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, v13 :: v_dual_mov_b32 v49, v10
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, v9 :: v_dual_mov_b32 v34, v6
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, v8 :: v_dual_mov_b32 v32, v3
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, v7 :: v_dual_mov_b32 v36, v2
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, v5 :: v_dual_mov_b32 v38, v0
|
|
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, v4 :: v_dual_mov_b32 v50, v1
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1f
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v0, off, s32 offset:128
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v100, off, s32 offset:124
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v87, off, s32 offset:120
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v99, off, s32 offset:116
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s32 offset:112
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v86, off, s32 offset:108
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s32 offset:104
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v102, off, s32 offset:100
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v3, off, s32 offset:96
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v82, off, s32 offset:92
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v64, off, s32 offset:88
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v81, off, s32 offset:84
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v4, off, s32 offset:80
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v68, off, s32 offset:76
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v5, off, s32 offset:72
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v85, off, s32 offset:68
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v6, off, s32 offset:132
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v7, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v8, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v9, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v10, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v11, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v12, off, s32 offset:64
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v98, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v71, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v97, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v96, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v101, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v70, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v67, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v69, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v66, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: s_clause 0x1
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v83, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v55, off, s32
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(33)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v119, 8, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(29)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v117, 8, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(27)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v118, 8, v2
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(25)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v115, 8, v3
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(21)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v114, 8, v4
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v116, 8, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(17)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v84, 8, v7
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(15)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v65, 8, v8
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(14)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v80, 8, v9
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(13)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v112, 8, v10
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v113, 8, v11
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(11)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v103, 8, v12
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB110_3
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB110_4
|
|
; GFX11-FAKE16-NEXT: .LBB110_2: ; %end
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB110_3: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v38, v50, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v36, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v51, v39, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v34, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v31, v53, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v49, v37, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v33, v52, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v54, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v16, v17, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v18, v19, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v21, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v22, v23, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v25, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v26, v27, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v28, v29, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v30, v55, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v83
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v5, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v7, v6, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v9, v8, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v11, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v66
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v84
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v101
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v96
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v70
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v65
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v69, v67, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v112
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v113
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v80
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v8, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v98
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v82
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v12, v11, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v68
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v9, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v85
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v86
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v100
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v11, v114
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v102
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v103
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v97, v71, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v116
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v115
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v81, v64, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v11, v118
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v17, v117
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v18, v119
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v99, v87, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v12, v14, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v16, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v15, v19, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v17, v20, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v18, v21, 0x5040100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr38
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr50
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr36
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr32
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr51
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr39
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr34
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr35
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr31
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr53
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr49
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr37
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr33
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr52
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr54
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr48
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr16
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr17
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr18
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr19
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr20
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr21
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr22
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr23
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr24
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr25
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr26
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr27
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr28
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr29
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr30
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr55
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr83
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr66
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr69
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr67
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr70
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr101
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr96
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr97
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr71
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr98
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr85
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr68
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr81
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr64
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr82
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr102
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr86
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr99
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr87
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr100
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr84
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr65
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr80
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr112
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr113
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr103
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr116
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr114
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr115
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr118
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr117
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr119
|
|
; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0
|
|
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB110_2
|
|
; GFX11-FAKE16-NEXT: .LBB110_4: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v99, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v100, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v87
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v102, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v86, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v81, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v23
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v119, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v118, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v82, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v81, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v64
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v85, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v117, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v68, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v115, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v64, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v116, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v97, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v68, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v98, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v114, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v71
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(6)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v101, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v96, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v71, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v103, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v69, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v69, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v112, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v113, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v67
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v83, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v67, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v66, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v28, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v80, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v84, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v29
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v30, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v65, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v55
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v24, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v26, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v25
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v27
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v20, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v22, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v4, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v16, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v21
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v5, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v6, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v16, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v18, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v33, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v31, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v52
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v54, 3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v53
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v16
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v48
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v18, v0
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v49, 3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v19, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v16, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v51, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v34, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v38, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v36, 3
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v39
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v21
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v50
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v32
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v35
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v37
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v23, v3
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v26, v21
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v27, v22
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v29, v18
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v30, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, 0x300, v18
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v22, v21, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v18, v3, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v16, v2, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v23, v19, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v26, v4, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v6, v5, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v20, v17, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v25, v7, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v24, v8, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v28, v9, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v67, v10, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v69, v11, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v71, v12, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v68, v13, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v64, v14, 0x5040100
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v81, v15, 0x5040100
|
|
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a, i32 inreg %b) #0 {
|
|
; SI-LABEL: bitcast_v64i8_to_v32bf16_scalar:
|
|
; SI: ; %bb.0:
|
|
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
|
|
; SI-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt expcnt(1)
|
|
; SI-NEXT: v_writelane_b32 v40, s34, 0
|
|
; SI-NEXT: v_writelane_b32 v40, s35, 1
|
|
; SI-NEXT: v_writelane_b32 v40, s36, 2
|
|
; SI-NEXT: v_writelane_b32 v40, s37, 3
|
|
; SI-NEXT: v_writelane_b32 v40, s38, 4
|
|
; SI-NEXT: v_writelane_b32 v40, s39, 5
|
|
; SI-NEXT: v_writelane_b32 v40, s48, 6
|
|
; SI-NEXT: v_writelane_b32 v40, s49, 7
|
|
; SI-NEXT: v_writelane_b32 v40, s50, 8
|
|
; SI-NEXT: v_writelane_b32 v40, s51, 9
|
|
; SI-NEXT: v_writelane_b32 v40, s52, 10
|
|
; SI-NEXT: v_writelane_b32 v40, s53, 11
|
|
; SI-NEXT: v_writelane_b32 v40, s54, 12
|
|
; SI-NEXT: v_writelane_b32 v40, s55, 13
|
|
; SI-NEXT: v_writelane_b32 v40, s64, 14
|
|
; SI-NEXT: v_writelane_b32 v40, s65, 15
|
|
; SI-NEXT: v_writelane_b32 v40, s66, 16
|
|
; SI-NEXT: v_writelane_b32 v40, s67, 17
|
|
; SI-NEXT: v_writelane_b32 v40, s68, 18
|
|
; SI-NEXT: v_writelane_b32 v40, s69, 19
|
|
; SI-NEXT: v_writelane_b32 v40, s70, 20
|
|
; SI-NEXT: v_writelane_b32 v40, s71, 21
|
|
; SI-NEXT: v_writelane_b32 v40, s80, 22
|
|
; SI-NEXT: v_writelane_b32 v40, s81, 23
|
|
; SI-NEXT: v_writelane_b32 v40, s82, 24
|
|
; SI-NEXT: v_writelane_b32 v40, s83, 25
|
|
; SI-NEXT: v_writelane_b32 v40, s84, 26
|
|
; SI-NEXT: v_writelane_b32 v40, s85, 27
|
|
; SI-NEXT: v_writelane_b32 v40, s86, 28
|
|
; SI-NEXT: v_writelane_b32 v40, s87, 29
|
|
; SI-NEXT: v_writelane_b32 v40, s96, 30
|
|
; SI-NEXT: v_writelane_b32 v40, s97, 31
|
|
; SI-NEXT: v_writelane_b32 v40, s98, 32
|
|
; SI-NEXT: v_writelane_b32 v40, s99, 33
|
|
; SI-NEXT: v_writelane_b32 v40, s30, 34
|
|
; SI-NEXT: v_writelane_b32 v40, s31, 35
|
|
; SI-NEXT: s_mov_b32 s6, s19
|
|
; SI-NEXT: v_readfirstlane_b32 s19, v28
|
|
; SI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76
|
|
; SI-NEXT: v_readfirstlane_b32 s8, v30
|
|
; SI-NEXT: v_readfirstlane_b32 s37, v29
|
|
; SI-NEXT: v_readfirstlane_b32 s47, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s56, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s13, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s14, v24
|
|
; SI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:72
|
|
; SI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:68
|
|
; SI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:64
|
|
; SI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:60
|
|
; SI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:56
|
|
; SI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:52
|
|
; SI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:48
|
|
; SI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44
|
|
; SI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:40
|
|
; SI-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:36
|
|
; SI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:32
|
|
; SI-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:28
|
|
; SI-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:24
|
|
; SI-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:20
|
|
; SI-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:16
|
|
; SI-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:12
|
|
; SI-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:8
|
|
; SI-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:4
|
|
; SI-NEXT: buffer_load_dword v51, off, s[0:3], s32
|
|
; SI-NEXT: ; implicit-def: $vgpr41 : SGPR spill to VGPR lane
|
|
; SI-NEXT: v_readfirstlane_b32 s75, v23
|
|
; SI-NEXT: s_waitcnt expcnt(0)
|
|
; SI-NEXT: v_writelane_b32 v41, s18, 0
|
|
; SI-NEXT: v_writelane_b32 v41, s6, 1
|
|
; SI-NEXT: v_writelane_b32 v41, s17, 2
|
|
; SI-NEXT: v_writelane_b32 v41, s16, 3
|
|
; SI-NEXT: v_writelane_b32 v41, s22, 4
|
|
; SI-NEXT: v_writelane_b32 v41, s23, 5
|
|
; SI-NEXT: v_writelane_b32 v41, s21, 6
|
|
; SI-NEXT: v_writelane_b32 v41, s20, 7
|
|
; SI-NEXT: v_writelane_b32 v41, s26, 8
|
|
; SI-NEXT: v_writelane_b32 v41, s27, 9
|
|
; SI-NEXT: v_writelane_b32 v41, s25, 10
|
|
; SI-NEXT: v_writelane_b32 v41, s24, 11
|
|
; SI-NEXT: v_writelane_b32 v41, s29, 12
|
|
; SI-NEXT: v_readfirstlane_b32 s76, v22
|
|
; SI-NEXT: v_readfirstlane_b32 s62, v21
|
|
; SI-NEXT: v_readfirstlane_b32 s63, v20
|
|
; SI-NEXT: v_readfirstlane_b32 s73, v19
|
|
; SI-NEXT: v_readfirstlane_b32 s74, v18
|
|
; SI-NEXT: v_readfirstlane_b32 s58, v17
|
|
; SI-NEXT: v_readfirstlane_b32 s59, v16
|
|
; SI-NEXT: v_readfirstlane_b32 s61, v15
|
|
; SI-NEXT: v_readfirstlane_b32 s72, v14
|
|
; SI-NEXT: v_readfirstlane_b32 s44, v13
|
|
; SI-NEXT: v_readfirstlane_b32 s45, v12
|
|
; SI-NEXT: v_readfirstlane_b32 s57, v11
|
|
; SI-NEXT: v_readfirstlane_b32 s60, v10
|
|
; SI-NEXT: v_readfirstlane_b32 s40, v9
|
|
; SI-NEXT: v_readfirstlane_b32 s41, v8
|
|
; SI-NEXT: v_readfirstlane_b32 s43, v7
|
|
; SI-NEXT: v_readfirstlane_b32 s46, v6
|
|
; SI-NEXT: v_readfirstlane_b32 s11, v5
|
|
; SI-NEXT: v_readfirstlane_b32 s12, v4
|
|
; SI-NEXT: v_readfirstlane_b32 s15, v3
|
|
; SI-NEXT: v_readfirstlane_b32 s42, v2
|
|
; SI-NEXT: v_readfirstlane_b32 s7, v1
|
|
; SI-NEXT: v_readfirstlane_b32 s10, v0
|
|
; SI-NEXT: v_writelane_b32 v41, s28, 13
|
|
; SI-NEXT: v_writelane_b32 v41, s7, 14
|
|
; SI-NEXT: s_waitcnt vmcnt(14)
|
|
; SI-NEXT: v_readfirstlane_b32 s87, v24
|
|
; SI-NEXT: v_readfirstlane_b32 s86, v25
|
|
; SI-NEXT: v_readfirstlane_b32 s98, v26
|
|
; SI-NEXT: v_readfirstlane_b32 s99, v27
|
|
; SI-NEXT: v_readfirstlane_b32 s82, v29
|
|
; SI-NEXT: s_waitcnt vmcnt(13)
|
|
; SI-NEXT: v_readfirstlane_b32 s81, v30
|
|
; SI-NEXT: s_waitcnt vmcnt(12)
|
|
; SI-NEXT: v_readfirstlane_b32 s84, v31
|
|
; SI-NEXT: s_waitcnt vmcnt(11)
|
|
; SI-NEXT: v_readfirstlane_b32 s85, v32
|
|
; SI-NEXT: s_waitcnt vmcnt(10)
|
|
; SI-NEXT: v_readfirstlane_b32 s68, v33
|
|
; SI-NEXT: s_waitcnt vmcnt(9)
|
|
; SI-NEXT: v_readfirstlane_b32 s67, v34
|
|
; SI-NEXT: s_waitcnt vmcnt(8)
|
|
; SI-NEXT: v_readfirstlane_b32 s70, v35
|
|
; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v28
|
|
; SI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; SI-NEXT: s_waitcnt vmcnt(7)
|
|
; SI-NEXT: v_readfirstlane_b32 s80, v36
|
|
; SI-NEXT: s_waitcnt vmcnt(6)
|
|
; SI-NEXT: v_readfirstlane_b32 s53, v37
|
|
; SI-NEXT: s_waitcnt vmcnt(5)
|
|
; SI-NEXT: v_readfirstlane_b32 s52, v38
|
|
; SI-NEXT: s_waitcnt vmcnt(4)
|
|
; SI-NEXT: v_readfirstlane_b32 s64, v39
|
|
; SI-NEXT: s_waitcnt vmcnt(3)
|
|
; SI-NEXT: v_readfirstlane_b32 s66, v48
|
|
; SI-NEXT: s_waitcnt vmcnt(2)
|
|
; SI-NEXT: v_readfirstlane_b32 s48, v49
|
|
; SI-NEXT: s_waitcnt vmcnt(1)
|
|
; SI-NEXT: v_readfirstlane_b32 s39, v50
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: v_readfirstlane_b32 s51, v51
|
|
; SI-NEXT: s_cbranch_scc0 .LBB111_4
|
|
; SI-NEXT: ; %bb.1: ; %cmp.false
|
|
; SI-NEXT: s_and_b32 s4, s16, 0xff
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 16
|
|
; SI-NEXT: s_lshl_b32 s5, s17, 24
|
|
; SI-NEXT: s_or_b32 s77, s5, s4
|
|
; SI-NEXT: s_and_b32 s4, s18, 0xff
|
|
; SI-NEXT: s_lshl_b32 s4, s4, 16
|
|
; SI-NEXT: s_lshl_b32 s5, s6, 24
|
|
; SI-NEXT: s_or_b32 s78, s5, s4
|
|
; SI-NEXT: s_and_b32 s4, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s21, 8
|
|
; SI-NEXT: s_or_b32 s4, s4, s5
|
|
; SI-NEXT: s_and_b32 s5, s22, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s23, 24
|
|
; SI-NEXT: s_or_b32 s88, s6, s5
|
|
; SI-NEXT: s_and_b32 s5, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s25, 24
|
|
; SI-NEXT: s_or_b32 s79, s6, s5
|
|
; SI-NEXT: s_and_b32 s5, s26, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s6, s27, 24
|
|
; SI-NEXT: s_or_b32 s89, s6, s5
|
|
; SI-NEXT: s_and_b32 s5, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s29, 8
|
|
; SI-NEXT: s_or_b32 s5, s5, s6
|
|
; SI-NEXT: s_and_b32 s6, s10, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 24
|
|
; SI-NEXT: s_or_b32 s91, s7, s6
|
|
; SI-NEXT: s_and_b32 s6, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s15, 24
|
|
; SI-NEXT: s_or_b32 s90, s7, s6
|
|
; SI-NEXT: s_and_b32 s6, s12, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s11, 24
|
|
; SI-NEXT: s_or_b32 s92, s7, s6
|
|
; SI-NEXT: s_and_b32 s6, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s43, 8
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: s_and_b32 s7, s41, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s40, 24
|
|
; SI-NEXT: s_or_b32 s94, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s60, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s57, 24
|
|
; SI-NEXT: s_or_b32 s93, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s45, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s44, 24
|
|
; SI-NEXT: s_or_b32 s95, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s61, 8
|
|
; SI-NEXT: s_or_b32 vcc_lo, s7, s17
|
|
; SI-NEXT: s_and_b32 s7, s59, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s58, 24
|
|
; SI-NEXT: s_or_b32 s31, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s73, 24
|
|
; SI-NEXT: s_or_b32 s30, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s63, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s62, 24
|
|
; SI-NEXT: s_or_b32 s34, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s76, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s75, 8
|
|
; SI-NEXT: s_or_b32 vcc_hi, s7, s17
|
|
; SI-NEXT: s_and_b32 s7, s14, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s13, 24
|
|
; SI-NEXT: s_or_b32 s36, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s56, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s47, 24
|
|
; SI-NEXT: s_or_b32 s35, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s19, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s37, 24
|
|
; SI-NEXT: s_mov_b32 s9, s37
|
|
; SI-NEXT: s_or_b32 s37, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s8, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s51, 8
|
|
; SI-NEXT: s_or_b32 s71, s7, s17
|
|
; SI-NEXT: s_and_b32 s7, s39, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s48, 24
|
|
; SI-NEXT: s_or_b32 s49, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s66, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s64, 24
|
|
; SI-NEXT: s_or_b32 s38, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s52, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s53, 24
|
|
; SI-NEXT: s_or_b32 s50, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s80, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s70, 8
|
|
; SI-NEXT: s_or_b32 s83, s7, s17
|
|
; SI-NEXT: s_and_b32 s7, s67, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s68, 24
|
|
; SI-NEXT: s_or_b32 s55, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s85, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s84, 24
|
|
; SI-NEXT: s_or_b32 s54, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s81, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s82, 24
|
|
; SI-NEXT: s_or_b32 s65, s17, s7
|
|
; SI-NEXT: s_and_b32 s7, s99, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s98, 8
|
|
; SI-NEXT: s_or_b32 s16, s7, s17
|
|
; SI-NEXT: s_and_b32 s7, s86, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_lshl_b32 s17, s87, 24
|
|
; SI-NEXT: s_or_b32 s69, s17, s7
|
|
; SI-NEXT: s_lshl_b32 s17, s4, 16
|
|
; SI-NEXT: s_lshl_b32 s18, s5, 16
|
|
; SI-NEXT: s_lshl_b32 s7, s6, 16
|
|
; SI-NEXT: s_lshl_b32 s6, vcc_lo, 16
|
|
; SI-NEXT: s_lshl_b32 s97, vcc_hi, 16
|
|
; SI-NEXT: s_lshl_b32 s96, s71, 16
|
|
; SI-NEXT: s_lshl_b32 s83, s83, 16
|
|
; SI-NEXT: s_lshl_b32 s71, s16, 16
|
|
; SI-NEXT: s_cbranch_execnz .LBB111_3
|
|
; SI-NEXT: .LBB111_2: ; %cmp.true
|
|
; SI-NEXT: s_add_i32 s99, s99, 3
|
|
; SI-NEXT: s_and_b32 s4, s99, 0xff
|
|
; SI-NEXT: s_lshl_b32 s5, s98, 8
|
|
; SI-NEXT: s_add_i32 s86, s86, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s6, s86, 0xff
|
|
; SI-NEXT: s_addk_i32 s4, 0x300
|
|
; SI-NEXT: s_lshl_b32 s5, s87, 24
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_and_b32 s4, s4, 0xffff
|
|
; SI-NEXT: s_or_b32 s5, s5, s6
|
|
; SI-NEXT: s_add_i32 s85, s85, 3
|
|
; SI-NEXT: s_or_b32 s4, s5, s4
|
|
; SI-NEXT: s_and_b32 s5, s85, 0xff
|
|
; SI-NEXT: s_lshl_b32 s6, s84, 8
|
|
; SI-NEXT: s_add_i32 s81, s81, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: s_and_b32 s7, s81, 0xff
|
|
; SI-NEXT: s_addk_i32 s5, 0x300
|
|
; SI-NEXT: s_lshl_b32 s6, s82, 24
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_and_b32 s5, s5, 0xffff
|
|
; SI-NEXT: s_or_b32 s6, s6, s7
|
|
; SI-NEXT: s_add_i32 s80, s80, 3
|
|
; SI-NEXT: s_or_b32 s5, s6, s5
|
|
; SI-NEXT: s_and_b32 s6, s80, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s70, 8
|
|
; SI-NEXT: s_add_i32 s67, s67, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s17, s67, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s68, 24
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s17
|
|
; SI-NEXT: s_add_i32 s66, s66, 3
|
|
; SI-NEXT: s_or_b32 vcc_lo, s7, s6
|
|
; SI-NEXT: s_and_b32 s6, s66, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s64, 8
|
|
; SI-NEXT: s_add_i32 s52, s52, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s17, s52, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s53, 24
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s17
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_add_i32 s8, s8, 3
|
|
; SI-NEXT: s_add_i32 vcc_hi, s6, 0x3000000
|
|
; SI-NEXT: s_and_b32 s6, s8, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s51, 8
|
|
; SI-NEXT: s_add_i32 s39, s39, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s8, s39, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s48, 24
|
|
; SI-NEXT: s_lshl_b32 s8, s8, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s8
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_add_i32 s56, s56, 3
|
|
; SI-NEXT: s_add_i32 s8, s6, 0x3000000
|
|
; SI-NEXT: s_and_b32 s6, s56, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s47, 8
|
|
; SI-NEXT: s_add_i32 s19, s19, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s16, s19, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s9, 24
|
|
; SI-NEXT: s_lshl_b32 s16, s16, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s16
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_add_i32 s76, s76, 3
|
|
; SI-NEXT: s_add_i32 s16, s6, 0x3000000
|
|
; SI-NEXT: s_and_b32 s6, s76, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s75, 8
|
|
; SI-NEXT: s_add_i32 s14, s14, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_lshl_b32 s7, s13, 24
|
|
; SI-NEXT: s_and_b32 s13, s14, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s13, s13, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s13
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_add_i32 s74, s74, 3
|
|
; SI-NEXT: s_add_i32 s13, s6, 0x3000000
|
|
; SI-NEXT: s_and_b32 s6, s74, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s73, 8
|
|
; SI-NEXT: s_add_i32 s63, s63, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s14, s63, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s62, 24
|
|
; SI-NEXT: s_lshl_b32 s14, s14, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s14
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_add_i32 s72, s72, 3
|
|
; SI-NEXT: s_add_i32 s14, s6, 0x3000000
|
|
; SI-NEXT: s_and_b32 s6, s72, 0xff
|
|
; SI-NEXT: s_lshl_b32 s7, s61, 8
|
|
; SI-NEXT: s_add_i32 s59, s59, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s17, s59, 0xff
|
|
; SI-NEXT: s_addk_i32 s6, 0x300
|
|
; SI-NEXT: s_lshl_b32 s7, s58, 24
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s6, s6, 0xffff
|
|
; SI-NEXT: s_or_b32 s7, s7, s17
|
|
; SI-NEXT: s_add_i32 s60, s60, 3
|
|
; SI-NEXT: s_or_b32 s6, s7, s6
|
|
; SI-NEXT: s_and_b32 s7, s60, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s57, 8
|
|
; SI-NEXT: s_add_i32 s45, s45, 3
|
|
; SI-NEXT: s_or_b32 s7, s17, s7
|
|
; SI-NEXT: s_and_b32 s18, s45, 0xff
|
|
; SI-NEXT: s_addk_i32 s7, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s44, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_or_b32 s7, s17, s7
|
|
; SI-NEXT: s_add_i32 s46, s46, 3
|
|
; SI-NEXT: s_add_i32 s19, s7, 0x3000000
|
|
; SI-NEXT: s_and_b32 s7, s46, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s43, 8
|
|
; SI-NEXT: s_add_i32 s41, s41, 3
|
|
; SI-NEXT: s_or_b32 s7, s17, s7
|
|
; SI-NEXT: s_and_b32 s18, s41, 0xff
|
|
; SI-NEXT: s_addk_i32 s7, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s40, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s7, s7, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_add_i32 s42, s42, 3
|
|
; SI-NEXT: s_or_b32 s7, s17, s7
|
|
; SI-NEXT: s_and_b32 s17, s42, 0xff
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 8
|
|
; SI-NEXT: s_add_i32 s12, s12, 3
|
|
; SI-NEXT: s_or_b32 s15, s15, s17
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xff
|
|
; SI-NEXT: s_addk_i32 s15, 0x300
|
|
; SI-NEXT: s_lshl_b32 s11, s11, 24
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 16
|
|
; SI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; SI-NEXT: s_or_b32 s11, s11, s12
|
|
; SI-NEXT: v_readlane_b32 s12, v41, 13
|
|
; SI-NEXT: s_or_b32 s11, s11, s15
|
|
; SI-NEXT: s_add_i32 s28, s12, 3
|
|
; SI-NEXT: v_readlane_b32 s15, v41, 12
|
|
; SI-NEXT: s_and_b32 s12, s28, 0xff
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 8
|
|
; SI-NEXT: s_add_i32 s10, s10, 3
|
|
; SI-NEXT: s_or_b32 s12, s15, s12
|
|
; SI-NEXT: v_readlane_b32 s9, v41, 14
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xff
|
|
; SI-NEXT: s_addk_i32 s12, 0x300
|
|
; SI-NEXT: s_lshl_b32 s9, s9, 24
|
|
; SI-NEXT: s_lshl_b32 s10, s10, 16
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_or_b32 s9, s9, s10
|
|
; SI-NEXT: v_readlane_b32 s10, v41, 11
|
|
; SI-NEXT: s_or_b32 s9, s9, s12
|
|
; SI-NEXT: s_add_i32 s24, s10, 3
|
|
; SI-NEXT: v_readlane_b32 s12, v41, 10
|
|
; SI-NEXT: v_readlane_b32 s15, v41, 8
|
|
; SI-NEXT: s_and_b32 s10, s24, 0xff
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 8
|
|
; SI-NEXT: s_add_i32 s26, s15, 3
|
|
; SI-NEXT: s_or_b32 s10, s12, s10
|
|
; SI-NEXT: v_readlane_b32 s12, v41, 9
|
|
; SI-NEXT: s_and_b32 s15, s26, 0xff
|
|
; SI-NEXT: s_addk_i32 s10, 0x300
|
|
; SI-NEXT: s_lshl_b32 s12, s12, 24
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 16
|
|
; SI-NEXT: s_and_b32 s10, s10, 0xffff
|
|
; SI-NEXT: s_or_b32 s12, s12, s15
|
|
; SI-NEXT: s_or_b32 s10, s12, s10
|
|
; SI-NEXT: v_readlane_b32 s12, v41, 7
|
|
; SI-NEXT: s_add_i32 s20, s12, 3
|
|
; SI-NEXT: v_readlane_b32 s15, v41, 6
|
|
; SI-NEXT: v_readlane_b32 s17, v41, 4
|
|
; SI-NEXT: s_and_b32 s12, s20, 0xff
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 8
|
|
; SI-NEXT: s_add_i32 s22, s17, 3
|
|
; SI-NEXT: s_or_b32 s12, s15, s12
|
|
; SI-NEXT: v_readlane_b32 s15, v41, 5
|
|
; SI-NEXT: s_and_b32 s17, s22, 0xff
|
|
; SI-NEXT: s_addk_i32 s12, 0x300
|
|
; SI-NEXT: s_lshl_b32 s15, s15, 24
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 16
|
|
; SI-NEXT: s_and_b32 s12, s12, 0xffff
|
|
; SI-NEXT: s_or_b32 s15, s15, s17
|
|
; SI-NEXT: s_or_b32 s12, s15, s12
|
|
; SI-NEXT: v_readlane_b32 s15, v41, 3
|
|
; SI-NEXT: s_add_i32 s15, s15, 3
|
|
; SI-NEXT: v_readlane_b32 s17, v41, 2
|
|
; SI-NEXT: v_readlane_b32 s18, v41, 0
|
|
; SI-NEXT: s_and_b32 s15, s15, 0xff
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 8
|
|
; SI-NEXT: s_add_i32 s18, s18, 3
|
|
; SI-NEXT: s_or_b32 s15, s17, s15
|
|
; SI-NEXT: v_readlane_b32 s17, v41, 1
|
|
; SI-NEXT: s_and_b32 s18, s18, 0xff
|
|
; SI-NEXT: s_addk_i32 s15, 0x300
|
|
; SI-NEXT: s_lshl_b32 s17, s17, 24
|
|
; SI-NEXT: s_lshl_b32 s18, s18, 16
|
|
; SI-NEXT: s_and_b32 s15, s15, 0xffff
|
|
; SI-NEXT: s_or_b32 s17, s17, s18
|
|
; SI-NEXT: s_or_b32 s15, s17, s15
|
|
; SI-NEXT: s_add_i32 s4, s4, 0x3000000
|
|
; SI-NEXT: s_add_i32 s5, s5, 0x3000000
|
|
; SI-NEXT: s_add_i32 vcc_lo, vcc_lo, 0x3000000
|
|
; SI-NEXT: s_add_i32 s6, s6, 0x3000000
|
|
; SI-NEXT: s_add_i32 s7, s7, 0x3000000
|
|
; SI-NEXT: s_add_i32 s11, s11, 0x3000000
|
|
; SI-NEXT: s_add_i32 s9, s9, 0x3000000
|
|
; SI-NEXT: s_add_i32 s10, s10, 0x3000000
|
|
; SI-NEXT: s_add_i32 s12, s12, 0x3000000
|
|
; SI-NEXT: s_add_i32 s15, s15, 0x3000000
|
|
; SI-NEXT: s_and_b32 s78, s15, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s77, s15, 16
|
|
; SI-NEXT: s_and_b32 s88, s12, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s17, s12, 16
|
|
; SI-NEXT: s_and_b32 s89, s10, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s79, s10, 16
|
|
; SI-NEXT: s_and_b32 s91, s9, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s18, s9, 16
|
|
; SI-NEXT: s_and_b32 s92, s11, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s90, s11, 16
|
|
; SI-NEXT: s_and_b32 s94, s7, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s7, s7, 16
|
|
; SI-NEXT: s_and_b32 s95, s19, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s93, s19, 16
|
|
; SI-NEXT: s_and_b32 s31, s6, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s6, s6, 16
|
|
; SI-NEXT: s_and_b32 s34, s14, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s30, s14, 16
|
|
; SI-NEXT: s_and_b32 s36, s13, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s97, s13, 16
|
|
; SI-NEXT: s_and_b32 s37, s16, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s35, s16, 16
|
|
; SI-NEXT: s_and_b32 s49, s8, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s96, s8, 16
|
|
; SI-NEXT: s_and_b32 s50, vcc_hi, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s38, vcc_hi, 16
|
|
; SI-NEXT: s_and_b32 s55, vcc_lo, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s83, vcc_lo, 16
|
|
; SI-NEXT: s_and_b32 s65, s5, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s54, s5, 16
|
|
; SI-NEXT: s_and_b32 s69, s4, 0xffff0000
|
|
; SI-NEXT: s_lshl_b32 s71, s4, 16
|
|
; SI-NEXT: .LBB111_3: ; %end
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s78
|
|
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; SI-NEXT: v_mul_f32_e64 v0, 1.0, s77
|
|
; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], 16
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s88
|
|
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
|
|
; SI-NEXT: v_mul_f32_e64 v1, 1.0, s17
|
|
; SI-NEXT: v_lshr_b64 v[1:2], v[1:2], 16
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s89
|
|
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
|
|
; SI-NEXT: v_mul_f32_e64 v2, 1.0, s79
|
|
; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], 16
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s91
|
|
; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
|
|
; SI-NEXT: v_mul_f32_e64 v3, 1.0, s18
|
|
; SI-NEXT: v_lshr_b64 v[3:4], v[3:4], 16
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s92
|
|
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
|
|
; SI-NEXT: v_mul_f32_e64 v4, 1.0, s90
|
|
; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], 16
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s94
|
|
; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v5
|
|
; SI-NEXT: v_mul_f32_e64 v5, 1.0, s7
|
|
; SI-NEXT: v_lshr_b64 v[5:6], v[5:6], 16
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s95
|
|
; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6
|
|
; SI-NEXT: v_mul_f32_e64 v6, 1.0, s93
|
|
; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], 16
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s31
|
|
; SI-NEXT: v_lshrrev_b32_e32 v8, 16, v7
|
|
; SI-NEXT: v_mul_f32_e64 v7, 1.0, s6
|
|
; SI-NEXT: v_lshr_b64 v[7:8], v[7:8], 16
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s34
|
|
; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v8
|
|
; SI-NEXT: v_mul_f32_e64 v8, 1.0, s30
|
|
; SI-NEXT: v_lshr_b64 v[8:9], v[8:9], 16
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s36
|
|
; SI-NEXT: v_lshrrev_b32_e32 v10, 16, v9
|
|
; SI-NEXT: v_mul_f32_e64 v9, 1.0, s97
|
|
; SI-NEXT: v_lshr_b64 v[9:10], v[9:10], 16
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s37
|
|
; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10
|
|
; SI-NEXT: v_mul_f32_e64 v10, 1.0, s35
|
|
; SI-NEXT: v_lshr_b64 v[10:11], v[10:11], 16
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s49
|
|
; SI-NEXT: v_lshrrev_b32_e32 v12, 16, v11
|
|
; SI-NEXT: v_mul_f32_e64 v11, 1.0, s96
|
|
; SI-NEXT: v_lshr_b64 v[11:12], v[11:12], 16
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s50
|
|
; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v12
|
|
; SI-NEXT: v_mul_f32_e64 v12, 1.0, s38
|
|
; SI-NEXT: v_lshr_b64 v[12:13], v[12:13], 16
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s55
|
|
; SI-NEXT: v_lshrrev_b32_e32 v14, 16, v13
|
|
; SI-NEXT: v_mul_f32_e64 v13, 1.0, s83
|
|
; SI-NEXT: v_lshr_b64 v[13:14], v[13:14], 16
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s65
|
|
; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14
|
|
; SI-NEXT: v_mul_f32_e64 v14, 1.0, s54
|
|
; SI-NEXT: v_lshr_b64 v[14:15], v[14:15], 16
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s69
|
|
; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v15
|
|
; SI-NEXT: v_mul_f32_e64 v15, 1.0, s71
|
|
; SI-NEXT: v_readlane_b32 s30, v40, 34
|
|
; SI-NEXT: v_lshr_b64 v[15:16], v[15:16], 16
|
|
; SI-NEXT: v_readlane_b32 s31, v40, 35
|
|
; SI-NEXT: v_readlane_b32 s99, v40, 33
|
|
; SI-NEXT: v_readlane_b32 s98, v40, 32
|
|
; SI-NEXT: v_readlane_b32 s97, v40, 31
|
|
; SI-NEXT: v_readlane_b32 s96, v40, 30
|
|
; SI-NEXT: v_readlane_b32 s87, v40, 29
|
|
; SI-NEXT: v_readlane_b32 s86, v40, 28
|
|
; SI-NEXT: v_readlane_b32 s85, v40, 27
|
|
; SI-NEXT: v_readlane_b32 s84, v40, 26
|
|
; SI-NEXT: v_readlane_b32 s83, v40, 25
|
|
; SI-NEXT: v_readlane_b32 s82, v40, 24
|
|
; SI-NEXT: v_readlane_b32 s81, v40, 23
|
|
; SI-NEXT: v_readlane_b32 s80, v40, 22
|
|
; SI-NEXT: v_readlane_b32 s71, v40, 21
|
|
; SI-NEXT: v_readlane_b32 s70, v40, 20
|
|
; SI-NEXT: v_readlane_b32 s69, v40, 19
|
|
; SI-NEXT: v_readlane_b32 s68, v40, 18
|
|
; SI-NEXT: v_readlane_b32 s67, v40, 17
|
|
; SI-NEXT: v_readlane_b32 s66, v40, 16
|
|
; SI-NEXT: v_readlane_b32 s65, v40, 15
|
|
; SI-NEXT: v_readlane_b32 s64, v40, 14
|
|
; SI-NEXT: v_readlane_b32 s55, v40, 13
|
|
; SI-NEXT: v_readlane_b32 s54, v40, 12
|
|
; SI-NEXT: v_readlane_b32 s53, v40, 11
|
|
; SI-NEXT: v_readlane_b32 s52, v40, 10
|
|
; SI-NEXT: v_readlane_b32 s51, v40, 9
|
|
; SI-NEXT: v_readlane_b32 s50, v40, 8
|
|
; SI-NEXT: v_readlane_b32 s49, v40, 7
|
|
; SI-NEXT: v_readlane_b32 s48, v40, 6
|
|
; SI-NEXT: v_readlane_b32 s39, v40, 5
|
|
; SI-NEXT: v_readlane_b32 s38, v40, 4
|
|
; SI-NEXT: v_readlane_b32 s37, v40, 3
|
|
; SI-NEXT: v_readlane_b32 s36, v40, 2
|
|
; SI-NEXT: v_readlane_b32 s35, v40, 1
|
|
; SI-NEXT: v_readlane_b32 s34, v40, 0
|
|
; SI-NEXT: s_or_saveexec_b64 s[4:5], -1
|
|
; SI-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
|
|
; SI-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
|
|
; SI-NEXT: s_mov_b64 exec, s[4:5]
|
|
; SI-NEXT: s_waitcnt vmcnt(0)
|
|
; SI-NEXT: s_setpc_b64 s[30:31]
|
|
; SI-NEXT: .LBB111_4:
|
|
; SI-NEXT: s_mov_b32 s9, s37
|
|
; SI-NEXT: ; implicit-def: $sgpr77
|
|
; SI-NEXT: ; implicit-def: $sgpr78
|
|
; SI-NEXT: ; implicit-def: $sgpr17
|
|
; SI-NEXT: ; implicit-def: $sgpr88
|
|
; SI-NEXT: ; implicit-def: $sgpr79
|
|
; SI-NEXT: ; implicit-def: $sgpr89
|
|
; SI-NEXT: ; implicit-def: $sgpr18
|
|
; SI-NEXT: ; implicit-def: $sgpr91
|
|
; SI-NEXT: ; implicit-def: $sgpr90
|
|
; SI-NEXT: ; implicit-def: $sgpr92
|
|
; SI-NEXT: ; implicit-def: $sgpr7
|
|
; SI-NEXT: ; implicit-def: $sgpr94
|
|
; SI-NEXT: ; implicit-def: $sgpr93
|
|
; SI-NEXT: ; implicit-def: $sgpr95
|
|
; SI-NEXT: ; implicit-def: $sgpr6
|
|
; SI-NEXT: ; implicit-def: $sgpr31
|
|
; SI-NEXT: ; implicit-def: $sgpr30
|
|
; SI-NEXT: ; implicit-def: $sgpr34
|
|
; SI-NEXT: ; implicit-def: $sgpr97
|
|
; SI-NEXT: ; implicit-def: $sgpr36
|
|
; SI-NEXT: ; implicit-def: $sgpr35
|
|
; SI-NEXT: ; implicit-def: $sgpr37
|
|
; SI-NEXT: ; implicit-def: $sgpr96
|
|
; SI-NEXT: ; implicit-def: $sgpr49
|
|
; SI-NEXT: ; implicit-def: $sgpr38
|
|
; SI-NEXT: ; implicit-def: $sgpr50
|
|
; SI-NEXT: ; implicit-def: $sgpr83
|
|
; SI-NEXT: ; implicit-def: $sgpr55
|
|
; SI-NEXT: ; implicit-def: $sgpr54
|
|
; SI-NEXT: ; implicit-def: $sgpr65
|
|
; SI-NEXT: ; implicit-def: $sgpr71
|
|
; SI-NEXT: ; implicit-def: $sgpr69
|
|
; SI-NEXT: s_branch .LBB111_2
|
|
;
|
|
; VI-LABEL: bitcast_v64i8_to_v32bf16_scalar:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; VI-NEXT: v_readfirstlane_b32 s41, v30
|
|
; VI-NEXT: v_readfirstlane_b32 s14, v29
|
|
; VI-NEXT: v_readfirstlane_b32 s40, v28
|
|
; VI-NEXT: v_readfirstlane_b32 s12, v27
|
|
; VI-NEXT: v_readfirstlane_b32 s15, v26
|
|
; VI-NEXT: v_readfirstlane_b32 s10, v25
|
|
; VI-NEXT: v_readfirstlane_b32 s13, v24
|
|
; VI-NEXT: v_readfirstlane_b32 s8, v23
|
|
; VI-NEXT: v_readfirstlane_b32 s11, v22
|
|
; VI-NEXT: v_readfirstlane_b32 s7, v21
|
|
; VI-NEXT: v_readfirstlane_b32 s9, v20
|
|
; VI-NEXT: v_readfirstlane_b32 s6, v19
|
|
; VI-NEXT: v_readfirstlane_b32 s44, v18
|
|
; VI-NEXT: v_readfirstlane_b32 s42, v17
|
|
; VI-NEXT: v_readfirstlane_b32 s43, v16
|
|
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:76
|
|
; VI-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:8
|
|
; VI-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:4
|
|
; VI-NEXT: buffer_load_ushort v16, off, s[0:3], s32
|
|
; VI-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:72
|
|
; VI-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:68
|
|
; VI-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:64
|
|
; VI-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:60
|
|
; VI-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:56
|
|
; VI-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:52
|
|
; VI-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:48
|
|
; VI-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:44
|
|
; VI-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:40
|
|
; VI-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:36
|
|
; VI-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:32
|
|
; VI-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:28
|
|
; VI-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:24
|
|
; VI-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:20
|
|
; VI-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:16
|
|
; VI-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:12
|
|
; VI-NEXT: v_readfirstlane_b32 s74, v15
|
|
; VI-NEXT: v_readfirstlane_b32 s76, v14
|
|
; VI-NEXT: v_readfirstlane_b32 s72, v13
|
|
; VI-NEXT: v_readfirstlane_b32 s75, v12
|
|
; VI-NEXT: v_readfirstlane_b32 s62, v11
|
|
; VI-NEXT: v_readfirstlane_b32 s73, v10
|
|
; VI-NEXT: v_readfirstlane_b32 s60, v9
|
|
; VI-NEXT: v_readfirstlane_b32 s63, v8
|
|
; VI-NEXT: v_readfirstlane_b32 s58, v7
|
|
; VI-NEXT: v_readfirstlane_b32 s61, v6
|
|
; VI-NEXT: v_readfirstlane_b32 s47, v5
|
|
; VI-NEXT: v_readfirstlane_b32 s59, v4
|
|
; VI-NEXT: v_readfirstlane_b32 s46, v3
|
|
; VI-NEXT: v_readfirstlane_b32 s56, v2
|
|
; VI-NEXT: v_readfirstlane_b32 s45, v1
|
|
; VI-NEXT: v_readfirstlane_b32 s57, v0
|
|
; VI-NEXT: s_waitcnt vmcnt(14)
|
|
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v35
|
|
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; VI-NEXT: s_cbranch_scc0 .LBB111_4
|
|
; VI-NEXT: ; %bb.1: ; %cmp.false
|
|
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
|
|
; VI-NEXT: v_mov_b32_e32 v1, s19
|
|
; VI-NEXT: v_mov_b32_e32 v3, s23
|
|
; VI-NEXT: v_mov_b32_e32 v0, s17
|
|
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
|
|
; VI-NEXT: v_mov_b32_e32 v2, s21
|
|
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
|
|
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: v_or_b32_e32 v1, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s27
|
|
; VI-NEXT: v_mov_b32_e32 v2, s25
|
|
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
|
|
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_mov_b32_e32 v4, s45
|
|
; VI-NEXT: v_or_b32_e32 v2, v2, v3
|
|
; VI-NEXT: v_mov_b32_e32 v3, s29
|
|
; VI-NEXT: v_perm_b32 v4, s57, v4, v11
|
|
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_mov_b32_e32 v5, s47
|
|
; VI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
; VI-NEXT: v_mov_b32_e32 v4, s46
|
|
; VI-NEXT: v_perm_b32 v5, s59, v5, v11
|
|
; VI-NEXT: v_perm_b32 v4, s56, v4, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_mov_b32_e32 v6, s60
|
|
; VI-NEXT: v_or_b32_e32 v4, v4, v5
|
|
; VI-NEXT: v_mov_b32_e32 v5, s58
|
|
; VI-NEXT: v_perm_b32 v6, s63, v6, v11
|
|
; VI-NEXT: v_perm_b32 v5, s61, v5, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_mov_b32_e32 v7, s72
|
|
; VI-NEXT: v_or_b32_e32 v5, v5, v6
|
|
; VI-NEXT: v_mov_b32_e32 v6, s62
|
|
; VI-NEXT: v_perm_b32 v7, s75, v7, v11
|
|
; VI-NEXT: v_perm_b32 v6, s73, v6, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_mov_b32_e32 v8, s42
|
|
; VI-NEXT: v_or_b32_e32 v6, v6, v7
|
|
; VI-NEXT: v_mov_b32_e32 v7, s74
|
|
; VI-NEXT: v_perm_b32 v8, s43, v8, v11
|
|
; VI-NEXT: v_perm_b32 v7, s76, v7, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
|
|
; VI-NEXT: v_mov_b32_e32 v9, s7
|
|
; VI-NEXT: v_or_b32_e32 v7, v7, v8
|
|
; VI-NEXT: v_mov_b32_e32 v8, s6
|
|
; VI-NEXT: v_perm_b32 v9, s9, v9, v11
|
|
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
|
|
; VI-NEXT: v_mov_b32_e32 v10, s10
|
|
; VI-NEXT: v_or_b32_e32 v8, v8, v9
|
|
; VI-NEXT: v_mov_b32_e32 v9, s8
|
|
; VI-NEXT: v_perm_b32 v10, s13, v10, v11
|
|
; VI-NEXT: v_perm_b32 v9, s11, v9, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
|
|
; VI-NEXT: v_mov_b32_e32 v12, s14
|
|
; VI-NEXT: v_or_b32_e32 v9, v9, v10
|
|
; VI-NEXT: v_mov_b32_e32 v10, s12
|
|
; VI-NEXT: v_perm_b32 v12, s40, v12, v11
|
|
; VI-NEXT: v_perm_b32 v10, s15, v10, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; VI-NEXT: v_perm_b32 v12, v18, v17, s4
|
|
; VI-NEXT: v_perm_b32 v11, s41, v16, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: v_or_b32_e32 v11, v11, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
|
|
; VI-NEXT: v_or_b32_e32 v12, v13, v12
|
|
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
|
|
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
|
|
; VI-NEXT: v_or_b32_e32 v13, v14, v13
|
|
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
|
|
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
|
|
; VI-NEXT: v_or_b32_e32 v14, v15, v14
|
|
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
|
|
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
|
|
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
|
|
; VI-NEXT: v_or_b32_e32 v15, v35, v15
|
|
; VI-NEXT: s_cbranch_execnz .LBB111_3
|
|
; VI-NEXT: .LBB111_2: ; %cmp.true
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
|
|
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; VI-NEXT: v_perm_b32 v8, v0, v31, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(12)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v33
|
|
; VI-NEXT: v_perm_b32 v9, v0, v28, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(10)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v32
|
|
; VI-NEXT: v_perm_b32 v10, v0, v26, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(8)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v29
|
|
; VI-NEXT: v_perm_b32 v11, v0, v23, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(6)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v30
|
|
; VI-NEXT: v_perm_b32 v12, v0, v24, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(4)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v27
|
|
; VI-NEXT: v_perm_b32 v13, v0, v21, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(2)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v25
|
|
; VI-NEXT: v_perm_b32 v14, v0, v20, s4
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v22
|
|
; VI-NEXT: v_perm_b32 v15, v0, v19, s4
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v18
|
|
; VI-NEXT: v_perm_b32 v17, v0, v17, s4
|
|
; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
|
|
; VI-NEXT: s_add_i32 s40, s40, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s14
|
|
; VI-NEXT: v_perm_b32 v18, s40, v1, v0
|
|
; VI-NEXT: s_add_i32 s15, s15, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s12
|
|
; VI-NEXT: v_perm_b32 v19, s15, v1, v0
|
|
; VI-NEXT: s_add_i32 s13, s13, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s10
|
|
; VI-NEXT: v_perm_b32 v20, s13, v1, v0
|
|
; VI-NEXT: s_add_i32 s11, s11, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s8
|
|
; VI-NEXT: v_perm_b32 v21, s11, v1, v0
|
|
; VI-NEXT: s_add_i32 s9, s9, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
; VI-NEXT: v_perm_b32 v22, s9, v1, v0
|
|
; VI-NEXT: s_add_i32 s44, s44, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s6
|
|
; VI-NEXT: v_perm_b32 v23, s44, v1, v0
|
|
; VI-NEXT: s_add_i32 s43, s43, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s42
|
|
; VI-NEXT: v_perm_b32 v7, s43, v1, v0
|
|
; VI-NEXT: s_add_i32 s76, s76, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s74
|
|
; VI-NEXT: v_perm_b32 v24, s76, v1, v0
|
|
; VI-NEXT: s_add_i32 s75, s75, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s72
|
|
; VI-NEXT: v_perm_b32 v6, s75, v1, v0
|
|
; VI-NEXT: s_add_i32 s73, s73, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s62
|
|
; VI-NEXT: v_perm_b32 v25, s73, v1, v0
|
|
; VI-NEXT: s_add_i32 s63, s63, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s60
|
|
; VI-NEXT: v_perm_b32 v5, s63, v1, v0
|
|
; VI-NEXT: s_add_i32 s61, s61, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s58
|
|
; VI-NEXT: v_perm_b32 v26, s61, v1, v0
|
|
; VI-NEXT: s_add_i32 s59, s59, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s47
|
|
; VI-NEXT: v_perm_b32 v4, s59, v1, v0
|
|
; VI-NEXT: s_add_i32 s56, s56, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s46
|
|
; VI-NEXT: v_perm_b32 v27, s56, v1, v0
|
|
; VI-NEXT: s_add_i32 s57, s57, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s45
|
|
; VI-NEXT: v_perm_b32 v3, s57, v1, v0
|
|
; VI-NEXT: s_add_i32 s28, s28, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s29
|
|
; VI-NEXT: v_perm_b32 v28, s28, v1, v0
|
|
; VI-NEXT: s_add_i32 s26, s26, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s27
|
|
; VI-NEXT: v_perm_b32 v2, s26, v1, v0
|
|
; VI-NEXT: s_add_i32 s24, s24, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s25
|
|
; VI-NEXT: s_add_i32 s41, s41, 3
|
|
; VI-NEXT: v_perm_b32 v29, s24, v1, v0
|
|
; VI-NEXT: s_add_i32 s22, s22, 3
|
|
; VI-NEXT: v_mov_b32_e32 v1, s23
|
|
; VI-NEXT: s_add_i32 s20, s20, 3
|
|
; VI-NEXT: v_mov_b32_e32 v30, s21
|
|
; VI-NEXT: s_add_i32 s18, s18, 3
|
|
; VI-NEXT: v_mov_b32_e32 v31, s19
|
|
; VI-NEXT: s_add_i32 s16, s16, 3
|
|
; VI-NEXT: v_mov_b32_e32 v32, s17
|
|
; VI-NEXT: v_perm_b32 v16, s41, v16, v0
|
|
; VI-NEXT: v_perm_b32 v1, s22, v1, v0
|
|
; VI-NEXT: v_perm_b32 v30, s20, v30, v0
|
|
; VI-NEXT: v_perm_b32 v31, s18, v31, v0
|
|
; VI-NEXT: v_perm_b32 v0, s16, v32, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
|
|
; VI-NEXT: v_add_u32_e32 v28, vcc, 0x300, v28
|
|
; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, 0x300, v27
|
|
; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
; VI-NEXT: v_add_u32_e32 v26, vcc, 0x300, v26
|
|
; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x300, v25
|
|
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
|
|
; VI-NEXT: v_add_u32_e32 v24, vcc, 0x300, v24
|
|
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
|
; VI-NEXT: v_add_u32_e32 v30, vcc, 0x300, v30
|
|
; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x300, v0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
|
|
; VI-NEXT: v_add_u32_e32 v29, vcc, 0x300, v29
|
|
; VI-NEXT: v_or_b32_sdwa v3, v3, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v4, v4, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v5, v5, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v6, v6, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v7, v7, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v8
|
|
; VI-NEXT: v_add_u32_e32 v25, vcc, 0x300, v9
|
|
; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v10
|
|
; VI-NEXT: v_add_u32_e32 v27, vcc, 0x300, v11
|
|
; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x300, v13
|
|
; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v14
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x300, v15
|
|
; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v17
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x300, v16
|
|
; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v18
|
|
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x300, v19
|
|
; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v20
|
|
; VI-NEXT: v_add_u32_e32 v17, vcc, 0x300, v21
|
|
; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
|
|
; VI-NEXT: v_add_u32_e32 v18, vcc, 0x300, v23
|
|
; VI-NEXT: v_or_b32_sdwa v0, v31, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v1, v1, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v2, v2, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v8, v8, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v9, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v10, v10, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v11, v11, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v12, v12, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v13, v28, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v14, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_or_b32_sdwa v15, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x3000000, v0
|
|
; VI-NEXT: v_add_u32_e32 v1, vcc, 0x3000000, v1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x3000000, v2
|
|
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x3000000, v3
|
|
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x3000000, v4
|
|
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x3000000, v5
|
|
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x3000000, v6
|
|
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x3000000, v7
|
|
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x3000000, v8
|
|
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x3000000, v9
|
|
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x3000000, v10
|
|
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x3000000, v11
|
|
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x3000000, v12
|
|
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x3000000, v13
|
|
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x3000000, v14
|
|
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x3000000, v15
|
|
; VI-NEXT: .LBB111_3: ; %end
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_setpc_b64 s[30:31]
|
|
; VI-NEXT: .LBB111_4:
|
|
; VI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; VI-NEXT: s_branch .LBB111_2
|
|
;
|
|
; GFX9-LABEL: bitcast_v64i8_to_v32bf16_scalar:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX9-NEXT: v_readfirstlane_b32 s72, v30
|
|
; GFX9-NEXT: v_readfirstlane_b32 s56, v29
|
|
; GFX9-NEXT: v_readfirstlane_b32 s57, v28
|
|
; GFX9-NEXT: v_readfirstlane_b32 s61, v27
|
|
; GFX9-NEXT: v_readfirstlane_b32 s63, v26
|
|
; GFX9-NEXT: v_readfirstlane_b32 s7, v25
|
|
; GFX9-NEXT: v_readfirstlane_b32 s47, v24
|
|
; GFX9-NEXT: v_readfirstlane_b32 s58, v23
|
|
; GFX9-NEXT: v_readfirstlane_b32 s60, v22
|
|
; GFX9-NEXT: v_readfirstlane_b32 s6, v21
|
|
; GFX9-NEXT: v_readfirstlane_b32 s8, v20
|
|
; GFX9-NEXT: v_readfirstlane_b32 s9, v19
|
|
; GFX9-NEXT: v_readfirstlane_b32 s10, v18
|
|
; GFX9-NEXT: v_readfirstlane_b32 s11, v17
|
|
; GFX9-NEXT: v_readfirstlane_b32 s12, v16
|
|
; GFX9-NEXT: v_readfirstlane_b32 s15, v12
|
|
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:76
|
|
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:8
|
|
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:4
|
|
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32
|
|
; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:72
|
|
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:68
|
|
; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:64
|
|
; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:60
|
|
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:56
|
|
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:52
|
|
; GFX9-NEXT: buffer_load_ushort v30, off, s[0:3], s32 offset:48
|
|
; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:44
|
|
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:40
|
|
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:36
|
|
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:32
|
|
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:28
|
|
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:24
|
|
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:20
|
|
; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:16
|
|
; GFX9-NEXT: buffer_load_ushort v29, off, s[0:3], s32 offset:12
|
|
; GFX9-NEXT: v_readfirstlane_b32 s13, v15
|
|
; GFX9-NEXT: v_readfirstlane_b32 s73, v14
|
|
; GFX9-NEXT: v_readfirstlane_b32 s14, v13
|
|
; GFX9-NEXT: v_readfirstlane_b32 s40, v11
|
|
; GFX9-NEXT: v_readfirstlane_b32 s76, v10
|
|
; GFX9-NEXT: v_readfirstlane_b32 s41, v9
|
|
; GFX9-NEXT: v_readfirstlane_b32 s42, v8
|
|
; GFX9-NEXT: v_readfirstlane_b32 s43, v7
|
|
; GFX9-NEXT: v_readfirstlane_b32 s75, v6
|
|
; GFX9-NEXT: v_readfirstlane_b32 s44, v5
|
|
; GFX9-NEXT: v_readfirstlane_b32 s45, v4
|
|
; GFX9-NEXT: v_readfirstlane_b32 s46, v3
|
|
; GFX9-NEXT: v_readfirstlane_b32 s74, v2
|
|
; GFX9-NEXT: v_readfirstlane_b32 s59, v1
|
|
; GFX9-NEXT: v_readfirstlane_b32 s62, v0
|
|
; GFX9-NEXT: s_waitcnt vmcnt(19)
|
|
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
|
|
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
|
|
; GFX9-NEXT: s_cbranch_scc0 .LBB111_4
|
|
; GFX9-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, 0xc0c0004
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s21
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, s19
|
|
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s23
|
|
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s59
|
|
; GFX9-NEXT: v_perm_b32 v4, s62, v4, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s46
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s44
|
|
; GFX9-NEXT: v_perm_b32 v5, s45, v5, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s43
|
|
; GFX9-NEXT: v_perm_b32 v5, s75, v5, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s41
|
|
; GFX9-NEXT: v_perm_b32 v6, s42, v6, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s40
|
|
; GFX9-NEXT: v_perm_b32 v6, s76, v6, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s14
|
|
; GFX9-NEXT: v_perm_b32 v7, s15, v7, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s13
|
|
; GFX9-NEXT: v_perm_b32 v7, s73, v7, v8
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s11
|
|
; GFX9-NEXT: v_perm_b32 v9, s12, v9, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
|
|
; GFX9-NEXT: s_waitcnt vmcnt(18)
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v16
|
|
; GFX9-NEXT: s_waitcnt vmcnt(16)
|
|
; GFX9-NEXT: v_perm_b32 v10, s72, v18, v8
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
|
|
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v26
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v29, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v19
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v21, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v20
|
|
; GFX9-NEXT: v_perm_b32 v10, v31, v28, s4
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v23, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v30
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v33, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v22
|
|
; GFX9-NEXT: v_or_b32_sdwa v10, v25, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v24
|
|
; GFX9-NEXT: v_perm_b32 v10, v34, v32, s4
|
|
; GFX9-NEXT: v_or_b32_sdwa v9, v27, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
|
|
; GFX9-NEXT: v_mov_b32_e32 v9, s58
|
|
; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
|
|
; GFX9-NEXT: s_and_b32 s4, s47, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s5, s7, 8
|
|
; GFX9-NEXT: s_or_b32 s4, s4, s5
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
|
|
; GFX9-NEXT: s_and_b32 s4, s10, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s5, s9, 8
|
|
; GFX9-NEXT: s_or_b32 s4, s4, s5
|
|
; GFX9-NEXT: s_and_b32 s5, s8, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s77, s6, 8
|
|
; GFX9-NEXT: s_or_b32 s5, s5, s77
|
|
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
|
|
; GFX9-NEXT: s_and_b32 s5, s63, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s77, s61, 8
|
|
; GFX9-NEXT: s_or_b32 s5, s5, s77
|
|
; GFX9-NEXT: s_and_b32 s77, s57, 0xff
|
|
; GFX9-NEXT: s_lshl_b32 s78, s56, 8
|
|
; GFX9-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
|
|
; GFX9-NEXT: v_mov_b32_e32 v8, s4
|
|
; GFX9-NEXT: v_mov_b32_e32 v10, s5
|
|
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
|
|
; GFX9-NEXT: .LBB111_2: ; %cmp.true
|
|
; GFX9-NEXT: s_waitcnt vmcnt(12)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v34
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v8, v0, v32, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v27
|
|
; GFX9-NEXT: v_perm_b32 v9, v0, v24, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(8)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v33
|
|
; GFX9-NEXT: v_perm_b32 v10, v0, v30, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v25
|
|
; GFX9-NEXT: v_perm_b32 v11, v0, v22, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(4)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v31
|
|
; GFX9-NEXT: v_perm_b32 v12, v0, v28, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v23
|
|
; GFX9-NEXT: v_perm_b32 v13, v0, v20, s4
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v29
|
|
; GFX9-NEXT: v_perm_b32 v14, v0, v26, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v21
|
|
; GFX9-NEXT: v_perm_b32 v15, v0, v19, s4
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 3, v17
|
|
; GFX9-NEXT: v_mov_b32_e32 v19, 0xc0c0004
|
|
; GFX9-NEXT: v_perm_b32 v16, v0, v16, s4
|
|
; GFX9-NEXT: s_add_i32 s63, s63, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s61
|
|
; GFX9-NEXT: v_perm_b32 v17, s63, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s57, s57, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s56
|
|
; GFX9-NEXT: v_perm_b32 v20, s57, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s58
|
|
; GFX9-NEXT: v_perm_b32 v21, s60, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s21
|
|
; GFX9-NEXT: v_perm_b32 v0, s20, v0, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v1, 0x300, v0
|
|
; GFX9-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s23
|
|
; GFX9-NEXT: v_perm_b32 v0, s22, v0, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v0
|
|
; GFX9-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v0, s17
|
|
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v19
|
|
; GFX9-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s19
|
|
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
|
|
; GFX9-NEXT: v_perm_b32 v3, s18, v3, v19
|
|
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
|
|
; GFX9-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
|
|
; GFX9-NEXT: v_mov_b32_e32 v2, s25
|
|
; GFX9-NEXT: v_lshl_or_b32 v0, v3, 16, v0
|
|
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v19
|
|
; GFX9-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s27
|
|
; GFX9-NEXT: v_add_u32_e32 v2, 0x300, v2
|
|
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX9-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, s29
|
|
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v19
|
|
; GFX9-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s59
|
|
; GFX9-NEXT: v_add_u32_e32 v3, 0x300, v3
|
|
; GFX9-NEXT: v_perm_b32 v4, s62, v4, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
|
|
; GFX9-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
|
|
; GFX9-NEXT: v_mov_b32_e32 v4, s46
|
|
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v19
|
|
; GFX9-NEXT: s_add_i32 s45, s45, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s44
|
|
; GFX9-NEXT: v_add_u32_e32 v4, 0x300, v4
|
|
; GFX9-NEXT: v_perm_b32 v5, s45, v5, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX9-NEXT: s_add_i32 s75, s75, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
|
|
; GFX9-NEXT: v_mov_b32_e32 v5, s43
|
|
; GFX9-NEXT: v_perm_b32 v5, s75, v5, v19
|
|
; GFX9-NEXT: s_add_i32 s42, s42, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s41
|
|
; GFX9-NEXT: v_add_u32_e32 v5, 0x300, v5
|
|
; GFX9-NEXT: v_perm_b32 v6, s42, v6, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX9-NEXT: s_add_i32 s76, s76, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
|
; GFX9-NEXT: v_mov_b32_e32 v6, s40
|
|
; GFX9-NEXT: v_perm_b32 v6, s76, v6, v19
|
|
; GFX9-NEXT: s_add_i32 s15, s15, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s14
|
|
; GFX9-NEXT: v_add_u32_e32 v6, 0x300, v6
|
|
; GFX9-NEXT: v_perm_b32 v7, s15, v7, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v6
|
|
; GFX9-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
|
|
; GFX9-NEXT: v_mov_b32_e32 v7, s13
|
|
; GFX9-NEXT: v_perm_b32 v7, s73, v7, v19
|
|
; GFX9-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s11
|
|
; GFX9-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX9-NEXT: v_add_u32_e32 v7, 0x300, v7
|
|
; GFX9-NEXT: v_perm_b32 v22, s12, v22, v19
|
|
; GFX9-NEXT: v_perm_b32 v18, s72, v18, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v22, 0x300, v22
|
|
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
|
|
; GFX9-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v23, s9
|
|
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v12
|
|
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v14
|
|
; GFX9-NEXT: s_add_i32 s47, s47, 3
|
|
; GFX9-NEXT: v_lshl_or_b32 v7, v22, 16, v7
|
|
; GFX9-NEXT: v_mov_b32_e32 v22, s7
|
|
; GFX9-NEXT: v_perm_b32 v23, s10, v23, v19
|
|
; GFX9-NEXT: s_add_i32 s8, s8, 3
|
|
; GFX9-NEXT: v_mov_b32_e32 v24, s6
|
|
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v11
|
|
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v15
|
|
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v18
|
|
; GFX9-NEXT: v_and_b32_e32 v12, 0xffff, v12
|
|
; GFX9-NEXT: v_perm_b32 v22, s47, v22, v19
|
|
; GFX9-NEXT: v_perm_b32 v19, s8, v24, v19
|
|
; GFX9-NEXT: v_add_u32_e32 v24, 0x300, v8
|
|
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v9
|
|
; GFX9-NEXT: v_add_u32_e32 v26, 0x300, v10
|
|
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
|
|
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v16
|
|
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v17
|
|
; GFX9-NEXT: v_add_u32_e32 v9, 0x300, v21
|
|
; GFX9-NEXT: v_add_u32_e32 v8, 0x300, v23
|
|
; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX9-NEXT: v_lshl_or_b32 v12, v14, 16, v12
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff, v28
|
|
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v20
|
|
; GFX9-NEXT: v_add_u32_e32 v17, 0x300, v22
|
|
; GFX9-NEXT: v_add_u32_e32 v18, 0x300, v19
|
|
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v11, v15, 16, v11
|
|
; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
|
|
; GFX9-NEXT: v_and_b32_e32 v14, 0xffff, v26
|
|
; GFX9-NEXT: v_and_b32_e32 v15, 0xffff, v24
|
|
; GFX9-NEXT: v_lshl_or_b32 v8, v18, 16, v8
|
|
; GFX9-NEXT: v_lshl_or_b32 v9, v17, 16, v9
|
|
; GFX9-NEXT: v_lshl_or_b32 v10, v16, 16, v10
|
|
; GFX9-NEXT: v_lshl_or_b32 v14, v27, 16, v14
|
|
; GFX9-NEXT: v_lshl_or_b32 v15, v25, 16, v15
|
|
; GFX9-NEXT: .LBB111_3: ; %end
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX9-NEXT: .LBB111_4:
|
|
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX9-NEXT: s_branch .LBB111_2
|
|
;
|
|
; GFX11-TRUE16-LABEL: bitcast_v64i8_to_v32bf16_scalar:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_clause 0xf
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
|
|
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
|
|
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
|
|
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB111_4
|
|
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
|
|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
|
|
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
|
|
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
|
|
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
|
|
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
|
|
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
|
|
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
|
|
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
|
|
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
|
|
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB111_3
|
|
; GFX11-TRUE16-NEXT: .LBB111_2: ; %cmp.true
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
|
|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v50, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v5
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v24, s41, s7, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v27, s26, s27, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v2
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v29, s2, s3, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v30, s18, s19, v1
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v31, s16, s17, v1
|
|
; GFX11-TRUE16-NEXT: v_perm_b32 v32, s0, s1, v1
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v24
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v29
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v31
|
|
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v32
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v29.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v30.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v33.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v27.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v28.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v24.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v26.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v25.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v23.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v22.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v21.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v20.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v19.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v18.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v17.l
|
|
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v16.l
|
|
; GFX11-TRUE16-NEXT: .LBB111_3: ; %end
|
|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-TRUE16-NEXT: .LBB111_4:
|
|
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-TRUE16-NEXT: s_branch .LBB111_2
|
|
;
|
|
; GFX11-FAKE16-LABEL: bitcast_v64i8_to_v32bf16_scalar:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_clause 0xf
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:56
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v49, off, s32 offset:52
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v36, off, s32 offset:48
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v52, off, s32 offset:44
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v33, off, s32 offset:40
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v39, off, s32 offset:36
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v35, off, s32 offset:32
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v50, off, s32 offset:28
|
|
; GFX11-FAKE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v38, off, s32 offset:24
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v51, off, s32 offset:20
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v48, off, s32 offset:16
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v53, off, s32 offset:12
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v31, off, s32 offset:8
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v37, off, s32 offset:4
|
|
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s74, v30
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s59, v29
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s61, v28
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s63, v27
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s73, v26
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s45, v25
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s56, v24
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s62, v23
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s72, v22
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s42, v21
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s46, v20
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s57, v19
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s60, v18
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s41, v17
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s44, v16
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s47, v15
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s58, v14
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s9, v13
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s12, v12
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s15, v11
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s43, v10
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s8, v9
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s10, v8
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s13, v7
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s40, v6
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s5, v5
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s7, v4
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s11, v3
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s14, v2
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s4, v1
|
|
; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s6, v0
|
|
; GFX11-FAKE16-NEXT: s_mov_b32 s75, 0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(7)
|
|
; GFX11-FAKE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v54
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
|
|
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB111_4
|
|
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s41, 8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s77, s44, 0xff
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
|
|
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s40, s13, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
|
|
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
|
|
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
|
|
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
|
|
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
|
|
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
|
|
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v20
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v16, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
|
|
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
|
|
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB111_3
|
|
; GFX11-FAKE16-NEXT: .LBB111_2: ; %cmp.true
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v52
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 3, v50
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 3, v49
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v36, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 3, v51
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 3, v39
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v4, v48, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s43, s43, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v5, v38, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, v0, v31, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s73, s73, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s74, v34, 0xc0c0004
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s56, s45, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s7, s7, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s73, s63, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s44, s41, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s72, s62, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s60, s57, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s61, s61, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s43, s15, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s7, s5, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s61, s59, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s46, s42, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s12, s9, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s26, s27, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v28, s0, s1, v2
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s58, s47, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s40, s13, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s24, s25, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s20, s21, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v29, s16, s17, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v30, s2, s3, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s10, s8, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s28, s29, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v28
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v29
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
|
|
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v2
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v31, s22, s23, v2
|
|
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s18, s19, v2
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v30, 16, v28
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v29
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v32
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v32, 0xffff, v1
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
|
|
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v3
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v27, 16, v5
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v26, 16, v32
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v24
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v7
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v6
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v23, 16, v22
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v21, 16, v8
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v19
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v12
|
|
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v11
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v28
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v31, 16, v29
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v30
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v25, 16, v24
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v9, 16, v26
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v10, 16, v27
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v20, 16, v19
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v18, 16, v17
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v13
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v14, 16, v21
|
|
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v22
|
|
; GFX11-FAKE16-NEXT: .LBB111_3: ; %end
|
|
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
|
|
; GFX11-FAKE16-NEXT: .LBB111_4:
|
|
; GFX11-FAKE16-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
|
|
; GFX11-FAKE16-NEXT: s_branch .LBB111_2
|
|
%cmp = icmp eq i32 %b, 0
|
|
br i1 %cmp, label %cmp.true, label %cmp.false
|
|
|
|
cmp.true:
|
|
%a1 = add <64 x i8> %a, splat (i8 3)
|
|
%a2 = bitcast <64 x i8> %a1 to <32 x bfloat>
|
|
br label %end
|
|
|
|
cmp.false:
|
|
%a3 = bitcast <64 x i8> %a to <32 x bfloat>
|
|
br label %end
|
|
|
|
end:
|
|
%phi = phi <32 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]
|
|
ret <32 x bfloat> %phi
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|