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96 lines
5.3 KiB
Markdown
96 lines
5.3 KiB
Markdown
# hipDNN CPU Reference Implementation - Operation Support
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This document provides a comprehensive overview of the operations currently supported in the hipDNN CPU Reference Implementation and the details of their implementation support.
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> [!IMPORTANT]
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> ⚠️ **The CPU Reference Implementation is for testing and validation purposes only.** This implementation provides ground-truth results for validating GPU implementations and is not optimized for performance.
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## Purpose
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The CPU Reference Implementation serves as:
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- **Reference Implementation**: Provides ground-truth results for validating GPU implementations
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- **Testing Infrastructure**: Enables comprehensive testing of graph execution
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- **Validation Tool**: Ensures correctness of GPU-accelerated operations
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## Current Operation Support
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The following table lists all operations currently supported in the CPU Reference Implementation:
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| Operation | Datatypes | Layouts | Implementation | Notes |
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|-----------|-----------|---------|----------------|-------|
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| BatchNorm Forward Inference | FP16, BFP16, FP32 | NCHW, NHWC, NCDHW, NDHWC | CPU Reference | |
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| BatchNorm Forward Inference with Variance | FP16, BFP16, FP32 | NCHW, NHWC, NCDHW, NDHWC | CPU Reference | |
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| BatchNorm Forward Training | FP16, BFP16, FP32 | NCHW, NHWC, NCDHW, NDHWC | CPU Reference | |
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| BatchNorm Backward | FP16, BFP16, FP32 | NCHW, NHWC, NCDHW, NDHWC | CPU Reference | |
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| Convolution Backward Data | FP16, BFP16, FP32 | NCHW, NHWC, NCDHW, NDHWC | CPU Reference | |
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| Convolution Forward | FP16, BFP16, FP32 | NCHW, NHWC, NCDHW, NDHWC | CPU Reference | |
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| Convolution Backward Weights | FP16, BFP16, FP32 | NCHW, NHWC, NCDHW, NDHWC | CPU Reference | |
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| Matmul | FP16, BFP16, FP32 | NCHW, NCDHW | CPU Reference | |
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| Pointwise Unary | FP16, BFP16, FP32 | All | CPU Reference | |
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| Pointwise Binary | FP16, BFP16, FP32 | All | CPU Reference | |
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## Implementation Details
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### BatchNormalization Operations
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| Operation | Plan Builder | Signature Key | Description |
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|-----------|-------------|---------------|-------------|
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| BatchNorm Forward Inference | `BatchnormFwdInferencePlanBuilder` | `BatchnormFwdInferenceSignatureKey` | Inference-mode forward pass |
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| BatchNorm Forward Inference with Variance | `BatchnormFwdInferenceWithVariancePlanBuilder` | `BatchnormFwdInferenceWithVarianceSignatureKey` | Inference-mode with variance forward pass |
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| BatchNorm Forward Training | `BatchnormTrainPlanBuilder` | `BatchnormTrainSignatureKey` | Training-mode forward pass with statistics |
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| BatchNorm Backward | `BatchnormBwdPlanBuilder` | `BatchnormBwdSignatureKey` | Gradient computation |
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### Convolution Operations
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| Operation | Plan Builder | Signature Key | Description |
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|-----------|-------------|---------------|-------------|
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| Convolution Forward | `ConvolutionFwdPlanBuilder` | `ConvolutionFwdSignatureKey` | Forward convolution |
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| Convolution Backward Data | `ConvolutionBwdPlanBuilder` | `ConvolutionBwdSignatureKey` | Data gradient computation |
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| Convolution Backward Weights | `ConvolutionWrwPlanBuilder` | `ConvolutionWrwSignatureKey` | Weight gradient computation |
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### Matmul Operations
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| Operation | Plan Builder | Signature Key | Description |
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|-----------|-------------|---------------|-------------|
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| Matmul | `MatmulPlanBuilder` | `MatmulSignatureKey` | Generic matrix multiplication |
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### Pointwise Operations
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| Operation Type | Plan Builder | Signature Key | Supported Operations |
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|----------------|-------------|---------------|---------------------|
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| Unary Operations | `PointwisePlanBuilder` | `PointwiseSignatureKey` | RELU_FWD, SIGMOID_FWD, TANH_FWD, ABS, NEG |
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| Binary Operations | `PointwisePlanBuilder` | `PointwiseSignatureKey` | ADD, SUB, MUL, RELU_BWD, SIGMOID_BWD, TANH_BWD |
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| Ternary Operations | `PointwisePlanBuilder` | `PointwiseSignatureKey` | None Supported Yet |
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## Legend
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### Datatypes
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- **FP16**: Half-precision floating point (16-bit)
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- **BFP16**: Brain floating point (16-bit)
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- **FP32**: Single-precision floating point (32-bit)
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### Layouts
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- **NCHW**: Batch, Channels, Height, Width (2D, channel-first)
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- **NHWC**: Batch, Height, Width, Channels (2D, channel-last)
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- **NCDHW**: Batch, Channels, Depth, Height, Width (3D, channel-first)
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- **NDHWC**: Batch, Depth, Height, Width, Channels (3D, channel-last)
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> **Note:** The layout names (NCHW, NHWC, etc.) describe the **memory layout** controlled by
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> strides. Dimension ordering is operation-specific: convolution and batch normalization use
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> `(N, C, H, W)` / `(N, C, D, H, W)` ordering, matmul uses `(...batch, M, K)` ordering,
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> and pointwise operations are dimension-agnostic. See the
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> [Porting Guide](./PortingGuide.md#tensor-dimensions-and-layouts) for details.
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### Implementation
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- **CPU Reference**: CPU-based reference implementation for validation
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## Extension Guidelines
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For detailed information on adding new operations or datatypes to the CPU Reference Implementation, please refer to the [Extension Guidelines](./rfcs/0001_CpuGraphExecutorDesign.md#extension-guidelines) section in the CPU Graph Executor Design document.
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## Related Documentation
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- [hipDNN Operation Support](./OperationSupport.md) - Central hub for hipDNN operation support
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- [CPU Graph Executor Design](./rfcs/0001_CpuGraphExecutorDesign.md) - Detailed architecture documentation
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- [Testing Plan](./testing/TestPlan.md) - Testing strategy and procedures
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